JPH0682755B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0682755B2 JPH0682755B2 JP1156166A JP15616689A JPH0682755B2 JP H0682755 B2 JPH0682755 B2 JP H0682755B2 JP 1156166 A JP1156166 A JP 1156166A JP 15616689 A JP15616689 A JP 15616689A JP H0682755 B2 JPH0682755 B2 JP H0682755B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- impurity well
- regions
- impurity
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 239000012535 impurity Substances 0.000 claims description 120
- 239000000758 substrate Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 description 20
- 238000000034 method Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 15
- 230000010354 integration Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 239000005360 phosphosilicate glass Substances 0.000 description 8
- 241000293849 Cordylanthus Species 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［概 要］ 複数の不純物ウエル領域及び素子形成領域は、不純物ウ
エル領域よりも深く、且つ絶縁膜を埋め込んで形成され
たトレンチによりセルフアラインに画定され、前記不純
物ウエル領域は前記トレンチの側面部及び底部に形成さ
れた反対導電型の不純物領域により接続されている構造
に形成されているため、素子分離領域がバーズビークの
存在しない構造に形成できることによる素子領域の微細
化、ゲート酸化膜耐圧の改善及びキャリア寿命の改善
を、不純物ウエル領域がセルフアラインに形成できるこ
とによる不純物ウエル領域及び境界領域の微細化を、不
純物ウエル領域の絶縁膜分離によるラッチアップの改善
を、不純物ウエル領域間接続用の不純物領域をセルフア
ライン形成できることによる不純物ウエル領域の微細で
容易な接続を、ソースドレイン領域とチャネルストッパ
ー領域を分離できることによる接合容量の低減化及び接
合耐圧の改善を実現した半導体集積回路の形成を可能と
した半導体装置。DETAILED DESCRIPTION [Outline] A plurality of impurity well regions and element formation regions are self-aligned with trenches formed deeper than the impurity well regions and filled with an insulating film. Since it is formed in a structure connected by impurity regions of opposite conductivity type formed in the side surface and the bottom of the trench, the element isolation region can be miniaturized by forming a bird's beak structure isolation region, Improvement of breakdown voltage of gate oxide film and improvement of carrier life, miniaturization of impurity well region and boundary region by self-alignment of impurity well region, improvement of latch-up by isolation of insulating film of impurity well region, improvement of impurity well region Impurity wells that can form self-aligned impurity regions for connecting regions Fine and easy connection of frequency, the semiconductor device capable of forming a semiconductor integrated circuit that achieves improvements in reduction and junction breakdown voltage of the junction capacitance due to be separated source and drain regions and the channel stopper region.
［産業上の利用分野］ 本発明はMIS型半導体装置に係り、特に微細な不純物ウ
エルコンタクト領域を含む微細な不純物ウエル領域の画
定及び微細な素子分離領域の形成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device, and more particularly to demarcation of a fine impurity well region including a fine impurity well contact region and formation of a fine element isolation region.
LSI、超LSI等、高集積化されるMIS型半導体装置におい
ては、半導体素子の微細化に伴って素子分離領域が占め
る面積の比率が増大しつつあること、不純物ウエル領域
の形成がセルフアラインでないこと、不純物ウエル領域
への接続をおこなう不純物ウエルコンタクト領域が微細
でないこと等が高集積化への妨げになるという問題が顕
著になってきている。そこで微細な不純物ウエルコンタ
クト領域を含む不純物ウエル領域のセルフアライン化に
よる微細化及び素子分離領域の微細化を改善した比較的
簡略プロセスにより実現できる手段が要望されている。In highly integrated MIS type semiconductor devices such as LSI and VLSI, the ratio of the area occupied by the element isolation region is increasing with the miniaturization of the semiconductor element, and the formation of the impurity well region is not self-aligned. In particular, the problem that the impurity well contact region for connecting to the impurity well region is not minute and the like is an obstacle to high integration has become remarkable. Therefore, there is a demand for means that can be realized by a relatively simple process that improves the miniaturization of the impurity well region including the fine impurity well contact region by self-alignment and the miniaturization of the element isolation region.
［従来の技術］ 第４図は従来の半導体装置の模式側断面図で、51はｐ−
−型シリコン（Si）基板、52はｎ−型不純物ウエル領
域、53はｐ−型不純物ウエル領域、54はｎ型チャネルス
トッパー領域、55はｐ型チャネルストッパー領域、56は
フィールド酸化膜、57はｎ＋型ソースドレイン領域、58
はｐ＋型ソースドレイン領域、59はｐ＋型ウエルコンタ
クト領域、60はｎ＋型ウエルコンタクト領域、61はゲー
ト酸化膜、62はゲート電極、63はブロック用酸化膜、64
は燐珪酸ガラス（PSG）膜、65はAl配線を示している。[Prior Art] FIG. 4 is a schematic side sectional view of a conventional semiconductor device, and 51 is p-
-Type silicon (Si) substrate, 52 n-type impurity well region, 53 p-type impurity well region, 54 n-type channel stopper region, 55 p-type channel stopper region, 56 field oxide film, 57 n + type source / drain region, 58
Is a p + type source / drain region, 59 is a p + type well contact region, 60 is an n + type well contact region, 61 is a gate oxide film, 62 is a gate electrode, 63 is a block oxide film, and 64 is
Is a phosphosilicate glass (PSG) film, and 65 is an Al wiring.
同図においては、LOCOS法による素子分離を行ってお
り、素子形成領域と素子分離領域は比較的段差が少なく
形成できるが、バーズビークが生じるため、素子分離領
域の微細化には限界がきつつある。又、不純物ウエル領
域の画定に関しては、セルフアラインではないため、ｎ
−型不純物ウエル領域52とｐ−型不純物ウエル領域53の
間隔の決定には、両不純物ウエル領域形成用の不純物の
横方向拡散及び位置合せ誤差を考慮しなければならず、
微細化が行われていないし、LOCOS法によるウエルコン
タクト領域（59,60）の形成も高集積化の妨げとなって
いる。従来技術及び従来技術の延長では、素子形成領域
の微細化は可能であるが微細な不純物ウエルコンタクト
領域を含む不純物ウエル領域の微細化及び素子分離領域
の微細化ができないため高集積化が達成できないという
問題があった。In the figure, element isolation is performed by the LOCOS method, and the element formation region and the element isolation region can be formed with relatively few steps, but bird's beaks are generated, so miniaturization of the element isolation region is approaching its limit. Further, since the definition of the impurity well region is not self-alignment, n
In determining the distance between the − type impurity well region 52 and the p − type impurity well region 53, the lateral diffusion and alignment error of the impurities for forming both impurity well regions must be taken into consideration.
The miniaturization has not been carried out, and the formation of the well contact regions (59, 60) by the LOCOS method also hinders high integration. With the conventional technology and the extension of the conventional technology, it is possible to miniaturize the element formation region, but it is not possible to miniaturize the impurity well region including the fine impurity well contact region and the element isolation region, so that high integration cannot be achieved. There was a problem.
［発明が解決しようとする問題点］ 本発明が解決しようとする問題点は、従来例に示される
ように、極めて高集積な半導体集積回路を得るために、
微細な不純物ウエルコンタクト領域を含む不純物ウエル
領域のセルフアラインによる微細な画定及びLOCOS法に
よる素子分離領域の形成をしのぐ微細な素子分離領域の
形成を可能とした半導体装置の実現が困難であったこと
である。[Problems to be Solved by the Invention] A problem to be solved by the present invention is to obtain an extremely highly integrated semiconductor integrated circuit as shown in a conventional example.
It was difficult to realize a semiconductor device capable of forming a fine element isolation region that surpasses the fine definition of the impurity well region including the fine impurity well contact region by self-alignment and the formation of the element isolation region by the LOCOS method. Is.
［問題点を解決するための手段］ 上記問題点は、一導電型半導体基板に形成された複数の
反対導電型不純物ウエル領域及び素子形成領域が前記不
純物ウエル領域より深く及び絶縁膜を埋め込んで形成さ
れたトレンチにより画定され、且つ前記不純物ウエル領
域が前記トレンチの側面部及び底部に形成された反対導
電型不純物領域により接続されている本発明による半導
体装置によって解決される。[Means for Solving the Problems] The above-mentioned problem is that a plurality of opposite conductivity type impurity well regions and element formation regions formed in one conductivity type semiconductor substrate are formed deeper than the impurity well regions and the insulating film is buried. And the impurity well region is connected by the opposite conductivity type impurity regions formed at the side and bottom portions of the trench.
［作用］ 即ち本発明の半導体装置においては、複数の不純物ウエ
ル領域及び素子形成領域は、不純物ウエル領域よりも深
く、且つ絶縁膜を埋め込んで形成されたトレンチにより
セルフアラインに画定され、前記不純物ウエル領域は前
記トレンチの側面部及び底部に形成された反対導電型の
不純物領域により接続されている構造に形成されてい
る。したがって、素子分離領域を選択酸化によるいわゆ
るLOCOS法を使用せずに形成できるため、即ちストレス
を内在させるバーズビークの存在しない構造に形成でき
るため、微細な素子領域を形成できることによる高集積
化を、ゲート酸化膜の耐圧を改善できることによる高性
能化を、エレクトロン又はホールがトラップされにくく
なり、キャリア寿命を改善できることによる高信頼性を
可能にすることができる。又、不純物ウエル領域を絶縁
膜分離によりセルフアラインに形成できるため、微細な
不純物ウエルコンタクト領域を含む不純物ウエル領域及
び境界領域を形成できることによる高集積化を、ラッチ
アップを改善できることによる高性能化も可能にするこ
とができる。さらに、ソースドレイン領域とチャネルス
トッパー領域を分離して形成できるため、接合容量の低
減化による高速化及び接合耐圧を改善をできることによ
る高性能化をも可能にすることができる。即ち、極めて
高性能、高信頼、高速且つ高集積な半導体集積回路の形
成を可能とした半導体装置を得ることができる。[Operation] That is, in the semiconductor device of the present invention, the plurality of impurity well regions and the element formation regions are defined in a self-aligned manner by trenches formed deeper than the impurity well regions and filled with an insulating film. The region is formed in a structure connected by impurity regions of opposite conductivity type formed on the side surface and the bottom of the trench. Therefore, since the element isolation region can be formed without using the so-called LOCOS method by selective oxidation, that is, it can be formed in a structure where there is no bird's beak that causes stress, the high integration by forming a fine element region can be achieved. Higher performance due to the improvement of the breakdown voltage of the oxide film can be made possible because electrons or holes are less likely to be trapped and the carrier life can be improved, resulting in higher reliability. Further, since the impurity well region can be formed in a self-aligned manner by separating the insulating film, the high integration due to the formation of the impurity well region including the fine impurity well contact region and the boundary region, and the high performance due to the improvement of the latch-up can be achieved. You can enable it. Further, since the source / drain region and the channel stopper region can be formed separately, it is possible to achieve high speed by reducing the junction capacitance and high performance by improving the junction breakdown voltage. That is, it is possible to obtain a semiconductor device capable of forming a semiconductor integrated circuit having extremely high performance, high reliability, high speed, and high integration.
［実施例］ 以下本発明を、図示実施例により具体的に説明する。[Examples] The present invention will be specifically described below with reference to illustrated examples.
第１図は本発明の半導体装置における第１の実施例の模
式側断面図、第２図は本発明の半導体装置における第２
の実施例の模式側断面図、第３図（ａ）〜（ｅ）は本発
明の半導体装置における製造方法の一実施例の工程断面
図である。FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a second side view of the semiconductor device of the present invention.
3A to 3E are schematic cross-sectional side views of the embodiment of FIG. 3A and FIG. 3A to FIG. 3E are process cross-sectional views of the embodiment of the method for manufacturing the semiconductor device of the present invention.
全図を通じ同一対象物は同一符号で示す。The same object is denoted by the same symbol throughout the drawings.
第１図はｐ型シリコン（Si）基板を用いた際の本発明の
半導体装置における第１の実施例の模式側断面図で、１
は1015cm-3程度のｐ−−型シリコン（Si）基板、２は10
16cm-3程度のｎ−型不純物ウエル領域、３は1016cm-3程
度のｐ−型不純物ウエル領域、４はトレンチ、５はトレ
ンチ埋め込み絶縁膜、６は1016cm-3程度の不純物ウエル
領域間接続用のｎ−型不純物領域、７は1020cm-3程度の
ｎ＋型ソースドレイン領域、８は1020cm-3程度のｐ＋型
ソースドレイン領域、９は1020cm-3程度のｎ＋型不純物
ウエルコンタクト領域、10は15nm程度のゲート酸化膜、
11は300nm程度のゲート電極、12は50nm程度のブロック
用酸化膜、13は800nm程度の燐珪酸ガラス（PSG）膜、14
は１μｍ程度のAl配線を示している。FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention when a p-type silicon (Si) substrate is used.
Is 10 15 cm -3 of about p-- type silicon (Si) substrate, 2 10
N-type impurity well region of about 16 cm -3 , 3 is a p-type impurity well region of about 10 16 cm -3 , 4 is a trench, 5 is a trench buried insulating film, 6 is an impurity of about 10 16 cm -3 n- type impurity region for inter-well regions connected, 10 20 cm -3 of about n + -type source and drain regions 7, 8 10 20 cm -3 of about p + -type source and drain regions, 9 about 10 20 cm -3 N + type impurity well contact region, 10 is a gate oxide film of about 15 nm,
11 is a gate electrode of about 300 nm, 12 is a block oxide film of about 50 nm, 13 is a phosphosilicate glass (PSG) film of about 800 nm, 14
Indicates an Al wiring of about 1 μm.
同図においては、複数のｎ−型不純物ウエル領域２及び
素子形成領域はｎ−型不純物ウエル領域２より深く且つ
絶縁膜が埋め込まれて形成された微細なトレンチ（４、
５）によりセルフアラインに微細に画定されており、隣
接する複数のｎ−型不純物ウエル領域２はトレンチ
（４、５）の側面部及び底部に形成されたｎ−型不純物
領域６により接続されている。ｎ−型不純物ウエル領域
２の一部にはｎ＋型不純物ウエルコンタクト領域９が形
成されており、ｎ＋型不純物ウエルコンタクト領域９に
与えられたウエル電圧はｎ＋型不純物ウエルコンタクト
領域９を内蔵するｎ−型不純物ウエル領域２にｎ−型不
純物領域６を介して隣接する複数のｎ−型不純物ウエル
領域２に与えられており、すべてのｎ−型不純物ウエル
領域２は同電位になっている。又、トレンチ（４、５）
によりｎ−型不純物ウエル領域２とｐ−型不純物ウエル
領域３はセルフアラインに微細に分離されている。した
がって、素子分離領域を選択酸化によるLOCOS法を使用
せずに形成できるため、即ちストレスを内在させるバー
ズビークの存在しない構造に形成できるため、微細な素
子領域を形成できることによる高集積化を、ゲート酸化
膜の耐圧を改善できることによる高性能化を、エレクト
ロン又はホールがトラップされにくくなり、キャリア寿
命を改善できることによる高信頼性を可能にすることが
できる。又、不純物ウエル領域を絶縁膜分離によるセル
フアラインに形成できるため、微細な不純物ウエルコン
タクト領域を含む不純物ウエル領域及び境界領域を形成
できることによる高集積化を、ラッチアップを改善でき
ることによる高性能化も可能にすることができる。さら
に、ソースドレイン領域とチャネルストッパー領域を分
離して形成できるため、接合容量の低減化による高速化
及び接合耐圧を改善をできることによる高性能化をも可
能にすることができる。In the figure, a plurality of n − -type impurity well regions 2 and element forming regions are deeper than the n − -type impurity well region 2 and have fine trenches (4,
5) is finely self-aligned by 5), and a plurality of adjoining n-type impurity well regions 2 are connected by n-type impurity regions 6 formed on the side surfaces and bottoms of the trenches (4, 5). There is. An n + type impurity well contact region 9 is formed in a part of the n− type impurity well region 2, and the well voltage applied to the n + type impurity well contact region 9 includes the n + type impurity well contact region 9 built-in. The n-type impurity well regions 2 are provided to a plurality of n-type impurity well regions 2 adjacent to each other via the n-type impurity region 6, and all the n-type impurity well regions 2 have the same potential. Also, trenches (4,5)
Thus, the n-type impurity well region 2 and the p-type impurity well region 3 are finely self-aligned and separated. Therefore, since the element isolation region can be formed without using the LOCOS method by selective oxidation, that is, it can be formed in a structure where there is no bird's beak in which stress is inherent, it is possible to increase the degree of integration by forming a fine element region. Higher performance due to the improvement of the breakdown voltage of the film can be made possible because electrons or holes are less likely to be trapped and the carrier life can be improved to achieve higher reliability. Further, since the impurity well region can be formed in a self-aligned manner by isolation of the insulating film, the high integration due to the formation of the impurity well region and the boundary region including the fine impurity well contact region and the high performance due to the improvement of the latch-up can be achieved. You can enable it. Further, since the source / drain region and the channel stopper region can be formed separately, it is possible to achieve high speed by reducing the junction capacitance and high performance by improving the junction breakdown voltage.
第２図は本発明の半導体装置における第２の実施例の模
式側断面図で、１、３〜５、７、８、10〜14は第１図と
同じ物を、2aは第１のｎ−型不純物ウエル領域、2bは第
２のｎ−型不純物ウエル領域、6aは不純物ウエル領域間
接続用の第１のｎ−型不純物領域、6bは不純物ウエル領
域間接続用の第２のｎ−型不純物領域、9aは第１のｎ＋
型不純物ウエルコンタクト領域、9bは第２のｎ＋型不純
物ウエルコンタクト領域を示している。FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, in which 1, 3 to 5, 7, 8, 10 to 14 are the same as those in FIG. 1, and 2a is the first n. -Type impurity well region, 2b is a second n-type impurity well region, 6a is a first n-type impurity region for connecting between impurity well regions, and 6b is a second n-type for connecting between impurity well regions. Type impurity region, 9a is the first n +
A type impurity well contact region, 9b is a second n + type impurity well contact region.
同図においては、二種の異なるウエル電圧を持つｎ−型
不純物ウエル領域（2a,2b）を形成したもので、第１の
ｎ＋型不純物ウエルコンタクト領域9aに与えられた第１
のウエル電圧は第１のｎ−型不純物領域6aを介して第１
のｎ−型不純物ウエル領域2aに与えられ、一方、第２の
ｎ＋型不純物ウエルコンタクト領域9bに与えられた第２
のウエル電圧は第２のｎ−型不純物領域6bを介して第２
のｎ−型不純物ウエル領域2bに与えられている点を除き
第１図の同じである。第１図の効果にくわえ、異電位の
不純物ウエル領域の形成及び異電位の不純物ウエル領域
への接続の形成を容易に実現できる。In the figure, n-type impurity well regions (2a, 2b) having two different well voltages are formed, and the first n + type impurity well contact region 9a is provided with the first n + type impurity well regions (2a, 2b).
Well voltage of the first n-type impurity region 6a via the first
Of the second n + type impurity well contact region 9b, while being applied to the second n + type impurity well contact region 9b.
Well voltage of the second n-type impurity region 6b via the second
1. It is the same as FIG. 1 except that it is provided to the n-type impurity well region 2b. In addition to the effect of FIG. 1, it is possible to easily realize the formation of the impurity well region of different potential and the formation of the connection to the impurity well region of different potential.
次いで本発明に係る半導体装置の製造方法の一実施例に
ついて第３図（ａ）〜（ｅ）及び第１図を参照して説明
する。Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 (a) to 3 (e) and FIG.
第３図（ａ） ｐ−−型シリコン（Si）基板１に50nm程度の酸化膜15、
50nm程度の窒化膜16を順次成長させる。次いで通常のフ
ォトリソグラフィー技術を利用し、選択的に窒化膜16、
酸化膜15、ｐ−−型シリコン（Si）基板１をエッチング
しトレンチ４を形成する。次いで通常のフォトリソグラ
フィー技術を利用し、レジスト（図示せず）及び窒化膜
16をマスク層として、燐を回転イオン注入し、トレンチ
４の側面部及び底部にｎ−型不純物領域６を選択的に形
成する。FIG. 3 (a) An oxide film 15 of about 50 nm is formed on the p--type silicon (Si) substrate 1,
A nitride film 16 having a thickness of about 50 nm is sequentially grown. Next, using a normal photolithography technique, the nitride film 16 is selectively formed,
The oxide film 15 and the p--type silicon (Si) substrate 1 are etched to form trenches 4. Then, using a normal photolithography technique, a resist (not shown) and a nitride film are formed.
Using 16 as a mask layer, rotary ion implantation of phosphorus is performed to selectively form the n − -type impurity region 6 on the side surface and the bottom of the trench 4.
第３図（ｂ） 次いで化学気相成長法による絶縁膜５を成長させ、異方
性ドライエッチングによるトレンチ４に絶縁膜５を埋め
込む。FIG. 3 (b) Next, the insulating film 5 is grown by chemical vapor deposition, and the insulating film 5 is embedded in the trench 4 by anisotropic dry etching.
第３図（ｃ） 次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）及び絶縁膜５を埋め込んだトレンチ
（４、５）をマスク層として、燐をイオン注入してｎ−
型不純物ウエル領域２を、硼素をイオン注入してｐ−型
不純物ウエル領域３をそれぞれ選択的に画定する。次い
で高温処理を施すことにより深さを調整し、トレンチ４
より浅いｎ−型不純物ウエル領域２及びｐ−型不純物ウ
エル領域３を形成する。次いで窒化膜16、酸化膜15をエ
ッチング除去する。FIG. 3 (c) Next, using a normal photolithography technique, using a trench (4, 5) in which a resist (not shown) and an insulating film 5 are buried as a mask layer, phosphorus is ion-implanted to n-.
Boron is ion-implanted into the type impurity well regions 2 to selectively define the p-type impurity well regions 3. Then, a high temperature treatment is performed to adjust the depth and
A shallower n-type impurity well region 2 and a p-type impurity well region 3 are formed. Next, the nitride film 16 and the oxide film 15 are removed by etching.
第３図（ｄ） 次いで通常の技法を適用することによりゲート酸化膜10
及び多結晶シリコン膜11を成長する。次いで通常のフォ
トリソグラフィー技術を利用し、多結晶シリコン膜11を
パターニングして、ゲート電極11を形成する。FIG. 3 (d) Then, a gate oxide film 10 is formed by applying an ordinary technique.
And a polycrystalline silicon film 11 is grown. Then, the polycrystalline silicon film 11 is patterned by using a normal photolithography technique to form the gate electrode 11.
第３図（ｅ） 次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）、絶縁膜５及びゲート電極11をマスク
層として、砒素をイオン注入してｎ＋型ソースドレイン
領域７及びｎ＋型不純物ウエルコンタクト領域９を、硼
素をイオン注入してｐ＋型ソースドレイン領域８及びｐ
＋型不純物ウエルコンタクト領域（図示せず）をそれぞ
れ選択的に画定する。FIG. 3 (e) Then, using a normal photolithography technique, using a resist (not shown), the insulating film 5 and the gate electrode 11 as a mask layer, arsenic is ion-implanted to n + type source / drain regions 7 and n + type. Boron is ion-implanted into the impurity well contact region 9 to form p + type source / drain regions 8 and p.
+ Type impurity well contact regions (not shown) are selectively defined.
第１図 次いで不要部のゲート酸化膜10をエッチング除去する。
次いで通常の技法を適用することによりブロック用酸化
膜12及び燐珪酸ガラス（PSG）膜13の成長、高温熱処理
によるｎ＋型ソースドレイン領域７、ｎ＋型不純物ウエ
ルコンタクト領域９、ｐ＋型ソースドレイン領域８及び
ｐ＋型不純物ウエルコンタクト領域（図示せず）の深さ
の制御、電極コンタクト窓の形成、Al配線14の形成等を
おこなって半導体装置を完成する。FIG. 1 Next, the unnecessary portion of the gate oxide film 10 is removed by etching.
Then, by applying an ordinary technique, the blocking oxide film 12 and the phosphosilicate glass (PSG) film 13 are grown, and the n + type source / drain region 7, the n + type impurity well contact region 9 and the p + type source / drain region 8 are formed by the high temperature heat treatment. Then, the semiconductor device is completed by controlling the depth of the p + type impurity well contact region (not shown), forming the electrode contact window, forming the Al wiring 14, and the like.
以上実施例に示したように、本発明の半導体装置によれ
ば、素子分離領域を選択酸化によるLOCOS法を使用せず
に形成できるため、即ちストレスを内在させるバーズビ
ークの存在しない構造に形成できるため、微細な素子領
域を形成できることによる高集積化を、ゲート酸化膜の
耐圧を改善できることによる高性能化を、エレクトロン
又はホールがトラップされにくくなり、キャリア寿命を
改善できることによる高信頼性を可能にすることができ
る。又、不純物ウエル領域を絶縁膜分離によるセルフア
ラインに形成できるため、微細な不純物ウエルコンタク
ト領域を含む不純物ウエル領域及び境界領域を形成でき
ることによる高集積化を、ラッチアップを改善できるこ
とによる高性能化も可能にすることができる。さらに、
ソースドレイン領域とチャネルストッパー領域を分離し
て形成できるため、接合容量の低減化による高速化及び
接合耐圧を改善をできることによる高性能化をも可能に
することができる。As shown in the above examples, according to the semiconductor device of the present invention, it is possible to form the element isolation region without using the LOCOS method by selective oxidation, that is, it is possible to form a structure in which there is no bird's beak for internal stress. , High integration by forming a fine element region, high performance by improving the breakdown voltage of the gate oxide film, high reliability by making it difficult for electrons or holes to be trapped and improving the carrier life be able to. Further, since the impurity well region can be formed in a self-aligned manner by isolation of the insulating film, the high integration due to the formation of the impurity well region and the boundary region including the fine impurity well contact region and the high performance due to the improvement of the latch-up can be achieved. You can enable it. further,
Since the source / drain region and the channel stopper region can be formed separately, it is possible to reduce the junction capacitance to achieve higher speed and to improve the junction breakdown voltage, thereby improving performance.
［発明の効果］ 以上説明のように本発明によれば、MIS型半導体におい
て、複数の不純物ウエル領域及び素子形成領域を同一の
トレンチで画定し、且つトレンチの側面部及び底部に設
ける不純物領域により隣接する不純物ウエル領域間の接
続を達成する構造に形成できるため、素子分離領域がバ
ーズビークの存在しない構造に形成できることによる素
子領域の微細化、ゲート酸化膜耐圧の改善及びキャリア
寿命の改善を、不純物ウエル領域がセルフアラインの形
成できることによる不純物ウエル領域及び境界領域の微
細化を、不純物ウエル領域の絶縁膜分離によるラッチア
ップの改善を、不純物ウエル領域間接続用の不純物領域
をセルフアライン形成できることによる不純物ウエル領
域の微細で容易な接続を、ソースドレイン領域とチャネ
ルストッパー領域を分離できることによる接合容量の低
減化及び接合耐圧の改善をも可能にすることができる。
即ち、極めて高性能、高信頼、高速且つ高集積な半導体
集積回路の形成を可能とした半導体装置を得ることがで
きる。[Effects of the Invention] As described above, according to the present invention, in an MIS type semiconductor, a plurality of impurity well regions and element formation regions are defined by the same trench, and by the impurity regions provided on the side surface and the bottom of the trench. Since the element isolation region can be formed in a structure in which the connection between adjacent impurity well regions is achieved, the element isolation region can be formed in a structure in which no bird's beak exists, so that the element region is miniaturized, the gate oxide film withstand voltage is improved, and the carrier life is improved. Impurity well regions and boundary regions can be miniaturized because the well regions can be self-aligned, latchup can be improved by insulating film isolation of the impurity well regions, and impurity regions can be formed by self-aligning the impurity regions for connecting the impurity well regions. For fine and easy connection of the well region, the source / drain region and the channel By separating the topper region, it is possible to reduce the junction capacitance and improve the junction breakdown voltage.
That is, it is possible to obtain a semiconductor device capable of forming a semiconductor integrated circuit having extremely high performance, high reliability, high speed, and high integration.
第１図は本発明の半導体装置における第１の実施例の模
式側断面図、 第２図は本発明の半導体装置における第２の実施例の模
式側断面図、 第３図（ａ）〜（ｅ）は本発明の半導体装置における製
造方法の一実施例の工程断面図、 第４図は従来の半導体装置の模式側断面図である。 図において、 １はｐ−−型シリコン（Si）基板、 ２はｎ−型不純物ウエル領域、 2aは第１のｎ−型不純物ウエル領域、 2bは第２のｎ−型不純物ウエル領域、 ３はｐ−型不純物ウエル領域、 ４はトレンチ、 ５はトレンチ埋め込み絶縁膜、 ６は不純物ウエル領域間接続用のｎ−型不純物領域、 6aは不純物ウエル領域間接続用の第１のｎ−型不純物領
域、 6bは不純物ウエル領域間接続用の第２のｎ−型不純物領
域、 ７はｎ＋型ソースドレイン領域、 ８はｐ＋型ソースドレイン領域、 ９はｎ＋型不純物ウエルコンタクト領域、 9aは第１のｎ＋型不純物ウエルコンタクト領域、 9bは第２のｎ＋型不純物ウエルコンタクト領域、 10はゲート酸化膜、 11はゲート電極、 12はブロック用酸化膜、 13は燐珪酸ガラス（PSG）膜、 14はAl配線 を示す。FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of a semiconductor device of the present invention, and FIGS. e) is a process cross-sectional view of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 4 is a schematic side cross-sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate, 2 is an n-type impurity well region, 2a is a first n-type impurity well region, 2b is a second n-type impurity well region, and 3 is p-type impurity well region, 4 a trench, 5 a trench buried insulating film, 6 an n-type impurity region for connecting impurity well regions, 6a a first n-type impurity region for connecting impurity well regions , 6b is a second n-type impurity region for connection between impurity well regions, 7 is an n + type source / drain region, 8 is a p + type source / drain region, 9 is an n + type impurity well contact region, and 9a is a first n + type. Type impurity well contact region, 9b second n + type impurity well contact region, 10 gate oxide film, 11 gate electrode, 12 block oxide film, 13 phosphosilicate glass (PSG) film, 14 Al wiring Indicates.
Claims (2)
対導電型不純物ウエル領域及び素子形成領域が前記不純
物ウエル領域より深く及び絶縁膜を埋め込んで形成され
たトレンチにより画定され、且つ前記不純物ウエル領域
が前記トレンチの側面部及び底部に形成された反対導電
型不純物領域により接続されていることを特徴とする半
導体装置。1. A plurality of opposite-conductivity-type impurity well regions and element forming regions formed in a one-conductivity-type semiconductor substrate are defined by trenches formed deeper than the impurity well regions and having an insulating film buried therein, and the impurities. A semiconductor device, characterized in that the well regions are connected by impurity regions of opposite conductivity type formed on the side surface and the bottom of the trench.
反対導電型不純物ウエルコンタクト領域に与えられたウ
エル電圧が前記不純物ウエルコンタクト領域を内蔵する
前記不純物ウエル領域及び前記不純物領域を介して隣接
する不純物ウエル領域に与えられたことを特徴とする特
許請求の範囲第１項記載の半導体装置。2. A well voltage applied to an impurity well contact region of opposite conductivity type formed in a portion of the impurity well region is adjacent to the impurity well region containing the impurity well contact region and the impurity region. The semiconductor device according to claim 1, wherein the semiconductor device is provided in the impurity well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1156166A JPH0682755B2 (en) | 1989-06-19 | 1989-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1156166A JPH0682755B2 (en) | 1989-06-19 | 1989-06-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0321039A JPH0321039A (en) | 1991-01-29 |
| JPH0682755B2 true JPH0682755B2 (en) | 1994-10-19 |
Family
ID=15621796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1156166A Expired - Lifetime JPH0682755B2 (en) | 1989-06-19 | 1989-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682755B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5859466A (en) * | 1995-06-07 | 1999-01-12 | Nippon Steel Semiconductor Corporation | Semiconductor device having a field-shield device isolation structure and method for making thereof |
| KR100480604B1 (en) * | 2002-07-24 | 2005-04-06 | 삼성전자주식회사 | Method for fabricating shallow well of semiconductor device by low energy implantation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60235437A (en) * | 1984-05-09 | 1985-11-22 | Hitachi Ltd | Manufacture of semiconductor device |
-
1989
- 1989-06-19 JP JP1156166A patent/JPH0682755B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0321039A (en) | 1991-01-29 |
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