JPH0682792B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a bipolar static RAM semiconductor memory device having a PNP transistor as a load.

[Conventional technology]

Conventionally, a Schottky barrier diode (SBD) load switching type memory cell is often used in a bipolar semiconductor memory device in order to increase a read speed and a write speed. However, this storage device has a large SBD substrate occupation area and is weak in α-ray resistance, so that it is difficult to increase the storage capacity. Therefore, in recent large-capacity storage devices, cross-coupled PNPN storage cells using PNP transistors as loads, which are likely to be highly integrated, have come to be used.

FIG. 4 shows an equivalent circuit diagram of the cross-coupled PNPN memory cell, where one memory cell is a pair of multi-emitter NPN transistors Q ₁ and Q that form a flip-flop.
₂ and a pair of laterally-configured PNP transistors Q ₃ and Q ₄ that form a load. Here, D, a pair of digit lines, WT and WB are a top word line and a bottom word line, respectively. This memory cell is usually one NP
The N-transistor Q ₁ or Q ₂ and one PNP transistor Q ₃ or Q ₄ are respectively paired and arranged in parallel on the substrate, and are connected through aluminum wiring as shown in FIG.

FIG. 5 is a connection diagram of transistor element arrangement on the semiconductor substrate of the cross-coupled PNPN memory cell, which corresponds to FIG. That is, PNP transistors Q ₃ , Q
₄ is transistor Q ₁ , Q ₃ forming area 10 or transistor Q
₂ , Q ₄ formation region 20 Since each is formed in a lateral structure, the circuit connection between the NPN transistor Q ₁ or Q ₂ and the PNP transistor Q ₃ or Q ₄ is structurally formed in the substrate. Done.

FIG. 6 is a sectional view taken along the line AA 'in FIG. 5, showing that the circuit connection between the pair of NPN transistor Q ₁ and PNP transistor Q ₃ is structurally made in the substrate as described above. ing. That is, one PNP transistor Q ₃
Since the P-type diffusion region 4 having the base region of the PN transistor Q _{1 as} the collector region and the N-type epitaxial layer 3 having the collector region as the base region are laterally configured, the P-type diffusion layer 14 for the emitter region is formed. outer providing the formation of a new active region is, of course, not necessary interconnection between NPN transistor Q _1. Therefore, the connection by the aluminum wiring 30 is, for example, apparent from FIG. 5, between the hold / emitter diffusion layers 11 and 21 of the pair of NPN transistors Q ₁ and Q ₂ or the NPN transistor Q ₁ Base or PNP transistor Q ₃ collector extraction diffusion layer 1
2 and the collector of the NPN transistor Q ₂ or the base extraction diffusion layer 25 of the PNP transistor Q ₄ , etc., so that the cell structure is simpler and the integration capacity is increased compared to the SBD load switching type memory cell. It will be possible. The other reference numerals 1, 2, 5, 6 and 7 shown in FIG. 6 indicate well-known P-type silicon substrate, N ⁺ buried layer, field oxide film, element isolation region and channel stopper, respectively. is there.

[Problems to be solved by the invention]

By the way, the above-mentioned conventional cross-coupled PNPN memory cell, as is well known, includes a PNP transistor and an N
The memory operation is performed by turning on the PNPN thyristor formed with the PN transistor. At this time, the transistor saturates deeply, so 10-
It takes a very long time of about 20ns. That is, in order to latch the PNPN thyristor, the current gain (h _FEn ) of the NPN transistors Q ₁ and Q ₂ and the PNP transistor Q 2
_{This is because} the product (h _FEn × h _FEP ) of the current gain (h _FEP ) of ₃ and Q ₄ must be 1 or more. Therefore, in order to shorten the writing time, the current gain (h _FEn ) of the PNP transistors Q ₃ and Q ₄ should be reduced to the minimum necessary limit, and the collector operating current should be reduced so that the saturation level of the PNP transistor becomes shallow. It will be necessary to set it. However, in order to realize this with the conventional element structure as shown in FIG. 6, it is necessary to increase the base width of the lateral PNP transistors Q ₃ and Q ₄ , that is, the lateral expansion of the N-type epitaxial layer 3. Therefore, the cell area is increased. On the other hand, in order to reduce the current gain (h _FEP ) of the PNP transistors Q ₃ and Q ₄ without increasing the base width, the base concentration may be increased, but the thickness of the N-type epitaxial layer 3 used as the base region is large. Since it is deep, it is difficult to increase the concentration uniformly in the depth direction. Therefore, even if the concentration is increased only in the vicinity of the surface, if the collector current is large, the current wraps around to the deeper part of the base, so the current gain does not drop as expected and is not very effective. is not.

In view of the above situation, an object of the present invention is to reduce the current in the high current region without expanding the base width of the PNP load transistor, and to set the saturation of the PNP transistor to a shallow cross-coupled PNPN memory cell of high speed. It is to provide a semiconductor memory device including the.

[Means for solving problems]

The present invention is characterized in that a P-type silicon substrate, an N-type epitaxial layer on the P-type silicon substrate, a groove formed in the N-type epitaxial layer, an insulating film filling the groove, and an insulating film are provided. The N-type layer formed in contact with the bottom surface of the groove and the N-type epitaxial layer extending to a depth shallower than the groove and having one end along one side surface of the groove. A first P-type diffusion region that is deeply formed and has a deep diffusion portion that is joined to one side surface of the N-type layer;
The deep diffusion portion facing the deep diffusion portion of the first P-type diffusion region is deeply formed along the other side surface of the groove and has a deep diffusion portion that is joined to the other side surface of the N-type layer. Second P-type diffusion region formed in the epitaxial type epitaxial layer, and first and second N ⁺ layers formed in a portion of the first P-type diffusion region extending to a depth shallower than the groove. The N-type epitaxial layer, the first P-type diffusion region, the first N ⁺ layer and the second N ⁺ layer are respectively collector, base, hold-emitter and read-write-emitter. And a lateral PNP transistor having the first P-type diffusion region, the N-type layer and the second P-type diffusion region as a collector, a base and an emitter, respectively.
The multi-emitter NPN transistor and the lateral P
Cross-coupled PNPN consisting of a pair of NP transistors
A semiconductor memory device including a memory cell.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional structural view of an element of a cross-coupled PNPN memory cell showing an embodiment of the semiconductor memory device of the present invention.

This embodiment is compared with the conventional structure shown in FIG. 6, and the same parts are allotted with the same reference numerals as in FIG. Therefore, the semiconductor memory device of the present embodiment has the P-type silicon substrate 1
And an N-type epitaxial layer 3 on the P-type silicon substrate 1 and a P-type diffusion region 4 formed by providing a deep diffusion portion at one end in the N-type epitaxial layer 3 as a collector region and a base region, respectively. Further, in the N-type epitaxial layer 3 and the multi-emitter NPN transistor Q ₁ having the two N ⁺ layers in the P-type diffusion region 4 as the hold-emitter diffusion layer 11 and the read-write-emitter diffusion layer 13, respectively. A P-type diffusion layer 14 and a P-type diffusion layer 14 which are formed adjacent to each other by arranging a P-type diffusion region 4 and a deep diffusion portion facing each other, and an N-type layer which is in contact with the N ⁺ buried layer 2 and is shallowly filled between the two deep diffusion portions facing each other. 26 as emitter and base respectively,
It also includes a lateral PNP transistor Q ₃ having the P-type diffusion region 4 as a collector. Here, 27 is an upper silicon oxide film that determines the depth of the N-type layer 26. According to this embodiment, since the base of the PNP transistor is formed by the shallow N-type layer 26 whose concentration is uniformly controlled in the depth direction, the magnitude of its current gain (h _FEP ) is independent of that of the NPN transistor. Can be set to any value. That is, the saturation in the high current region of the lateral PNP transistor can be set to a shallow state by controlling the layer thickness and the concentration of the N-type layer 26, respectively.
It is possible to easily achieve the speedup of the PN memory cell.

The structure of this embodiment can be easily manufactured by the following steps.

FIGS. 2A to 2D are manufacturing process sequence diagrams of the above-described embodiment structure. That is, as shown in FIG. 2A, the N ⁺ buried layer 2 is first formed on the P-type silicon substrate 1, and then the N ⁺ buried layer 2 is formed.
The type epitaxial layer 3 is formed. Here, the element isolation region 6 is formed by trench isolation insulation, and after the channel stopper 7 is formed, the field oxide film 5 is further opened to form a high concentration N-type impurity diffusion layer 15 in the collector contact portion of the NPN transistor Q _1. Form. Then, as shown in FIG. 2B, a groove 28 is formed in the region where the base of the lateral PNP transistor Q ₃ is to be formed using a photoresist as a mask, and a P type diffusion layer 29 is formed along the inside of this groove 28. To do. At this time, the end of the groove 28 in the direction perpendicular to the drawing should be in contact with the groove wall of the element isolation region 6, and the P-type diffusion layer 29 should not be formed on the side surface lateral to the drawing. To do. Here, as shown in FIG. 2C, the N-type diffusion layer 26 is formed only on the bottom surface of the groove 28 by the ion implantation method, and the inside of the groove is buried with the silicon oxide film 27 or polycrystalline silicon. This causes the PNP transistor Q consisting of the N-type layer 26 along the groove wall.
A base of ₃ is formed. Furthermore, as shown in Fig. 2 (d), PNP
The P-type layers 14 and 4 serving as the emitter of the transistor Q _{3 and} the base of the NPN transistor Q ₁ are selectively formed by ion implantation, and then the N-types of the two read / write and hold emitter diffusion layers 13 and 11 are formed. By forming each layer and finally opening the contact of each electrode to form an aluminum electrode, the structure of the embodiment shown in FIG. 1 can be obtained.

As is clear from the above manufacturing process, the base layer (N-type layer 26) of the lateral PNP transistor has the groove 27 and the N ⁺ buried layer 2.
The current gain of the lateral PNP transistor Q ₃ can be controlled to be smaller than that of the conventional structure shown in FIG.
It is possible to set a desired value independently of the transistor.

FIG. 3 is a cross-sectional view of elements of a cross-coupled PNPN memory cell showing another embodiment of the semiconductor memory device of the present invention. In this embodiment, the N-type layer 2 that forms the base of the PNP transistor 2
Although 6 is not in contact with the N ⁺ buried layer 2, the same effect as that of the structure of the embodiment shown in FIG. 1 can be obtained.

〔The invention's effect〕

As described in detail above, according to the present invention, the base region of the PNP transistor element in the cross-coupled PNPN memory cell is structurally shallower than the conventional lateral PNP transistor, and the concentration in the depth direction is made uniform. Therefore, it is possible to obtain a low current gain with a narrow base width. Therefore, since the PNP transistor can operate in a state of shallow saturation, a significant effect can be obtained in realizing high-speed writing.

[Brief description of drawings]

FIG. 1 is a sectional view of an element of a cross-coupled PNPN memory cell showing an embodiment of the semiconductor memory device of the present invention, and FIG.
(D) is a manufacturing process sequence diagram of the structure of the above embodiment, FIG. 3 is a sectional view of a cross-coupled PNPN memory cell element showing another embodiment of the semiconductor memory device of the present invention, and FIG. 4 is the cross-coupled PNPN. FIG. 5 is an equivalent circuit diagram of the memory cell, FIG. 5 is a wiring diagram of transistor element arrangement on the semiconductor substrate of the cross-coupled PNPN memory cell, and FIG. 6 is a sectional view taken along the line AA ′ of FIG. 1 ... P-type silicon substrate, 2 ... N ⁺ buried layer, 3 ... N-type epitaxial layer, 4 ... P-type diffusion region, 5 ... field oxide film, 6 ... element isolation region, 7 ... Channel stopper, 11 …… NPN transistor Q ₁ hold-emitter diffusion layer, 12 …… NPN transistor Q ₁ base and P
Diffusion layer for collector collector of NP transistor Q ₃ , 13 …… NPN
Read / write emitter diffusion layer of transistor Q ₁ , 14
...... P-type diffusion layer that forms the emitter of PNP transistor Q ₃ , 15 …… NPNP transistor Q ₁ collector and PNP transistor Q ₃ base extraction diffusion layer, 21 …… NPN transistor Q ₂ hold-emitter diffusion layer , 22 …… Base of NPN transistor Q ₂ and collector extraction diffusion layer of PNP transistor Q ₄ , 23 …… Lead of NPN transistor Q ₂
Light / emitter diffusion layer, 24 ... P-type diffusion layer that forms the emitter of PNP transistor Q ₄ , 25 ... NPN transistor Q ₂ collector and PNP transistor Q ₄ base extraction diffusion layer, 26 ... N-type layer .

Claims (1)

[Claims] 1. A P-type silicon substrate, an N-type epitaxial layer on the P-type silicon substrate, a groove formed in the N-type epitaxial layer, an insulating film filling the groove, and contacting the insulating film. An N-type layer formed on the bottom surface of the groove,
It is formed in the N-type epitaxial layer so as to extend to a depth shallower than the groove, and one end of the groove is deeply formed along one side surface of the groove to be joined to one side surface of the N-type layer. A first P-type diffusion region having a deep diffusion portion, and a second P-type diffusion region facing the deep diffusion portion of the first P-type diffusion region and deeply formed along the other side surface of the groove. And a second P-type diffusion region formed in the N-type epitaxial layer having a deep diffusion portion that is joined to the side surface of the first P-type diffusion region and extending to a depth shallower than the groove of the first P-type diffusion region. A first and a second N ⁺ layer formed at a location, the N-type epitaxial layer, the first P-type diffusion region,
A multi-emitter NPN transistor having the first N ⁺ layer and the second N ⁺ layer as a collector, a base, a hold emitter and a read / write emitter, respectively, and the first P-type diffusion region, A lateral PNP transistor having the N-type layer and the second P-type diffusion region as a collector, a base and an emitter, respectively, is formed, and the multi-emitter NPN transistor and the lateral PNP transistor are formed.
Cross-coupled PNPN consisting of a pair of NP transistors
A semiconductor memory device including a memory cell.