JPH0752753B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a bipolar ECL.
Regarding RAM.

[Conventional technology]

Recently, speeding up and increasing the capacity of ECL RAM have been further promoted. In particular, in 4kbit ECL RAM, horizontal PNP load type memory cells are often used to meet such demands. The circuit of this PNP load type memory cell is shown in Fig. 4, and the transistors (hereinafter referred to as Tr) Q1 and Q3 in it.
A plan view of the above is shown in FIG. 5 (a), and a sectional view thereof is shown in FIG. 5 (b). F / F (flip
NPN Tr Q3, Q4 paired as the load of the flop) circuit
Are respectively cross-connected to the base and collector.
Also, the horizontal PNP Tr Q1 and Q2 base areas are Tr Q
It is shared with the collector area of 3, Q4.

[Problems to be solved by the invention]

Although the bipolar ECL RAM using the conventional lateral PNP load type memory cell described above is superior in terms of integration and power consumption, it is faster in performance than the one using the Schottky barrier diode load, especially in the memory cell. Was inferior in writing performance.

If the grounded emitter current amplification factor β of the horizontal PNP Tr shown in Fig. 4 is large, the base current i _B of the vertical NPN Tr Q3 on the ON side will be large and the saturation level will be high, so the write pulse width must be increased. There wasn't. Therefore, in order to speed up writing, it is necessary to reduce the gain β of the lateral PNP Trs Q1 and Q3 at the time of large writing current (collector current is several mA).

For this purpose, the base width of the horizontal PNP Tr is increased,
Measures such as reducing the injection efficiency into the base are taken.

However, if the gain β of the PNP Tr is made smaller and smaller to improve the writing performance, the holding operation becomes unstable. In order to stabilize the holding operation, the gain β must be increased in a small current region such as when holding. In other words, β of the lateral PNP Tr is small at large current (collector current is several mA) and small at small current (collector current is several tens of mA).
It is desirable to increase with mA).

As shown in Fig. 6, the β of the conventional Tr for PNP load has some of the above tendency, but the lower limit of the gain β is limited by β in the minimum current region, and β in the high current region becomes faster. However, there is a problem that β cannot be speeded up because β has a lower limit.

[Means for solving problems]

A semiconductor memory device according to the present invention is provided with a first and second first semiconductor layers selectively provided in the first conductivity type semiconductor layer of a semiconductor substrate having a first conductivity type semiconductor layer on a semiconductor substrate. A second conductivity type impurity layer, and first and second first conductivity type impurity layers selectively provided in the first second conductivity type impurity layer, respectively. A multi-emitter NPN (or PNP) vertical drive transistor in which the first conductivity type impurity layer, the first second conductivity type impurity layer, and the first conductivity type semiconductor layer are used as an emitter region, a base region, and a collector region, respectively. An inverter including a PNP lateral load transistor having the second second conductivity type impurity layer, the first conductivity type semiconductor layer, and the first second conductivity type impurity layer as an emitter region, a base region, and a collector region, respectively. Two input terminals In the semiconductor memory device including a memory cell constructed by intersecting the output end connected together,
The emitter electrode of the PNP (or NPN) lateral load transistor is connected to a remote part of the surface of the second second-conductivity-type impurity layer while avoiding a proximity part as viewed from the first second-conductivity-type impurity layer. The effective emitter width of the PNP (or NPN) lateral load transistor that is provided is smaller than that during the write operation due to the voltage drop of the second impurity layer of the second conductivity type.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a plan view of a semiconductor chip showing a main part of the first embodiment of the present invention, and FIG. 1 (b) is an A of FIG. 1 (a).
It is a sectional view taken along the line A-A '.

In this embodiment, the first and second P layers selectively provided in the N ⁻ type semiconductor layer 3 of the semiconductor substrate having the N ⁻ type semiconductor layer 3 on the P ⁻ type semiconductor substrate 1. ^- the type impurity layers 4 and 5,
First and second N ⁺ -type impurity layers 6 and 7, which are selectively provided in the first P ⁻ -type impurity layer 4, respectively, and the first and second N ⁺ -type impurity layers , A multi-emitter NPN vertical drive transistor (Q3 in FIG. 4) having a first P ⁻ -type impurity layer and an N ⁻ -type semiconductor layer as an emitter region, a base region, and a collector region, respectively, and a second P ⁻ -type impurity layer. Layer 5, N ^- type semiconductor layer 3
And two PNP lateral load transistors (Q1 in FIG. 4) having the first P ⁻ -type impurity layer 4 as the emitter region, the base region, and the collector region, respectively. In a semiconductor memory device including a Mommel cell configured to be connected, the emitter electrode E1 of the above-mentioned PNP lateral load transistor is located in the vicinity of the surface of the second P ⁻ -type impurity layer 5 when viewed from the first P ⁻ -type impurity layer. In order to avoid this, the effective emitter width of the PNP lateral load transistor described above is smaller than that during the holding operation due to the voltage drop of the second P ⁻ -type impurity layer 5.

Next, the manufacturing method of this embodiment will be described.

2A and 2B are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method according to the first embodiment of the present invention.

First, as shown in FIG. 2 (a), an N ⁺ -type semiconductor substrate 1 having a surface perpendicular to the crystal axis <111> and having a diameter of 4 inches and a specific resistance of 10 Ωcm is made of N ⁻ -type semiconductor substrate 1. A layer 2 is formed, and an N ⁻ type semiconductor layer 3 having a specific resistance of 5 Ωcm and a thickness of 1 μm is formed on the layer 2.
m, a semiconductor substrate epitaxially grown is prepared. Then, a silicon nitride film 1 having a thickness of 0.5 μm is formed on the N ⁻ type semiconductor layer 3.
2 is grown, a resist film 13 is applied, and exposed and developed.

Next, as shown in FIG. 2B, the resist film 12 is used as a mask to selectively etch a groove having a width of 1 μm until the P ⁻ type semiconductor substrate 1 is reached, and a PNP Tr and an NPN Tr are formed. The region forming the is separated from other regions. Silicon nitride film 12
Are removed, and thermal oxidation is performed at 1000 ° C. for 10 minutes to form a silicon oxide film 11 having a thickness of 400 nm.

Then, P ^- buried all grooves described above in the form of polysilicon, the height of which is the way made substantially the same as the semiconductor region. After the substantially flat surface, a silicon oxide film 11 and openings reach there from the high concentration N ⁺ impurity thermal diffusion N ⁺ -type buried layer N ⁺
A mold collector lead-out region 14 is formed. Then, boron is selectively ion-implanted using the resist film as a mask,
First, second P ⁻ -type impurity layers 4 and 5 are formed. The layer resistance of these layers is set to about 1500Ω / □. The N ⁻ type semiconductor layer 3 between the first and second P ⁻ type impurity layers 4 and 5 serves as the base region of the PNP Tr. The width of the second P ⁻ type impurity layer is the same as that of the emitter region of the conventional PNP Tr, but it is free to be widened or narrowed for convenience of the gain β. The length should be slightly longer than the emitter electrode of PNP Tr.

Next, as shown in FIG. 1B, high-concentration boron diffusion is selectively performed on the first and second P ⁻ -type impurity layers 4 and 5, respectively, to obtain a P ⁺ -type base region 8 and a P ⁺ -type base region. The emitter region 9 is formed. Then, high-concentration N ⁺ diffusion is selectively performed on the first P ⁻ -type impurity layer 1 to form the first and second N ⁺ -type impurity layers 7 and 6.

In FIG. 1B, for convenience, the silicon oxide film 11 is kept in this state.
The figure shows a state in which the emitter electrodes E1, E3, E4, the base electrode B3, and the collector electrode C3 are formed by forming holes in the substrate and depositing an Al electrode. Actually, the first layer of Al is used to form the circuit of FIG.
Although there are steps of wiring, interlayer insulating film, opening, and second layer Al wiring, they will not be described in detail again because they are not directly related to the description of the gist of the present invention.

Next, the gain β of the PNP lateral load transistor of this embodiment is
Will be described.

The second P ⁻ type impurity layer 5 and the P ⁺ type emitter region 9 and the layer resistances are set to 1500 Ω / □ and 30 Ω / □ respectively, and the emitter electrode E1
Seen from the P ⁺ type emitter region 9 and the second P ⁻ type impurity layer 5
The resistance values of 6Ω and 1200Ω are assumed to be 6Ω and 1200Ω, respectively.

First, the gain β _A in the low current region of the collector current I _C = 5 μA
Try to ask.

The potentials V _B and V _{C at} the left ends of the P ⁺ type emitter region 9 and the second P ⁻ type impurity layer 5 are respectively V _B = 6 × with reference to the potential V _A at the center of the P ⁺ type emitter region 9. 0.005 = 0.03mV, V _C = 1200
× 0.005 = 6mV. When the base-emitter forward voltage V _f of the PNP Tr is set to about 800 mV, the second P ⁻ -type impurity layer 5
, Hole injection can be performed from all regions on the left side of the central portion of the P ⁺ -type emitter region 9. At this time, the base width W _1A is almost equal to the distance between the first and second P ⁻ -type impurity layers 4 and 5, and if the diffusion length of holes in the N ⁻ -type semiconductor layer 3 is L _P ,
The current amplification factor β _A of PNP Tr at low current is If L _P = 6 μm and W _lA = 4 μm, then B _A = 3
Becomes

Since the vertical parasitic PNP has extremely low transmission efficiency,
Do not consider.

Next, let's find the current amplification factor β _B of the PNP Tr Q in the high current region (I _C = 1.5 mA).

When the emitter current is I _E = 1.5 mA, the above V _A , V _B , and V _C are V _A = 0, V _B = 6 × 1.5 = 9 mV, and V _C = 1200 × 1.5 = 1800 mV, respectively.
Becomes If V _{f is set} to about 900 mV, about half of the second P ⁻ type impurity layer 5 on the left side of the P ⁺ type emitter region 9 operates as an emitter. Therefore, most of the holes injected from the emitter are emitted from immediately below the P ⁺ type emitter region 9 and reach immediately below the P ⁺ type base region 8.
This distance is the base width W _1B . Some holes pass through the N ⁺ type buried layer 2, but the amount is extremely small. In the high current region, β is 1/1 / due to the effect of base conduction modulation and recombination.
If it decreases to k, the current amplification factor β _B of PNP Tr in the high current region is If W _1B = 13 μm and k = 10, then β _B = 0.925
Becomes Therefore, the gain β _B in the high current range is The writing performance of the PNP load type memory cell can be improved to about double.

FIG. 3 (a) is a plan view of a semiconductor chip showing the main part of the second embodiment of the present invention, and FIG. 3 (b) is an A in FIG. 3 (a).
It is a sectional view taken along the line A-A '.

In this embodiment, the second P ⁻ type impurity layer 5 ′ is shallower than the first P ⁻ type impurity layer 5 and has a layer resistance of 5 kΩ / □ and a narrow width, which is about 1/3 of the P ⁺ type emitter region 9. ing.

The gain β of the PNP lateral load transistor is about 3 in the low current region, which is almost the same as that in the first embodiment, but is about 3 in the high current region because the second P ⁻ -type impurity layer 5 ′ hardly contributes. 0.
It becomes 4 and smaller.

FIG. 6 shows a characteristic diagram showing the current dependency of β in the second embodiment. Note that I _H is a holding current of the memory cell and I _W is a writing current.

In the above embodiments, it is obvious that the conductivity types may be reversed, without detailed explanation again.

〔The invention's effect〕

As described above, according to the present invention, the emitter region which can be operated by disposing the emitter electrode on the surface of the lateral bipolar load transistor located away from the collector of the lateral bipolar load transistor is automatically changed according to the magnitude of the current, and the current amplification factor β is high. Since it can be set small in the current range and large in the low current range, the write characteristics of the lateral transistor load type memory cell can be greatly improved, and the speed can be increased.

In addition, β can be freely set by adjusting the shape such as width and length of the lateral load transistor, the depth and the dose amount, and the speed can be optimized. The gain β can be made more finely variable by setting a plurality of regions having different depths and impurity concentrations.

[Brief description of drawings]

FIG. 1 (a) is a plan view of a semiconductor chip showing a main part of the first embodiment of the present invention, and FIG. 1 (b) is an A of FIG. 1 (a).
2A and 2B are sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment of the present invention, and FIG. ) Is a plan view of a semiconductor chip showing a main part of a second embodiment of the present invention,
FIG. 3B is a sectional view taken along the line AA ′ of FIG.
FIG. 5 is a circuit diagram of a PNP load type memory cell, FIG. 5 (a) is a plan view of a semiconductor chip showing a main part of a conventional example, and FIG. 5 (b) is a line AA 'in FIG. 5 (a). A sectional view and FIG. 6 are characteristic diagrams showing the current dependence of the gain β of the lateral PNP transistor. 1 ...... P ^- type semiconductor substrate, 2 ...... N ⁺ -type buried layer, 3 ...... N ^- -type semiconductor layer, 4 ...... first P ^- -type impurity layer, 5 ...... second P ^-
Type impurity layer, 6 ... second N ⁺ type impurity layer, 7 ... first
N ⁺ -type impurity layer, 8 ... P ⁺ -type base region, 9 ... P ⁺ -type emitter region, 10 ... polysilicon, 11 ... silicon oxide film, 12 ... silicon nitride film, 13 ... resist film, 14……
Collector lead-out area, B1, B2 …… PNP transistor base electrode, B3 …… NPN transistor base electrode, C1, C2 ……
PNP transistor collector electrode, C3 ... NPN transistor collector electrode, D, D ... Digit line, E1, E2 ... PN
P transistor emitter electrode, E3 to E6 …… NPN transistor emitter electrode, Q1, Q2 …… PNP transistor, Q3, Q
4 …… NPN transistor, WT …… Word line (top), WB
...... Word line (bottom).

Claims (1)

[Claims] 1. A first and second second conductivity type selectively provided in the first conductivity type semiconductor layer of a semiconductor substrate having a first conductivity type semiconductor layer on a semiconductor substrate. An impurity layer and first and second first conductivity type impurity layers that are selectively provided in the first and second conductivity type impurity layers, respectively. First conductivity type impurity layer, the first
Multi-emitter NPN (or PNP) vertical drive transistor having a second conductivity type impurity layer and the first conductivity type semiconductor layer as an emitter region, a base region and a collector region, respectively, and the second second conductivity type impurity layer. , A PNP having the first conductive type semiconductor layer and the first second conductive type impurity layer as an emitter region, a base region and a collector region, respectively.
(Or NPN) lateral load transistors, and a semiconductor memory device including a memory cell configured by connecting two inverters each having an input terminal and an output terminal cross-connected to each other, wherein an emitter of the PNP (or NPN) lateral load transistor is provided. The electrode is provided so as to be connected to a remote portion of the surface of the second impurity layer of the second conductivity type, avoiding a proximity portion as viewed from the impurity layer of the first second conductivity type, and the second conductivity type of the second conductivity type. A semiconductor memory device, wherein the effective emitter width of the PNP (or NPN) lateral load transistor is smaller than that during a holding operation during a writing operation due to a voltage drop in an impurity layer.