JPH0682925B2 - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH0682925B2 JPH0682925B2 JP60054260A JP5426085A JPH0682925B2 JP H0682925 B2 JPH0682925 B2 JP H0682925B2 JP 60054260 A JP60054260 A JP 60054260A JP 5426085 A JP5426085 A JP 5426085A JP H0682925 B2 JPH0682925 B2 JP H0682925B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signal line
- layer
- lines
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 (発明の利用分野) 本発明はプリント配線板に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a printed wiring board.
(発明の背景) 従来のプリント配線板においては、たとえば実公昭57-5
2949号公報に記載され、かつ第2図および第3図に示す
如きもので、1は多層印刷板、2は内層の信号層にし
て、信号線2aから形成されている。3および4は搭載部
品の端子挿入穴および部品端子挿入ランドにして、互い
に直角な2方向(縦,横方向)の主基準格子線5a,5bの
交点5c上に配置されている。上記の構成であるから、た
とえば上記交点5c間の格子ピッチPを2.54mmにした場
合、1格子間の信号線2aの最大数nは従来一般に2本で
あったのを4本にすることが可能であり、同様に上記格
子ピッチPを1.27mmにした場合、1格子間の信号線2aの
最大数nは従来0で1本も通らなかったのを1乃至2本
通すことが可能になる。したがって印刷配線の密度を上
げることができるというものである。このように従来の
プリント配線板においては、印刷配線の高密度化につい
ての配慮がなされているが、異なった信号層の信号線相
互間を接続するための信号線接続専用のバイヤホールを
設ける場合に主基準格子線5a,5bの交点5c上に配置する
しかなく、高密度化が阻害されたり、万一主基準格子線
5a,5b間にバイヤホールを設けると、信号線2aの相互間
の間隙量を不均にする結果となり、結局間隙量を均一に
配置する配慮がなされていないこととなり絶縁特性が印
刷板1の位置によって差を発生し、全体の絶縁特性の低
下を招いていた。(Background of the Invention) In a conventional printed wiring board, for example, Japanese Utility Model Publication 57-5
As described in Japanese Patent No. 2949 and shown in FIGS. 2 and 3, 1 is a multilayer printed board and 2 is a signal layer of an inner layer, which is formed from a signal line 2a. Numerals 3 and 4 are terminal insertion holes and component terminal insertion lands, which are arranged on the intersection 5c of the main reference grid lines 5a, 5b in two directions (vertical and horizontal directions) perpendicular to each other. With the above configuration, for example, when the grating pitch P between the intersections 5c is set to 2.54 mm, the maximum number n of signal lines 2a between one grating can be set to four, which was generally two in the past. Similarly, when the grating pitch P is set to 1.27 mm, the maximum number n of signal lines 2a between one grating is 0, which is not 0 in the conventional case, but 1 or 2 can be passed. . Therefore, the density of the printed wiring can be increased. As described above, in the conventional printed wiring board, consideration is given to increasing the density of the printed wiring. However, when a via hole dedicated to signal line connection for connecting signal lines of different signal layers is provided. In addition, it must be placed on the intersection 5c of the main reference grid lines 5a and 5b, which may hinder high density,
If a via hole is provided between 5a and 5b, the amount of gap between the signal lines 2a becomes uneven, which means that no consideration is given to evenly arranging the amount of gap. A difference occurs depending on the position, which causes deterioration of the entire insulation characteristic.
(発明の目的) 本発明は前記従来の問題点を解決しプリント配線板全体
の絶縁特性を向上可能にしたプリント配線板を提供する
ことにある。(Object of the Invention) It is an object of the present invention to provide a printed wiring board which solves the above-mentioned conventional problems and can improve the insulating characteristics of the entire printed wiring board.
(発明の概要) 本発明は前記の目的を達成するため、同一平面上に互い
に略平行に配置された第一,第二の信号線を有する第一
の信号層と、第一の信号層と異なる平面上に互いに略平
行に配置された第三,第四の信号線を有する第二の信号
層と、前記第一の信号層における第一の信号線と第二の
信号層における第三の信号線とを電気的に接続する第一
のバイヤホールと、前記第一の信号層における第二の信
号線と第二の信号層における第四の信号線とを電気的に
接続する第二のバイヤホールとを備えている。そして、
第一の信号層の各信号線は、第二の信号層の各信号線に
対して交差するように配置され、前記第一のバイヤホー
ルは、第一の信号線と第三の信号線との交点より第二の
信号線及び第四の信号線に対し離れる方向にずらして設
けられ、前記第二のバイヤホールは、第二の信号線と第
四の信号線との交点より第一の信号線及び第三の信号線
に対し離れる方向にずらして設けられている。(Summary of the Invention) In order to achieve the above object, the present invention includes a first signal layer having first and second signal lines arranged on the same plane and substantially parallel to each other, and a first signal layer. A second signal layer having third and fourth signal lines arranged on different planes substantially parallel to each other, a first signal line in the first signal layer and a third signal line in the second signal layer. A first via hole for electrically connecting the signal line and a second signal line for electrically connecting the second signal line in the first signal layer and the fourth signal line in the second signal layer. It has a bay hall. And
Each signal line of the first signal layer is arranged so as to intersect with each signal line of the second signal layer, and the first via hole is a first signal line and a third signal line. Is provided in a direction away from the intersection of the second signal line and the fourth signal line, the second via hole, the first from the intersection of the second signal line and the fourth signal line The signal lines and the third signal line are provided so as to be displaced in the direction away from each other.
(発明の実施例) 以下本発明の実施例を示す第1図について説明する。な
お、従来と同一部分については第2図および第3図と同
一符号をもって示す。同図に示す如く、互いに直角な
縦,横2方向の主基準格子線5a,5bの交点5cに搭載部品
の端子挿入穴3および部品端子挿入ランド4を配置して
いる。これら搭載部品の端子挿入穴3および部品端子挿
入ランド4間の主基準格子線5a,5b間を5等分した位置
に副格子線6a,6bを配置しその中の最も中央部の隣接す
る2/5および3/5の副格子線6a,6b上に信号線2a,2b,およ
び信号線2c,2dを配置し、これらの信号線2a,2b,2c,2dの
交点から一定寸法外れた位置に上記搭載部品の端子挿入
穴3の穴径および部品端子挿入ランド4の径よりも小さ
な穴径の上記信号線2a,2b,2c,2d接続専用のバイヤホー
ル7を設けたものである。なお、一般に、信号線2a,2b
は同一信号層で、また信号線2c,2dは2a,2bとは別の信号
層面で形成される場合が多い。上記の構成であるから、
副格子線6a,6b上の信号線2a,2bおよび信号線2c,2dと、
これらの信号線2a,2bおよび信号線2c,2dの交点付近に配
置されたバイヤホール7との間の導体間隙量2eが隣接す
る2本の副格子線6a,6b上に信号線2a,2b,および信号線2
c,2dが平行して走る場合の信号線2a,2bの間隙量2fおよ
び信号線2c,2dの間隙量2fと略等しくなる。したがっ
て、バイヤホール7,7を夫々設けても、該バイヤホール
の外周によって信号線2a,2bの間隙量2f、および信号線2
c,2dの間隙量2fが部分的に狭くなることがなくなり、隣
接する信号線2aと2b、あるいは2cと2d間の間隙量は何れ
の場所でも平均化されるので、絶縁特性の面でも何れの
場合でも差が少くなり、これによってプリント基板の絶
縁特性を向上することができる。(Embodiment of the Invention) Hereinafter, FIG. 1 showing an embodiment of the present invention will be described. The same parts as in the prior art are indicated by the same reference numerals as in FIGS. 2 and 3. As shown in the figure, the terminal insertion hole 3 and the component terminal insertion land 4 of the mounted component are arranged at the intersection 5c of the main reference grid lines 5a and 5b in the vertical and horizontal directions perpendicular to each other. Sub-grid lines 6a and 6b are arranged at positions equally dividing the main reference grid lines 5a and 5b between the terminal insertion holes 3 and the component terminal insertion lands 4 of these mounted parts into two, which are adjacent to the most central part. The signal lines 2a, 2b and the signal lines 2c, 2d are arranged on the sub-lattice lines 6a, 6b of / 5 and 3/5, and the positions are deviated from the intersection of these signal lines 2a, 2b, 2c, 2d by a certain dimension. In addition, a via hole 7 dedicated to connecting the signal lines 2a, 2b, 2c, 2d having a hole diameter smaller than the diameter of the terminal insertion hole 3 of the mounted component and the diameter of the component terminal insertion land 4 is provided. In general, the signal lines 2a, 2b
Are often formed on the same signal layer, and the signal lines 2c and 2d are often formed on the surface of a signal layer different from 2a and 2b. Because of the above configuration,
Signal lines 2a, 2b and signal lines 2c, 2d on the sub-lattice lines 6a, 6b,
The conductor lines 2e between the signal lines 2a, 2b and the signal lines 2c, 2d and the via holes 7 disposed near the intersections of the signal lines 2a, 2b are arranged on the two sub-lattice lines 6a, 6b adjacent to each other. , And signal line 2
The gap amount 2f between the signal lines 2a and 2b and the gap amount 2f between the signal lines 2c and 2d when c and 2d run in parallel are substantially equal. Therefore, even if each of the via holes 7 and 7 is provided, the gap amount 2f between the signal lines 2a and 2b and the signal line 2 are determined by the outer circumference of the via hole.
The gap amount 2f between c and 2d does not become partially narrowed, and the gap amount between adjacent signal lines 2a and 2b or between 2c and 2d is averaged at any place, so that the insulation characteristics are not limited. In this case, the difference is small, and the insulating property of the printed circuit board can be improved.
(発明の効果) 本発明は以上述べたる如く、隣接する2個の信号線間の
間隙量を何れの場所にても均一化され、隣接する2個の
信号線間の電気絶縁的な負荷も均一化され、これによっ
て絶縁特性の面でも場所による違いを減少してプリント
配線板の絶縁特性を向上することができる。また搭載部
品の端子挿入穴および部品端子挿入ランド間に信号線を
複数個配置して印刷配線の高密度を行なう場合でも、隣
接する2個の信号線間に高電圧を印加することを可能に
することができる。(Effect of the Invention) As described above, according to the present invention, the gap amount between two adjacent signal lines is made uniform at any place, and an electrically insulating load between two adjacent signal lines is also provided. It is uniformized, and thereby, the difference in the insulating property depending on the place can be reduced and the insulating property of the printed wiring board can be improved. Further, even when a plurality of signal lines are arranged between the terminal insertion holes of the mounted parts and the component terminal insertion lands to achieve high density of the printed wiring, it is possible to apply a high voltage between two adjacent signal lines. can do.
第1図は本発明の一実施例を示すプリント配線板の平面
図、第2図は従来のプリント配線板の平面図、第3図は
その縦断面図である。 1……多層印刷板、2……信号層、2a,2b,2c,2d……信
号線、3……搭載部品の端子挿入穴、4……部品端子挿
入ランド、5a,5b……主基準格子線、6a,6b……副格子
線、7……バイヤホール。FIG. 1 is a plan view of a printed wiring board showing an embodiment of the present invention, FIG. 2 is a plan view of a conventional printed wiring board, and FIG. 3 is a longitudinal sectional view thereof. 1 ... Multilayer printing board, 2 ... Signal layer, 2a, 2b, 2c, 2d ... Signal line, 3 ... Mounting terminal terminal insertion hole, 4 ... Component terminal insertion land, 5a, 5b ... Main standard Lattice line, 6a, 6b ... Sub-lattice line, 7 ... Buyer hole.
Claims (2)
一,第二の信号線を有する第一の信号層と、第一の信号
層と異なる平面上に互いに略平行に配置された第三,第
四の信号線を有する第二の信号層と、前記第一の信号層
における第一の信号線と第二の信号層における第三の信
号線とを電気的に接続する第一のバイヤホールと、前記
第一の信号層における第二の信号線と第二の信号層にお
ける第四の信号線とを電気的に接続する第二のバイヤホ
ールとを備え、第一の信号層の各信号線は、第二の信号
層の各信号線に対して交差するように配置され、前記第
一のバイヤホールは、第一の信号線と第三の信号線との
交点より第二の信号線及び第四の信号線に対し離れる方
向にずらして設けられ、前記第二のバイヤホールは、第
二の信号線と第四の信号線との交点より第一の信号線及
び第三の信号線に対し離れる方向にずらして設けられた
ことを特徴とするプリント配線板。1. A first signal layer having first and second signal lines arranged substantially parallel to each other on the same plane, and arranged substantially parallel to each other on a plane different from the first signal layer. A first signal layer electrically connecting a second signal layer having third and fourth signal lines, a first signal line in the first signal layer and a third signal line in the second signal layer And a second via hole for electrically connecting the second signal line in the first signal layer and the fourth signal line in the second signal layer, the first signal layer Each of the signal lines is arranged so as to intersect with each of the signal lines of the second signal layer, and the first via hole is located at a second point from the intersection of the first signal line and the third signal line. Of the second signal line and the fourth signal line in a direction away from each other. Printed circuit board, characterized in that provided displaced in the direction away from the intersection between the signal line to the first signal line and the third signal line.
第一の信号線と第二の信号線との信号線間と、第三の信
号線と第四の信号との信号線間とが略均一となるようず
らして設けられたことを特徴とする特許請求の範囲第1
項記載のプリント配線板。2. Each of the first and second via holes,
The first signal line and the second signal line, the signal line between the signal line, and the third signal line and the signal line between the fourth signal are arranged so as to be substantially uniform Claims No. 1
The printed wiring board according to the item.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60054260A JPH0682925B2 (en) | 1985-03-20 | 1985-03-20 | Printed wiring board |
| CA000501578A CA1237820A (en) | 1985-03-20 | 1986-02-11 | Multilayer printed circuit board |
| US06/828,717 US4636919A (en) | 1985-03-20 | 1986-02-12 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60054260A JPH0682925B2 (en) | 1985-03-20 | 1985-03-20 | Printed wiring board |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9121393A Division JPH0680901B2 (en) | 1993-04-19 | 1993-04-19 | Printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61214498A JPS61214498A (en) | 1986-09-24 |
| JPH0682925B2 true JPH0682925B2 (en) | 1994-10-19 |
Family
ID=12965590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60054260A Expired - Fee Related JPH0682925B2 (en) | 1985-03-20 | 1985-03-20 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682925B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5543639B2 (en) * | 1973-12-29 | 1980-11-07 | ||
| JPS55103793A (en) * | 1979-01-31 | 1980-08-08 | Nippon Electric Co | Through hole printed circuit board |
| JPS5927079Y2 (en) * | 1979-12-27 | 1984-08-06 | 日本電気株式会社 | wiring board |
| JPS58184783A (en) * | 1982-04-22 | 1983-10-28 | 日本電気株式会社 | Printed circuit board |
| JPS59131171U (en) * | 1983-02-23 | 1984-09-03 | 日本電気株式会社 | printed wiring board |
-
1985
- 1985-03-20 JP JP60054260A patent/JPH0682925B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61214498A (en) | 1986-09-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |