JPH0683050B2 - Amplitude conversion circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit (hereinafter referred to as Bi-CMOS integrated circuit) in which a bipolar transistor circuit and a C-MOSFET circuit are integrated on the same semiconductor substrate, In particular, the present invention relates to an amplitude conversion circuit for converting the logic amplitude of an ECL logic circuit using bipolar transistors into the logic amplitude of a logic circuit using C-MOSFET in a logic circuit.

[Conventional technology]

In recent years, the ECL logic circuit, which has been frequently used in supercomputers and measuring instruments due to its high speed, often has its logic amplitude set from 260 mVp-p to 500 mVp-p. Since it is remarkably smaller than the logic amplitude of the logic circuit, it is necessary to amplify the logic amplitude of the ECL when connecting to the most general C-MOS circuit as the logic circuit.

In the Bi-CMOS integrated circuit, the circuit shown in FIG. 5 has been conventionally used. The transistors 25 and 26, the resistors 27 and 28, and the constant current source 33 form an ECL buffer, and signals having phases different from each other by 180 ° are obtained from both ends of the resistors 27 and 28. The transistors 29 and 31 are MOS P-channel FETs.
When transistor 26 is on and transistor 25 is off, resistance
28 is the resistance value of R ₂₈ and the current value of the current source 33 is I ₃₃ , and the collector voltage of the transistor 26 is only R ₂₈ and I _33.
Will fall below V _CC . Therefore, the gate-source voltage V _GS29 of _{MOSFET 29} is V _GS29 = R ₂₈ × I ₃₃ . MOSFET31 gate,
The source-to-source voltage V _GS31 is “0V” because the transistor 25 is off. Therefore, MOSFET 29 is ON and MOSFET ₃₁ is OFF, which can be expressed as I _D29 = K (W / L) × (V _GS29 −Vt) ² (W: gate width, L: gate length, K: transconductance parameter, Vt: threshold Value voltage, I _D29 MOSFET2
9 drain current). I _D29 drives the N-type MOSFET 30 whose drain and gate are short-circuited, and makes the current mirror pair with the N-type MOSFET 32 conductive. At this time, the P-type MOSFET 31
Since it is OFF, the voltage V ₃₅ of the output terminal 35 is V ₃₅ ≈0.

Conversely, if transistor 25 is on and transistor 26 is off,
The P-type MOSFET 29 turns off, and as a result, the N-type MOSFET 32 also turns off.
On the contrary, since the P-type MOSFET 31 is turned on, V ₃₅ ≈V _CC . resistance
The logic amplitude of ECL generated at both ends of 27 and 28 is now C-MOS.
It is converted into the logic amplitude of the logic circuit.

[Problems to be solved by the invention]

In the conventional amplitude conversion circuit, in order to enhance the driving capacity of the capacitive load at the output terminal 35, the W of the MOSFETs 31 and 32 must be increased. Since it is smaller than the N-type MOSFET, it requires a large W which is 2 to 3 times as large as that of the N-type MOSFET. Naturally, a large C-MOSFET having a high load driving capability has a large gate input capacitance, so that it is necessary to increase W in the MOSFETs 29 and 30 to improve the load driving force. In the conventional circuit, the W of all MOSFETs must be increased in order to obtain a large fan-out, and there is a drawback that the speed of the circuit is impaired.

[Means for solving problems]

The amplitude conversion circuit of the present invention is a differential amplifier including first and second bipolar transistors, a constant current source, and first and second load resistors respectively connected to the collectors of the first and second bipolar transistors. And at least one of the bases of the first and second bipolar transistors is applied with a signal voltage sufficient to alternately cut off the first and second bipolar transistors to make them conductive. The source of the bipolar transistor is connected to the collector, the gate is connected to the collector of the second bipolar transistor, and the drain has the same conductivity characteristics as the first and second bipolar transistors, and the collector is connected to the first potential. And a first MOSFET connected to the base of the third bipolar transistor, which is cut off when the first MOSFET is turned on, The gate and the source respectively have a collector of the first or second bipolar transistor and a second MOSFET connected to the first potential so as to be conductive when the MOSFET is cut off. MO
The drain and the drain of the SFET are connected to the gate and drain of the third MOSFET that is complementary to the second MOSFET, and the gates of the fourth and fifth MOSFETs of the same conductivity type as the third MOSFET. Sources of the fourth and fifth MOSFETs are connected to a second potential, the fourth and fifth MOSFETs form respective current mirror pairs with respect to the third MOSFET, and the second MOSFET is cut off. Then, the third, fourth, and fifth MOSFETs are cut off, and when the second MOSFET is turned on, a connection is made so that the third, fourth, and fifth MOSFETs are also turned on, and the third bipolar transistor is turned on. The emitter of is connected to the other end of the third resistor whose one end is connected to the second potential and the fourth MOSF.
The drain of ET is connected, and the output is taken out from the emitter of the third bipolar transistor.

〔Example〕

FIG. 1 is a circuit diagram of the first embodiment of the present invention. ECL with transistors 1 and 2 and resistors 3 and 4 with resistance value Rc and constant current source 6
Form a buffer. A P-type MOSFET 5 opens and closes the base bias current path of the bipolar transistor 7. N type MO
SFET11 is driven by a current mirror circuit consisting of C-MOSFETs 9 and 10, and turns on when transistor 7 is off and output terminal 13
It plays the role of pulling down the voltage of 0V. N-type MOSFET 12 is MO
Like SFET11, it is driven by a current mirror circuit consisting of C-MOSFETs 9 and 10, and when the transistor 7 turns off, turn O
The base charge of the transistor 7 is extracted and the transition time when the transistor 7 is turned off is shortened.

P-type M when transistor 1 turns on and transistor 2 turns off
Since the source potential of the OSFET 5 becomes almost equal to the voltage V _{CC of the} power supply 14 and the gate voltage becomes V _CC -RcI ₆ , the P-type MOSFET 5 turns on and the base bias is applied to the transistor 7 to start the operation as an emitter follower. Since the gate and source voltage V _GS of the P-type MOSFET 9 is 0V at this time, it is cut off and the N-type MOSFETs 10, 11 and 12 are also turned off. Therefore, output terminal 13
From the perspective, it looks as if it is operating as the circuit of FIG. In the figure, 5'corresponds to the ON resistance of the P-type MOSFET 5.

Now, returning to FIG. 1, when the transistor 1 is turned off, the collector potentials of the transistor 2 and the transistor 1 are reversed,
FET5 turns off, the base bias circuit of transistor 7 is cut off, transistor 7 turns off, and instead FET9 turns on.
To do. The reference current generating circuit of the current mirror circuit composed of FET9 and FET10 is activated, and FET12 and FET11 are turned on.

The FET 12 absorbs the base accumulated charge of the transistor 7 which is turned off, and the FET 11 drives the output terminal 13 in the 0V direction. Similar to FIG. 2, FIG. 3 shows the internal circuit when the output viewed from the output terminal is low level.

FIG. 4 shows a second embodiment of the present invention. The same elements as those in FIG. 1 have the same numbers. This is an example in which an N-type MOSFET 15 is used as an element for opening and closing the base bias current path of the emitter follower 7.

〔The invention's effect〕

As described above, the present invention has the effect of reducing the decrease in operating speed due to the increase in load capacitance when fanout is suppressed by adopting the emitter follower of the bipolar transistor instead of the MOSFET in the output stage. .
Further, by providing the base of the emitter follower with the discharge path of the base accumulated charge by the MOSFET, the transition time of the emitter follower itself can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams for explaining the operation of FIG. 1, and FIG. 4 is a circuit diagram of another embodiment of the present invention. The figure is a circuit diagram of a conventional example. 1,2 ...... NPN bipolar transistor that constitutes a differential amplifier, 3, 4 ...... Load resistance of the differential amplifier, 5 ...... P-type MOSFET that is cut off and conducted by the output of the differential amplifier, 6 ...... Differential amplifier , A NPN transistor that forms an emitter follower, 8 ... a resistor that forms an emitter follower, and 9 ... a P-type MOSFE that operates in an opposite phase to MOSFET5.
T, 10, 11, 12 ... N-type MOSFE that composes a current mirror pair
T, 13 ... Output terminal, 14 ... Power supply, 15 ... N-type MOSFET.

Claims (1)

[Claims] 1. A differential amplifier is composed of first and second bipolar transistors, a constant current source, and first and second load resistors connected to the collectors of the first and second bipolar transistors, respectively. At least one of the bases of the first and second bipolar transistors is provided with a signal voltage sufficient to alternately cut off the first and second bipolar transistors to make them conductive. A source connected to the collector of the second bipolar transistor, a gate connected to the collector of the second bipolar transistor, and a drain having the same conductive characteristics as the first and second bipolar transistors, and a collector connected to the first potential First connected to the base of a bipolar transistor
A gate and a source, respectively, such that the gate and the source have a MOSFET so that they are cut off when the first MOSFET is conducting, and are turned on when the first MOSFET is shut off, respectively. The second MOSFET is connected to the first potential, and the drain of the second MOSFET has a gate and a drain of a third MOSFET which is complementary to the second MOSFET, and the third MOSFET. The gates of the fourth and fifth MOSFETs of the same conductivity type are connected, the sources of the third, fourth and fifth MOSFETs are connected to the second potential, and the fourth and fifth MOSFETs are connected to the second potential. When each of the three MOSFETs forms a current mirror pair and the second MOSFET is cut off, the third, fourth, and fifth MOSFETs are also cut off, and when the second MOSFET is turned on, the third and the third MOSFETs are turned on. Fourth and fifth MOSFET
Is connected to the emitter of the third bipolar transistor, the other end of the third resistor whose one end is connected to the second potential and the drain of the fourth MOSFET are connected, and the output of Is extracted from the emitter of the third bipolar transistor.