JPH0683076B2 - Sign conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an NR in which input data is synchronized with a clock signal.
Z (None Return to Zero) code sequence data and RZ
(Return to Zero) The present invention relates to a code conversion circuit that can convert any data in a code sequence.

[Conventional technology]

Figure 3 shows, for example, the 59th National Conference of the Telecommunications Society of Japan's Communications Division, Paper No. S31-13 "G bit / s Si Bipol for optical communication.
It is a conventional code conversion circuit shown in "ar digital IC technology", and it is mainly used for NR synchronizing input data with a clock signal.
An identification circuit (1) that reproduces Z code sequence data and this N
And a conversion circuit (2) for converting RZ code series data into RZ code series data.

Among them, the identification circuit (1) has a power supply voltage terminal (3),
(4) Data input terminals (5), (6), clock signal input terminals (7), (8), current source (12), resistor (14) to
(17) and transistors (20) to (27).

In this case, the collector of the transistor (20) and the collector of the transistor (23) are connected to the other end of the resistor (14) whose one end is connected to the power supply voltage terminal (3), and further, one end is connected to the power supply voltage terminal (3 The collector of the transistor (21) and the collector of the transistor (22) are connected to the other end of the resistor (15) connected to (). And, of these transistors, the emitter of the transistor (20) and the emitter of the transistor (21) are the other transistor (2
The base of the transistor (20) is connected to the data input terminal (5), and the base of the transistor (21) is connected to the data input terminal (6). The emitter of the transistor (22) and the emitter of the transistor (23) are another transistor (25).
Connected to the collector. The base of the transistor (24) is connected to the clock signal terminal (7), the base of the transistor (25) is connected to the clock signal terminal (8), and the emitters of these transistors are connected to the current source (12). Further connected to the anode of the current source (12)
Is connected to the power supply voltage terminal (4).

On the other hand, the collector of the transistor (26) and the collector of the transistor (27) are connected to the power supply voltage terminal (3), and the base of the transistor (26) is connected to the other end of the resistor (14) to the transistor (27). The base is connected to the other end of the resistor (15), and the emitter of the transistor (26) is connected through the resistor (16), and the emitter of the transistor (27) is connected through the resistor (17). )It is connected to the. The base of the transistor (22) is the mutual junction of the emitter of the transistor (26) and the resistor (16), and the base of the transistor (23) is the mutual junction of the emitter of the transistor (27) and the resistor (17). Respectively connected to.

Next, the conversion circuit (2) has a clock signal input terminal (9),
(10), a data output terminal (11), a current source (13), resistors (18) and (19), and transistors (28) to (31).

In this case, the collector of the transistor (28) is a resistor (18).
Is connected to the power supply voltage terminal (3) via the, and the base is connected to the clock signal input terminal (9). The collector of the transistor (29) is connected to the power supply voltage terminal (3),
The base is connected to the clock signal input terminal (10). The emitters of these transistors are connected to the anode of the current source (13), and the cathode of the current source (13) is connected to the power supply voltage terminal (4). Also, the base of the transistor (30) is connected to the resistor (18) and the transistor (2).
8) is connected to the mutual junction with the collector, and the base of the transistor (31) is connected to the mutual junction between the resistor (14) and the collector of the transistor (20) described above.
The collector of the transistor (30) and the collector of the transistor (31) are both connected to the power supply voltage terminal (3), and the emitters of these transistors are connected to the data output terminal (11) and the resistor ( 19) and is connected to the power supply voltage terminal (4).

Next, after the operation of the identification circuit (1) is described, the operation of the conversion circuit (2) will be described with reference also to FIG.
The high voltage state of the signal voltage is "H", and the low voltage state is "L".
As described below.

Now, a predetermined voltage is applied to the power supply voltage terminals (3) and (4), and the clock signal (7a) having the illustrated phase is applied to the clock signal input terminal (7). Further, a clock signal of opposite phase to this is applied to the clock signal input terminal (8). Then, as an initial state, the discrimination circuit output (3
2) and (33) are reset to "H" and "L" respectively.

In this state, as shown in Fig. 4, "H" → "L" → "L" →
It is assumed that the data (5a) such as "H" is input to the data input terminal (5) and the data of the opposite phase is input to the data input terminal (6).

Now, while the input data (5a) is "H", the clock signal (7a) changes from "L" to "H", and the transistor (24)
When the electric potential of the base of the transistor becomes "H" (hereinafter referred to as the sample state), the electric potential of the current source (12) flows through the resistor (14) because the electric potential of the base of the transistor (20) is "H". The output (32) changes to "L" due to the voltage drop due to the resistor (14), and conversely, the identification circuit output (33) becomes the resistor (15).
It changes to “H” because the voltage drop due to disappears. These potential states are input to the bases of the transistors (22) and (23) via the transistors (26) and (27), respectively.

Next, while the input data (5a) is "H", the clock signal (7a) changes from "H" to "L", and the transistor (2a
When the base potential of 4) becomes "L" (hereinafter referred to as a hold state), the base potential of the transistor (23) is "H", so that the current of the current source (12) passes through the transistor (23) and becomes a resistance ( 14), so the identification circuit output (32),
(33) is held at "L" and "H", respectively.

Next, since the base potential of the transistor (21) is “H” during the sampling state during the period when the input data (5a) is “L”, the current of the current source (12) is
1) through the resistor (15), the identification circuit output (32),
(33) inverts to "H" and "L", respectively, and then maintains this state in the hold state.

As described above, the discrimination circuit output (32) becomes “L” → by repeating the operation in the sample state and the hold state.
The data changes from "H" to "H" to "L", and the data (5a) input to the data input terminal (5) is output as NRZ series data synchronized with the clock signal (7a).

In addition, the transistor (24) that constitutes the identification circuit (1),
(25) is alternately turned on by the clock signal (7a).

Next, the conversion circuit (2) will be described. When the clock signal (9a) is input to the clock signal input terminal (9), the clock signal of the opposite phase is input to the clock signal input terminal (10), This allows the transistor (28),
(29) is alternately on. Further, due to the action of the resistor (18) inserted in the collector circuit of the transistor (28), a base signal (34) having a phase opposite to that of the input of the clock signal input terminal (9) is added to the base of the transistor (30).

Here, it is assumed that the discrimination circuit output (32) described above, that is, the data of the NRZ code sequence is added to the base of the transistor (31). In this case, transistors (30) and (3
Output terminal (11) when both are in the off state
The AND circuit that the level (11a) of becomes "L". Therefore, the base signal (34) and the discrimination circuit output (32)
When the discriminator output (32) is "L", it changes to "L" and "H" in synchronization with the clock signal by taking the logical sum with and the discriminator output (32) is "H". At some time, the data that remains "H" or "H" is output in synchronization with the clock signal.

Thus, the RZ code sequence data synchronized with the clock signal is output from the data output terminal (11).

[Problems to be Solved by the Invention]

Since the conventional code conversion circuit configured as described above includes the identification circuit that obtains the NRZ code sequence data and the conversion circuit that outputs the RZ code sequence data, the circuit scale is large. Moreover, there is a problem that the power consumption increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a code conversion circuit that can realize a circuit miniaturization and can significantly reduce power consumption.

[Means for Solving the Problems]

In the code conversion circuit according to the present invention, the identification operation is performed by the first to eighth transistors, and the ninth transistor is connected in parallel to one of the transistors, so that the data of the NRZ code sequence and the RZ code can be obtained. Any of the series of data is configured to obtain desired data.

[Action]

In the present invention, one transistor is additionally provided in the discrimination circuit that has constituted the conventional device, and the base potential of this transistor is changed to two types to obtain data of different encoded sequences. Therefore, the circuit can be downsized and the power consumption can be significantly reduced.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 3 denote the same elements.

Here, in the code conversion circuit (35), a transistor (36) is added to the above-described identification circuit (1), and a base voltage setting terminal (for applying a voltage set to the base of the transistor (36) ( 37), a data output terminal (38) for extracting output data from the mutual junction of the emitter of the transistor (27) and the resistor (17) and the mutual junction of the emitter of the transistor (26) and the resistor (16). , (39) are provided.

The transistor (36) is connected in parallel with the transistor (22).

The operation of the present embodiment configured as described above will be described below with reference to the time chart of FIG.

First, "H" →
A voltage signal (5a) that changes from "L" to "L" to "H" is input, and a clock signal (7a) having the illustrated phase is also applied to the clock signal input terminal (7). At this time, the data input terminal (6) has data in a phase opposite to that of the data input terminal (5), and the clock signal input terminal (8) has a clock signal in phase opposite to that of the clock signal input terminal (7). Are added respectively.

Now, it is assumed that the potentials of the data output terminals (38) and (39) have been reset to "L" and "H" respectively in the initial state. In this state, change the voltage of the base voltage setting terminal (37) from the base potential of the transistors (22) and (23).
The transistor (36) is always kept in the off state if it is set to a voltage value on the lower side.

Then, the code conversion circuit (35) repeats the sample state and the hold state and performs exactly the same operation as the conventional identification circuit, and the data output terminals (38) and (39) are connected to the (38) of FIG.
a), (39a), NRZ synchronized with the clock signal
Data of the code sequence is obtained.

Next, when the voltage of the base voltage setting terminal (37) is set higher than the higher voltage value of the base potentials of the transistors (22) and (23), the base voltage of the transistor (25) becomes "H". In the hold state, the transistor (36) is turned on. At this time, the current of the current source (12) flows through the resistor (15), and the potentials of the data output terminals (38) and (39) are set to “L”, via the transistors (26) and (27), respectively.
Reset to “H”.

By the above operation, the data output terminals (38) and (39) output the data of the RZ code sequence synchronized with the clock signal as shown in (38b) and (39b) of FIG.

Thus, according to this embodiment, if a transistor is added to the conventional identification circuit and the base potential of this transistor is lowered to turn it off, NRZ code sequence data is obtained and the base potential of the transistor is raised. When turned on, the RZ code sequence data is obtained.

In the above embodiment, the code conversion circuit in which the transistor (36) is added to the D latch flip flop that holds the level of the input data when the clock signal rises has been described. The same operation as described above can be performed by adding a transistor to another flip-flop such as a J, K flip-flop.

Further, in the above embodiment, the signals of opposite phases are inputted to the data input terminals (5) and (6) and the clock signal input terminal, but instead of this, the reference voltage is inputted to either one of the terminals. May be.

[Effects of the Invention] As is clear from the above description, according to the present invention, a part of the conventional device is provided with a transistor in a circuit.
Since the data are differently encoded by changing the base potential of the transistor to two types, it is possible to reduce the size of the circuit.
This has the effect of significantly reducing power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the structure of an embodiment of the present invention, and FIG.
The figure is a time chart for explaining the operation of the embodiment,
FIG. 3 is a circuit diagram showing the configuration of a conventional code conversion circuit, and FIG.
The figure is a time chart for explaining the operation of the code conversion circuit. (5), (6): Data input terminal (7), (8): Clock signal input terminal (12): Current source (14) to (17): Resistor (20) to (27): Transistor (37) : Base voltage setting terminals (38), (39): Data output terminals In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first power source, wherein each emitter is connected to one end of the power source.
And a second transistor, third and fourth transistors whose collectors are connected to the collectors of the first transistor and whose collectors are connected to the other end of the power source through resistors, respectively, and the second transistor. An emitter is connected to the collectors of the transistors, collectors are connected to the collectors of the fourth and third transistors, respectively, and fifth and sixth transistors, and emitters are connected to the bases of the fifth and sixth transistors, respectively. As well as
Seventh and eighth transistors each connected to one end of the power source through a resistor, a collector connected to the other end of the power source, and bases connected to the collectors of the third and fourth transistors, respectively. A fifth transistor and a ninth transistor connected in parallel, wherein a positive phase clock signal is applied to the base of the first transistor, and a negative phase clock signal is applied to the base of the second transistor, and Positive-phase data is input to the base of the third transistor, and negative-phase data is input to the base of the fourth transistor, and the base voltage of the ninth transistor is changed to change the ON / OFF state. From the emitter of the seventh transistor or the eighth transistor, the third transistor is synchronized with the clock signal. Or code conversion circuit and outputs the data of the fourth data input to the base of the transistor coded sequence with different coding sequences.