JPH0683170B2 - Frame synchronization circuit - Google Patents

Description

The present invention relates to frame synchronization of a time division multiplex conversion device, etc.
In particular, the present invention relates to synchronization protection of a frame synchronization circuit using a multiple nomination majority decision system that simultaneously determines synchronization for a plurality of bits in a frame.

[Conventional technology]

First, a frame synchronization method based on a so-called multiple nomination majority decision method to which the present invention is applied will be briefly described.

In the conventional general frame synchronization method, in order to specify a frame bit position, it is verified whether or not a certain bit position is a frame bit, and if the condition is not satisfied, the same is performed for the next bit position. A bit hunting method such as a 1-bit continuous shift method is used in which verification is performed and this is continued until a bit position satisfying the conditions is detected. In this bit hunting system, since the synchronization determination is performed for 1 bit as described above, the synchronization determination conditions for specifying the frame bit position are as follows. That is, the occurrence status of the coincidence signal and the non-coincidence signal must satisfy a predetermined condition at the bit position to be verified. (Judgment condition 1) Here, the coincidence signal and the non-coincidence signal are signals indicating that they are coincident with each other by comparing the expected signal when it is at the frame bit position with the signal under verification in the synchronization detection circuit. , And a signal indicating a mismatch.

The plural nomination majority decision method does not perform bit hunting for each bit but verifies all the bits in a frame at the same time, which makes it possible to shorten the synchronization pull-in time. However, since verification is performed simultaneously for a plurality of bit positions, if there are a plurality of bit positions that satisfy the above-mentioned determination condition 1, the frame bit position cannot be specified. Therefore, the synchronization determination condition in this method is the above-mentioned determination condition. In addition to condition 1, the following condition is required. That is, when the above-mentioned judgment condition 1 is satisfied at a certain bit position, all the remaining bit positions do not satisfy the above-mentioned judgment condition 1. (Judgment condition 2) In order to further reduce the possibility of false synchronization pull-in due to a bit error or the like, it is practically necessary to make the judgment condition 2 strict as follows. That is, when the judgment condition 1 is satisfied at a certain bit position, the occurrence status of the coincidence signal and the non-coincidence signal at the remaining bit positions has a certain difference or more from the condition of the judgment condition 1. (Judgment Condition 2 ') Here, let us consider the configuration of the multiple nomination majority decision method when the judgment conditions 1 and 2'are assumed as follows.

The match signal must be continuous 6 times or more for a certain bit position. (Judgment condition 1) The number of coincidence signals generated for the remaining bit positions is 3 or more less than that at the bit positions satisfying judgment condition 1. (Judgment Condition 2 ') FIG. 2 shows the configuration of a frame synchronization circuit based on the conventional multiple nomination majority decision method.

Here, reference numeral 5 is a synchronization detection unit corresponding to each bit position, which sends a coincidence signal and a non-coincidence signal. Further, 6 is a counter for counting the number of coincidence signals and non-coincidence signals from the respective synchronization detecting units 5, and 7 is for receiving the states of the counter 6 at all bit positions to judge whether or not the judgment conditions 1 and 2'are satisfied. It is a synchronization determination unit.

[Problems to be Solved by the Invention]

In the above-mentioned conventional frame synchronization circuit in the so-called multiple nomination majority decision method, in order to specify the frame bit position from the decision condition 2 ', counting is continued until a certain difference appears in the count state at the plural bit positions. Therefore, the number of stages of the counter 6 in FIG. 2 cannot be uniquely determined.

Generally, the occurrences of 0 and 1 in the data signal are considered to be random, so that it is extremely rare that a match signal is generated consecutively many times at bit positions other than the frame bit.
In practice, limiting the number of stages of the counter to an appropriate value is not considered to be a big problem. However, when a specific fixed pattern is repeatedly transmitted to the data signal, the coincidence signal may occur at the data bit position many times in succession. In such a case, in the synchronization method that performs bit hunting, erroneous synchronization pull-in may occur depending on the bit position at which hunting starts, but in the synchronization method that uses the multiple nomination majority decision method, the number of stages of the counter must be set large enough. It is possible to reduce the probability of false synchronization pull-in. But,
In this case, since the counter is required independently for each bit position, there is a drawback that the hardware amount increases if the number of stages of the counter at each bit position is increased.

In addition, if the number of times a fixed pattern is repeatedly sent is not limited, there is no upper limit on the number of coincidence signals that can be generated at the corresponding data bit positions. There was a drawback that you couldn't.

An object of the present invention is to eliminate such drawbacks and to provide a frame synchronization circuit that suppresses an increase in the amount of hardware even with respect to a repetitive signal of a specific fixed pattern and surely carries out synchronization.

[Means for Solving the Problems]

According to the present invention, when the frame length is N bits, whether or not the condition of the frame bit is satisfied for each bit position in the frame synchronization circuit using the method of simultaneously determining the synchronization for all the bits in the frame. The N synchronization detection units to be verified and the coincidence signals and non-coincidence signals output from the corresponding synchronization detection units are set to 1 and 0, respectively,
The N memory units that operate as M-stage shift registers that store only the latest M frames and the corresponding signal contents are stored in the correct frame bit position. The N difference detection units for detecting the difference in how many bits are different from the all 1 state, and the detection results of the N difference detection units have no difference at a certain one bit position, and all other When there is a difference of a certain number or more in bit positions, it is characterized by having a determination circuit that determines a bit position having no difference as a correct frame bit position.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Here, 1 is a synchronization detection unit that verifies whether the signal at each bit position satisfies the condition of the frame bit, and 2 is a memory that stores the occurrence status of the coincidence signal and the disagreement signal output from the synchronization detection unit 1. And a reference numeral 3 is a difference detecting section for detecting how many bits the contents of the memory section 2 are different from the occurrence status of the match signal and the mismatch signal which should be expected at the frame bit position. 2. Since the difference detection unit 3 operates independently for each bit position in one frame length, N sets are required when one frame is composed of N bits. Further, 4 receives the signals from the N number of difference detection units 3, one of the bit positions matches the expected state of the frame bit position, and the remaining bit positions are all bit positions. ,
This is a determination unit that determines whether or not there is a certain difference or more from the expected state at the frame bit position.

Further, according to the present invention, the operation of the frame synchronization protection when the judgment conditions 1 and 2'are assumed as in the case of the conditions used in the description of the conventional system as follows will be described.

Judgment condition 1: The coincidence signal is continuous 6 times or more for a certain bit position Judgment condition 2 ′: The number of coincidence signals generated for the remaining bit positions is higher than that of the bit positions satisfying the judgment condition 1 3 or less Under the above conditions, the memory unit 2 and the difference detection unit 3 in FIG. 1 can be configured as follows. That is, since it is sufficient to consider that the memory unit 2 has a capacity of 6 bits and updates one bit for each frame according to the determination condition 1, a 6-bit shift register is assumed as a special type memory here. Further, assuming that the signal from the synchronization detecting unit 1 is a signal which becomes 1 when they match and 0 when they do not match, the difference detecting unit 3 expects that the signal expected at the frame bit position will be 1 consecutive 6 times or more. , Whether there is a difference of 3 bits or more from the state where all 6 bits are 1
That is, it is determined whether or not 0 is 3 bits or more.

The frame structure is N bits, the i-th bit is a regular frame bit position, and a signal that repeats a fixed pattern that pseudo matches the frame bit is output at the j-th bit position, and the bit length is The operation of frame synchronization protection when the length is 30 bits will be described with reference to FIG.

FIG. 3 is a diagram showing the occurrence status of the coincidence signal and the non-coincidence signal at each bit position under the above conditions. The numbers on the vertical axis indicate the bit positions in the frame, and the numbers on the horizontal axis indicate what frame. . In addition, ∘ indicates that a match signal has been generated, and x indicates that a mismatch signal has been generated. Also D ₆ , D ₇ , ...
, D ₃₂ , D ₃₃ indicate the range stored in the shift register (memory unit 2) at the sixth, seventh, ..., 32nd, and 33rd frame positions, respectively. Where D ₆ is i,
Six consecutive coincidence signals are generated at the j-th and N-th bit positions, and these satisfy the judgment condition 1, but the frame bit position cannot be specified from the judgment condition 2 '. D comes out a three mismatch signal ₉ in N-th bit position, N th is determined not to be the frame bit position.

Up to the 30th frame, the coincidence signal is continuously generated at the bit positions of i and j, and no significant difference is recognized between the bit positions. A mismatch signal starts to occur at the j-th bit position from the 31st frame, and a difference occurs. However, since the difference is 2 or less up to D ₃₂ , the frame bit position is not specified yet. Since the difference becomes 3 or more for the first time at D ₃₃ and the judgment condition 2 ′ is satisfied, the i-th bit position is specified here as the frame bit position.

〔The invention's effect〕

As described above, according to the present invention, instead of the counter for counting the coincidence signal and the non-coincidence signal of the conventional method, the generation status of these signals is written in a memory of a fixed capacity and is constantly updated to make the first determination condition. The contents of this memory are compared with the expected occurrences of coincidence signals and non-coincidence signals at the frame bit positions, and a difference detection unit that detects differences and a determination unit that verifies this across all bit positions. By verifying the determination condition of No. 2, there is an effect that it is possible to suppress the increase in the amount of hardware even for the repetitive signal of the specific fixed pattern and reliably perform the synchronization pull-in.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a conventional frame synchronization circuit, and FIG. 3 is a diagram showing the bit position and the bit position in the embodiment of FIG. It is the figure which showed an example of the generation condition of the coincidence signal and the disagreement signal in each frame position. 1,5 …… Synchronization detection unit 2 …… Memory unit 3 …… Difference detection unit 4 …… Determination unit 6 …… Counter 7 …… Synchronization determination unit

Claims (1)

[Claims] 1. When the frame length is N bits, whether or not the condition of the frame bit is satisfied for each bit position in a frame synchronization circuit using a method of simultaneously determining the synchronization for all bits in the frame. N sync detectors for verifying the above, and the coincidence signal and the non-coincidence signal output from the corresponding sync detectors are set to 1 and 0, respectively, and operate as an M-stage shift register that stores only the latest M frames. N memory units and N memory units that detect the difference in how many bits the contents of the corresponding memory units are different from the all 1 state, which is the generation status of the match signal and the mismatch signal expected at the correct frame bit position. Difference detection units and the detection results of the N difference detection units have no difference at a certain one bit position, and a predetermined number or more at all other bit positions. And a determination circuit for determining a bit position having no difference as a correct frame bit position.