JPS5947902B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization system, which is useful for use in a time division multiplex transmission system, and is designed to ensure accuracy of synchronization and at the same time achieve speedup. .

In a time division multiplex transmission system, whether it is a character multiplex transmission system, a bit multiplex transmission system, or any type of frame structure, the position of a synchronization signal in a frame can be determined accurately and in a short time. That is essential.

Synchronization pull-in in such a frame synchronization method can be easily achieved if the range in which the synchronization pattern exists can be identified (
For example, ``Basics of PCM Communication and New Technologies'' edited by Hiroshi Inose, P.
254~P. 256). However, when actually proceeding with the development of a system in this technical field, there is a major problem that becomes an obstacle to accurately specifying the range in which a synchronization pattern exists in a short period of time. One of them is called code sensitivity, when trying to accurately determine the position of a synchronization signal, when a digital signal transmitted through a time division multiplex transmission system is
The problem is that when the same pattern as the synchronization signal occurs, synchronization is erroneously pulled in. The other one is
When determining the synchronization signal in a frame, if the bit error rate is poor, the synchronization acquisition time becomes long. Such problems also apply to the detection of out-of-synchronization. Therefore, in conventional time division multiplex transmission systems, in order to prevent code sensitivity, which is primarily required in this technical field, the synchronization pull-in conditions are made stricter, and the digital signal is processed using a scrambler/descrambler. Measures are taken such as randomization or prohibiting the same pattern as the synchronization signal.

However, a trade-off relationship arises in that the stronger such means becomes, the longer the synchronization pull-in time becomes, the more vulnerable it becomes to bit errors, or the more complex the circuit becomes. In other words, the requirement to prevent code sensitivity and the requirement to shorten the synchronization pull-in time are contradictory.
SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a frame synchronization method that can identify a range in which a sufficiently reliable synchronization pattern exists in a short period of time, and can perform synchronization satisfactorily. .

The configuration of the present invention that achieves such an object has a temporary storage memory for temporarily storing an input data signal when detecting a synchronization signal in a frame in a time division multiplex transmission system, and the input data signal is stored in the temporary storage memory. Every time the input data signal is updated by one character (in the case of concentrated insertion method) or one bit (in the case of distributed insertion method), all time slots in one frame are checked, and as a result, a synchronization pattern specific to the synchronization signal is detected. is detected, restore all the numbers of that time slot and count by adding +1 to the time slot each time the synchronization pattern is detected, or if a synchronization pattern specific to the synchronization signal is detected. In that case, restore all the numbers of that time slot, and add +1 to that time slot each time the synchronization pattern is detected, and if no synchronization pattern is detected, add +1 to the time slot as long as the count value is within a positive value. When a certain time slot first counts a predetermined number of synchronization patterns, the count value of this time slot is compared with the count values of all remaining time slots, and the count difference at this time is constant. If the predetermined number of synchronization patterns is greater than or equal to the predetermined number, the synchronization pattern of the time slot in which the predetermined number of synchronization patterns has been detected is determined to be a synchronization pattern based on a genuine synchronization signal;
The present invention is characterized in that it includes an arithmetic processing unit that repeats detection of the synchronization pattern until the count difference reaches a certain number when the difference in count is less than a certain number. Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram for realizing the frame synchronization method according to this embodiment.

As shown in the figure, the input data signal R. The AGG is stored in the temporary memory RAM via the high-speed side interface HSI in response to a control signal from the arithmetic processing unit CPU, and checks the presence or absence of a synchronization pattern in all time slots. This synchronization pattern is a pattern unique to the synchronization signal and is determined in advance in the time division multiplex transmission system. Further, the details of the processing performed by the arithmetic processing unit CPU will be described later, but related programs, the synchronization patterns, etc. are stored in a read-only memory ROM. In addition, the input data signal R. AGG and control signals are transmitted to each block via a common bus CBUS. Furthermore, in FIG. 1, the LSI is connected to the terminal side of the time division multiplex transmission system through a low-speed side interface. Similarly, S. AGG is high speed side interface HS
The output data signal is a time division multiplexed signal sent over I. In such a system, an input data signal R. In this embodiment, the input data signal R is used to detect the synchronization signal from the AGG.
．． All time slots of the AGG are checked for the presence or absence of a synchronization pattern, and if a synchronization pattern is detected, +1 is added to that time slot. Such operations
This process is repeated until the count value of one time cut reaches a predetermined value. When the count value of a certain time slot reaches a predetermined number, it is determined whether or not there is a difference in count of a certain number or more with the count values of all other time slots except that time slot. If there is a count difference of a certain number or more, the synchronization pattern of the time cut that has reached the predetermined number is determined to be a genuine synchronization pattern based on the synchronization signal. On the other hand, if the count difference is less than a certain number, the synchronization pattern detection operation is repeated until the count value of any time slot is a predetermined number or exceeds a predetermined number and the count difference becomes a constant number. The graph formed at this time is shown in FIG.

In the figure, the frame length is assumed to be L words, so L time slots are formed at this time. In this time slot, times "rod number 1-"
It is marked with L and plotted on the horizontal axis. On the other hand, the vertical axis shows a count value Ci corresponding to the number of times the synchronization pattern has been detected. In this example, the count value C of the time slot with time slot number 1
i reaches a predetermined number N, and at this time, the count difference δ with the one that takes the largest count value Ci among the remaining time slots is a constant number K, satisfying the condition that δ≧K. . Therefore, the synchronization pattern of the time slot with time slot number i is determined to be a genuine synchronization pattern based on the synchronization signal. Next, the storage mode in the temporary memory RAM and the processing mode performed by the arithmetic processing unit CPU will be explained separately for the character multiplexing method and the bit multiplexing method.

FIG. 3a shows the input data signal R in the case of character multiplexing. FIGS. 3B and 3C are explanatory diagrams conceptually showing the AGG. FIGS. 3B and 3C are explanatory diagrams conceptually showing the storage mode of the temporary memory RAM at this time.

Furthermore, the l character at this time is made up of M bits, and therefore the synchronization pattern uses a concentrated insertion method made up of M bits. Furthermore, FIGS. 3B and 3c correspond to FIG.
The input data signal R. In addition to showing the storage mode of AGG, we also examined the synchronization pattern regarding all time slots. The case where N times, that is, the predetermined number is N, is shown. Therefore, the input data signal R. AGG is read vertically M bits at a time, and at the same time time slot numbers 1-L and frame numbers 1-1N are designated. In this case, regarding the first time slot of the first frame, it is checked whether a synchronization pattern exists only in this time slot, but after reading the subsequent M bits, this read M bit and the previously read M bit are checked. of M bits. Check whether a synchronization pattern exists in
This is especially true if the time slot is ideally read from the beginning with a genuine synchronization pattern as shown by diagonal lines in Figure 3b, and if it is ideally read from the beginning into a time slot with a genuine synchronization pattern as shown by diagonal lines in Figure 3c. This is because if the time slot is read across two time slots, it will be impossible to detect the synchronization pattern by just inspecting one time slot. In the case as shown in FIG. 3c, the subsequent processing is performed on the assumption that the synchronization pattern is detected at a time slot numbered after the second half of the synchronization pattern has been read. As a result of such inspection, the time slot numbers where the synchronization pattern was detected are restored and added by 1 for each detection.
Count. In the portion indicated by C in FIGS. 3B and 3C, the numbers given in the horizontal direction in the figure represent the number of digits to which the bits common to each time slot indicated by the numbers given on the vertical axis on the left side of the figure correspond. That is, M represents M digits, 2 represents 2 digits, and 1 represents 1 digit. Further, the numbers attached to the vertical axis on the right side of the figure represent frame numbers. That is, according to these numbers, one frame consists of L bytes of input data signal R.
AGG has been read for N frames, and in Fig. 3b there is a synchronization pattern in the M bits of the i-th time slot, and in Fig. 3c there is a synchronization pattern in the middle of the (i-1)th time slot. M from the first digit to the first digit and from the M digit of the i-th time slot number to the middle digit
It is understood that a synchronization pattern exists in the bits. On the other hand, in the case of the bit multiplexing method, the input data signal R. FIG. 4a is an explanatory diagram conceptually showing the AGG, and FIGS. 4b and 4c are explanatory diagrams conceptually showing the storage mode of the temporary memory RAM at this time. Furthermore, the synchronization pattern at this time consists of M bits and is inserted by a distributed insertion method. Furthermore, FIGS. 4B and 4C correspond to FIG. 2, and show the input data signal R.B and C in which one frame is composed of L bits having L time slots. It shows the storage mode of the AGG and also shows the case where the synchronization pattern for all time slots is checked N times, that is, the predetermined number is N. In such a bit multiplexing system, the input data signal R.
Reading of AGG is performed one bit at a time while shifting vertically or vertically and horizontally. At the same time, time slot numbers 1 to L and frame numbers 1 to N are specified. In this case, for the first frame, the first frame is It is checked whether a pattern of M bits per L bits at a certain distance on the same column over the same column or a pattern of M bits per L bits over two adjacent columns matches the synchronization pattern.

As a result, even if the head of the synchronization pattern is included in the topmost frame of the figure, as indicated by diagonal lines and surrounded by thick lines in Fig. 4b, the head of the synchronization pattern is indicated by diagonally lines and surrounded by thick lines in Fig. 4c. As shown representatively, frames excluding the top row, for example, the M-th frame as shown in FIG. A synchronization pattern can always be detected even if it is included in the first frame. The subsequent processing is similar to the character synchronization method. In Figures 4B and 4C, the lower horizontal axis shows the number of this group when M frames are made into one group, the left axis shows the time slot number, and the right vertical axis shows the number of this group. A frame number is attached to each frame. In this manner, regardless of whether the bit multiplexing distributed insertion method or the character multiplexing intensive insertion method is adopted, if a synchronization pattern is detected, +1 is counted on the graph shown in FIG. Therefore, the counting part C
The configuration of is similar. Then, the count value Ci is a predetermined number N
After that, as mentioned above, the count difference δ with other count values Ci
is greater than or equal to a certain number. At this time, the predetermined number N and the predetermined number K of the count difference δ can take various values depending on how the bit error rate of the line is taken. For example, under the condition that the bit error rate is 10-5, Appropriate values are N=6 and K=3.

Although the storage capacity of the temporary storage memory RAM is explained above as N frames, in principle, it is 2 characters in the case of the central insertion method, and 2M in the case of the distributed insertion method.
It is sufficient to have a storage capacity for frames.

Furthermore, the storage mode and readout mode need not be limited to the above two examples. On the other hand, if past memory contents remain as in this embodiment, the following effects can be expected. 1) Functions such as counting erroneous rebits in a synchronizing signal and determining when a synchronizing signal is disconnected can be easily added.

2) With the addition of the above function, it is also possible to switch without losing synchronization when two or more multiplexed signals are received in diversity.

In this case, the storage capacity of the temporary storage memory is determined by the transmission delay time of the transmission path. If a synchronization pattern is detected, +l is counted in that time slot, but if no synchronization pattern is detected in the next test, +1 may be subtracted.

In this case, the count value Ci is always set to a positive value.
That is, if the count value Ci of the time slot becomes zero, it is removed from the nomination list. Next, we will compare the characteristics of the second invention, which uses the second counting method, and the first invention, which uses the first counting method, which simply performs addition as described above.

The first invention performs counting only by addition, whereas the second invention differs in that addition and subtraction are performed. For this reason,
Similar to the results in all competing models, the second invention has a faster synchronization pull-in time than the first invention. On the other hand, the first invention is more resistant to erroneous rebiting than the second invention. Therefore, it becomes possible to apply them by taking advantage of their respective strengths. Furthermore,
An embodiment of the present invention will be systematically explained using the flowchart shown in FIG.

First, input data signal R. AGG is M bits or 1
The bit reading time slot is specified, that is, the time slot number 1 and frame number j are specified.

Next, a synchronization pattern in the new situation is detected, and if a synchronization pattern is detected, +1 is added to the time slot of the corresponding time slot number, while if no synchronization pattern is detected, the process proceeds to the next step. At this time, the second
If the invention is not detected, +1 is subtracted. In the flowchart, *1 and *2 are added to indicate that the invention relates to the first invention or the second invention. This operation is continued until a certain time slot detects a predetermined number N. Next, it is determined whether there is a count difference δ of a certain number K or more between the time slots and the remaining time slots. If there is no synchronization, there is a high probability that an erroneous synchronization pull-in will occur, so the above-described operation is continued until the count difference δ reaches a certain number K or more. If all of the above conditions are met, the synchronization pattern of the corresponding time slot is determined to be a genuine synchronization pattern based on the synchronization signal, the time slot is adjusted, and the start position of the synchronization signal is confirmed, that is, the start position of the synchronization signal is found. Do the following. As specifically explained above in conjunction with the embodiments, according to the present invention, the requirements for preventing code sensitivity and the requirements for shortening the synchronization pull-in time, which have conventionally been contradictory requirements, can be more rationally harmonized. Therefore, highly reliable synchronization pull-in can be performed in a short time.

[Brief Description of the Drawings] Fig. 1 is a block diagram according to an embodiment of the present invention, Fig. 2 is a graph formed as a result of synchronization pattern detection, and Fig. 3 a.
is an explanatory diagram conceptually showing the input data signal of the character multiplexing method/concentrated insertion method, FIGS. 3B and c are explanatory diagrams conceptually showing the storage mode at that time, and FIG. An explanatory diagram conceptually showing the input data signal of the insertion method. FIGS. 4B and 4C are explanatory diagrams conceptually showing the storage mode at that time. FIG. , FIG. 4c shows the case where the image exists across two frames. FIG. 5 is a flowchart according to an embodiment of the present invention.
In the drawing, R. AGG is an input data signal, RAM is a temporary storage memory, N is a predetermined number, Ci is a count value, δ is a count difference, K
is a fixed number, and CPU is an arithmetic processing unit.

Claims (1)

[Claims] 1. Consecutive M bits inserted according to a concentrated insertion method into a time division multiplex transmission signal in which 1 M bit (M is a natural number of 2 or more) constitutes 1 time slot and L time slots constitute 1 frame. A frame synchronization method that detects a frame synchronization signal consisting of a pattern includes a temporary storage memory that stores input data signals for at least two time slots, and every time the input data stored in the temporary storage memory is updated by M bits. The contents of the temporary storage memory are inspected, and as a result, when the M-bit pattern of the frame synchronization signal is detected in a certain time slot, the time slot number is listed up, and the M-bit pattern of the frame synchronization signal is detected in a certain time slot. When detected over two time slots, the number of the time slot in which the second half of the M-bit pattern is accommodated is listed, and each time the M-bit pattern of the frame synchronization signal is detected, the number of the time slot is When a certain time slot first detects a predetermined number of synchronization patterns, the count value of this time slot is compared with the count values of all remaining time slots, and the difference in count at this time is calculated. is greater than or equal to a certain number, the synchronization pattern of the time slot in which the predetermined number of synchronization patterns has been detected is determined to be a synchronization pattern based on a genuine synchronization signal, while if the count difference is less than a certain number, the synchronization pattern is determined to be a synchronization pattern based on a genuine synchronization signal. A frame synchronization method characterized by having an arithmetic processing unit that repeats detection of synchronization patterns until the number of synchronization patterns is reached. 2. In a time division multiplex transmission system, when detecting a synchronization signal in a frame, a temporary storage memory is provided to temporarily store the input data signal, and each time the input data signal stored in this temporary storage memory is updated by 1 bit. As a result, if a synchronization pattern specific to the synchronization signal inserted by the distributed insertion method is detected, all the timeslot numbers are listed and the synchronization pattern is Each time a time slot is detected, +1 is added to that time slot for counting, and when a certain time slot detects a predetermined number of synchronization patterns for the first time, the counted value of this time slot is combined with the counted value of all remaining time slots. If the count difference at this time is a certain number or more, the synchronization pattern of the time slot in which the predetermined number of synchronization patterns has been detected is determined to be a synchronization pattern based on a genuine synchronization signal. A frame synchronization method characterized by having an arithmetic processing unit that repeats detection of synchronization patterns until the number reaches a certain number when the number is less than a certain number. 3. A frame synchronization signal consisting of a continuous M bit pattern inserted according to the concentrated insertion method into a time division multiplexed transmission signal in which one time slot consists of 3 M bits (M is a natural number of 2 or more) and one frame consists of L time slots. In a frame synchronization method for detecting an input data signal, a temporary storage memory is provided that stores input data signals for at least two time slots, and the temporary storage memory is updated every time the input data stored in the temporary storage memory is updated by M bits. If the M-bit pattern of the frame synchronization signal is detected in a certain time slot, the time slot number is listed and the M-bit pattern of the frame synchronization signal is detected over the two time slots. When detected, the number of the time slot in which the latter half of the M-bit pattern is accommodated is listed, and each time the M-bit pattern of the frame synchronization signal is detected, +1 is added to that time slot, and the synchronization pattern is is not detected, the count value is counted by subtracting +1 within the range of positive values, and when a certain time slot counts a predetermined number of synchronization patterns for the first time, the count value of this time slot and all remaining times are calculated. Compare the count value of the slot, and if the count difference at this time is a certain number or more, determine that the synchronization pattern of the time slot in which the predetermined number of synchronization patterns has been detected is a synchronization pattern based on a genuine synchronization signal. On the other hand, a frame synchronization method characterized by having an arithmetic processing unit that repeatedly detects a synchronization pattern when the counted difference is less than a certain number until it reaches a certain number. 4 In a time division multiplex transmission system, when detecting a synchronization signal in a frame, a temporary storage memory is provided to temporarily store the input data signal, and each time the input data signal stored in this temporary storage memory is updated by 1 bit, As a result, if a synchronization pattern specific to the synchronization signal inserted by the distributed insertion method is detected, all the timeslot numbers are listed and the synchronization pattern is Each time a time slot is detected, +1 is added to that time slot, and if no synchronization pattern is detected, +1 is subtracted from the count value within a positive value range. When counting, the count value of this time slot is compared with the count values of all remaining time slots, and if the count difference at this time is a certain number or more, the count value of the time slot in which the predetermined number of synchronization patterns has been detected is determined. The device is characterized by having an arithmetic processing unit that determines that the synchronization pattern is a synchronization pattern based on a genuine synchronization signal, and, if the count difference is less than a certain number, repeats the detection of the synchronization pattern until it reaches a certain number. Frame synchronization method.