JPH0685533B2 - Clock pulse balanced transmission output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to clock pulse balanced transmission used for balanced transmission of synchronizing signal clock pulses (48 [kHz]) for constructing a digital audio system, for example. Regarding the output circuit.

(Prior Art) Generally, in a digital audio system, when transmitting a clock pulse as a sampling synchronization signal,
A balanced transmission method is used. The structure is shown in FIG.

In FIG. 3, the transmitted clock pulse CP is input to the balanced line driver circuit 11. The driver circuit 11 outputs the non-inverted signal CP ₁ and the inverted signal CP ₂ of the input pulse CP at the same time. Both signals CP ₁ and CP ₂ are respectively balanced transmission lines 12
Through the non-inverting input terminal of the balanced line receiver circuit 13,
It is sent to the inverting output. A terminating resistor 14 is connected between the non-inverting input terminal and the inverting output terminal of the receiver circuit 13.
The terminating resistor 14 is for impedance matching of the balanced transmission line 12. The receiver circuit 13 accurately reproduces and outputs the clock pulse CP based on both inputs.

By the way, in the clock pulse balanced transmission output circuit having the above configuration, when the driver circuit is broken, the clock pulse cannot be sent. Therefore, for important clock pulse transmission, it is required to use two transmission systems to improve reliability. However, if only two systems are used, the cost of the cable as the transmission line will be doubled, which is uneconomical.

(Problems to be Solved by the Invention) As described above, the conventional clock pulse balanced transmission output circuit can no longer transmit clock pulses when the driver circuit is broken.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a clock pulse balanced transmission output circuit capable of duplexing a transmission form with a simple configuration, suppressing cost increase and improving reliability. To aim.

[Object of the Invention] (Means for Solving the Problems) In order to achieve the above object, a clock pulse balanced transmission output circuit according to the present invention inputs the same clock pulse, respectively, and outputs a non-inverted pulse of the input clock pulse. A plurality of line driver circuits that generate and output the inverted pulses at the same time, and a plurality of coupling capacitors that remove the direct current components from the non-inverted output pulses and the inverted pulses output from these line driver circuits and output them. ,
The pulses output from these coupling capacitors are respectively passed through the first resistance to be converted into a voltage, and then the non-inverted pulses are merged with the inverted pulses, and the addition processing is performed. And a voltage adding means for sending out to a pair of balanced transmission lines through resistors.

(Operation) In the clock pulse balanced transmission output circuit with the above configuration,
The non-inverted pulse and the inverted pulse of the input clock pulse are individually generated by the line driver circuits of a plurality of systems, and the DC components are removed by the coupling capacitors, respectively, and then the non-inverted pulses are inverted by the first and second resistors. Voltages of the pulses are added together and the pulses are transmitted to a pair of balanced transmission lines.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals, and the different parts will be mainly described here.

FIG. 1 shows the configuration thereof. The clock pulse CP inputted to this circuit is branched into two systems and inputted to the balanced line driver circuits 11a and 11b, respectively. Each driver circuit 11a, 11b has a non-inverted signal CPa of the input pulse CP.
₁ and CPb ₁ and inverted signals CPa ₂ and CPb ₂ are output simultaneously,
Both of these are input to the adder circuit 15.

The adder circuit 15 uses the non-inverted pulse C from the driver circuits 11a and 11b.
Pa ₁ and CPb ₁ are input with the coupling capacitors C ₁ and C ₂ blocking the direct current component, and the voltage is added through resistors R ₁ , R ₂ and R ₃ and at the same time the inversion pulse CPa from the driver circuits 11a and 11b. ₂ and CPb ₂ are input by blocking the DC component with the coupling capacitors C ₃ and C ₄ , respectively, and the voltage is added through the resistors R ₄ , R ₅ and R ₆ .

Here, the non-inverted pulse CPa ₁ from the driver circuits 11a and 11b,
Since both CPb ₁ have the same phase waveform as shown in FIG. 2 (A), if both are added in voltage, the amplitude is doubled in the same phase. Similarly, the inversion pulses CPa ₂ and CPb ₂ from the driver circuits 11a and 11b both have the same phase waveform shown in FIG. 2 (B). Becomes Each of these added pulses is transmitted through the balanced transmission line 12 to a balanced line receiver circuit.
It is sent to 13 non-inverting inputs and inverting outputs.

According to the above configuration, even if one driver circuit is broken, as long as the other driver circuit operates normally, the clock pulse CP
Can be continuously transmitted, and reliability is improved. In this case, since only one transmission line is required, the structure is simple and the cost does not increase. However, since the output amplitude is halved, it is necessary to determine the output level of each driver circuit 11a, 11b according to the receiving sensitivity of the receiver circuit 13.

The present invention is not limited to the above configuration, and
Of course, the driver circuits of the system or more may be operated in parallel.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a clock pulse balanced transmission output circuit capable of duplexing the transmission form with a simple configuration, suppressing the cost increase and improving the reliability. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a clock pulse balanced transmission output circuit according to the present invention, FIG. 2 is a waveform diagram showing an output waveform of a driver circuit of the embodiment, and FIG. 3 is a conventional clock pulse balanced. It is a circuit diagram which shows the structure of a transmission output circuit. CP ...... the transmission clock pulses, 11, 11a, 11b ...... the balanced line preparative driver circuit, CP ₁ ...... non-inverted signal, CP ₂ ...... inverted signal, 12 ...... balanced transmission lines, 13 ...... the balanced line Receiver circuit, 14 …… Terminal resistor, 15 …… Adding circuit, CPa ₁ , CPb ₁ …
… Non-inverted pulse, CPa ₂ , CPb ₂ …… Inverted pulse, C ₁ , C ₂ ……
Coupling capacitors, R _{1 to} R ₆ ... Resistors.

Claims (1)

[Claims] 1. Inputting the same clock pulse respectively,
Multiple line driver circuits that generate and output non-inverted pulses and inverted pulses of the input clock pulse at the same time, and output by removing the DC component from the non-inverted output pulses and inverted pulses output from these line driver circuits, respectively. A plurality of coupling capacitors, and the pulses output from these coupling capacitors are converted into voltages by passing through the first resistors, respectively, and then the non-inverted pulses are merged with the inverted pulses and the addition processing is performed. ,
A clock pulse balanced transmission output circuit further comprising voltage adding means for sending each addition output through a second resistor to a pair of balanced transmission lines.