JPH0685617B2 - Method of simulating overload detection relay - Google Patents
Method of simulating overload detection relayInfo
- Publication number
- JPH0685617B2 JPH0685617B2 JP63268567A JP26856788A JPH0685617B2 JP H0685617 B2 JPH0685617 B2 JP H0685617B2 JP 63268567 A JP63268567 A JP 63268567A JP 26856788 A JP26856788 A JP 26856788A JP H0685617 B2 JPH0685617 B2 JP H0685617B2
- Authority
- JP
- Japan
- Prior art keywords
- overload detection
- power
- current
- relay
- power system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電力系統の保護に用いられている過負荷検
出リレーの機能を模擬する模擬方法に関する。The present invention relates to a simulation method for simulating the function of an overload detection relay used for protection of a power system.
一般に過負荷検出リレーは、第１図に示すような回路か
ら構成されており、過負荷検出リレーの機能を模擬する
方法としては第１図に示す回路図に基づいて実行され
る。第１図は過負荷検出リレーを示す回路図で、図にお
いて、１−１〜１−３は電力系統から導出された電流Ｉ
が過電流になったときに応動する過電流リレー、２−１
〜２−３は適当値に設定されたオンディレー時間tL,tM,
tHをもつタイマ、３は電力系統の潮流計算により得た有
効電力Ｐを入力とする電力方向リレー、４はタイマ２−
１〜２−３の出力が入力されるオア・ゲート、５はオア
・ゲート４よりの出力と電力方向リレー３の出力とを入
力とするアンド・ゲートである。Generally, the overload detection relay is composed of a circuit as shown in FIG. 1, and a method for simulating the function of the overload detection relay is executed based on the circuit diagram shown in FIG. FIG. 1 is a circuit diagram showing an overload detection relay. In the figure, 1-1 to 1-3 are currents I derived from a power system.
Overcurrent relay that responds when the overcurrent occurs in 2-1
2 to 3 are on-delay times t L , t M , which are set to appropriate values.
A timer having t H , 3 is a power direction relay that inputs active power P obtained by power flow calculation of the power system, and 4 is a timer 2-
The OR gates 5 to which outputs 1 to 2-3 are input are AND gates to which the output from the OR gate 4 and the output of the power direction relay 3 are input.
次に動作について説明する。タイマ２−１〜２−３の出
力はオア・ゲート４を介してアンド・ゲート５に入力さ
れ、電力方向リレー３の出力と論理積がとられると、過
負荷検出信号となる。Next, the operation will be described. The outputs of the timers 2-1 to 2-3 are input to the AND gate 5 via the OR gate 4, and when they are ANDed with the output of the power direction relay 3, they become an overload detection signal.
模擬において、電流Ｉは電力系統の有効電力Ｐ、無効電
力Ｑ及び電圧Ｖを用い、次式から求める。In the simulation, the current I is obtained from the following equation using the active power P, the reactive power Q and the voltage V of the power system.
〔発明が解決しようとする課題〕 従来の過負荷検出リレーの模擬方法は以上のように構成
されているので、（１）式を各サンプル時間毎に演算す
る場合、平方根の演算が含まれるため、演算に時間がか
かるという問題点があった。しかも、過電流リレー１−
１〜１−３は複数個あるので、それぞれについて（１）
式の演算を実行すると、計算処理に全体で相当量の時間
が必要となり、従って、このような処理を実行するため
に計算機の負荷を相当に大きなものにしなければならな
いという問題点があった。 [Problems to be Solved by the Invention] Since the conventional method for simulating an overload detection relay is configured as described above, when the formula (1) is calculated for each sample time, the calculation of the square root is included. However, there is a problem that the calculation takes time. Moreover, the overcurrent relay 1-
Since there are multiple 1 to 1-3, (1) for each
When the calculation of the formula is executed, a considerable amount of time is required for the whole calculation process, and therefore, there has been a problem that the load of the computer must be considerably increased in order to execute such a process.
この発明は上記のような問題点を解決するためになされ
たもので、計算処理を実行するための計算機の負荷を軽
減するようにした過負荷検出リレーの模擬方法を得るこ
とを目的とするものである。The present invention has been made to solve the above problems, and an object thereof is to obtain a simulation method of an overload detection relay that reduces the load of a computer for executing calculation processing. Is.
この発明に係る過負荷検出リレーの模擬方法は、電力系
統の有効電力の異常を判定する第１段階と、この第１段
階で異常判定がなされたときに上記電力系統よりの電流
を所定の演算により求める第２段階と、この第２段階で
求めた電流について過電流の判定をする第３段階と、こ
の第３段階で過電流の判定がなされたときに過負荷検出
信号を発生するための処理を実行する第４段階とを各段
階ごとに順次行わせるものである。An overload detection relay simulation method according to the present invention includes a first step of determining an abnormality of active power of a power system, and a predetermined calculation of a current from the power system when an abnormality determination is made in the first step. For determining the overcurrent with respect to the current obtained in the second step, and for generating an overload detection signal when the overcurrent is determined in the third step. The fourth step of executing the process and the fourth step are sequentially performed.
この発明における過負荷検出リレーの模擬方法は、第１
段階として電力系統の有効電力について過負荷判定し、
この判定で真となったときは第２段階として所定の演算
により電流を求め、第３段階として上記電流について過
電流の判定をすることにより、演算時間を短縮し、計算
機の負荷を軽減できるものである。The simulation method of the overload detection relay according to the present invention is the first method.
As a stage, an overload judgment is made on the active power of the power system,
When the result of this judgment is true, the current is obtained by a predetermined calculation as the second step, and the overcurrent is judged for the above current as the third step, whereby the calculation time can be shortened and the load on the computer can be reduced. Is.
以下、この発明の一実施例を第２図に示すフローチャー
トについて説明する。図において、ステップST6におい
て有効電力Ｐが異常（Yes）か否（No）かを判定する。
否のときは処理は終りとなり、異常のときはステップST
7に進む。ステップST7では（１）式の演算を実行する。
ステップST8はステップST7で得た電流Ｉが異常（Yes）
か否（No）かを判定する。否のときは処理は終りとな
り、異常のときはステップST9に進む。ステップST9は第
１図に示す回路による過負荷検出信号を発生する機能に
対応した処理で、これを終了すると一連の過負荷検出の
処理を終る。An embodiment of the present invention will be described below with reference to the flowchart shown in FIG. In the figure, in step ST6, it is determined whether the active power P is abnormal (Yes) or not (No).
If not, the process ends, and if abnormal, step ST
Proceed to 7. In step ST7, the operation of the equation (1) is executed.
In step ST8, the current I obtained in step ST7 is abnormal (Yes)
Whether or not (No) is determined. If not, the process ends, and if abnormal, the process proceeds to step ST9. Step ST9 is a process corresponding to the function of the circuit shown in FIG. 1 for generating an overload detection signal.
ここで、もしステップST6の有効電力ＰをステップST8の
電流Ｉよりも大きく整定すると、電流Ｉが過電流であっ
ても検出見逃しが生じる。Here, if the active power P in step ST6 is settled larger than the current I in step ST8, detection oversight will occur even if the current I is an overcurrent.
（１）式を変形すると、 P2＋Q2＝（VI）２ ……（２） となる。実系統では、電圧Ｖが0.9（p.u.）以下にはな
らないので、有効電力Ｐと無効電力Ｑとの比率は1/2以
下と考えると、（２）式により Ｐ＝±0.805I ……（３） 従って、電流Ｉを110％に整定し、（３）式より有効電
力Ｐを90％に整定すると、110％以上の過負荷をこの発
明により十分に検出できる。By transforming equation (1), P 2 + Q 2 = (VI) 2 (2) In the actual system, the voltage V does not become 0.9 (pu) or less, so if the ratio of the active power P and the reactive power Q is considered to be 1/2 or less, P = ± 0.805I (3) according to the equation (2). Therefore, if the current I is settled to 110% and the active power P is set to 90% from the equation (3), overload of 110% or more can be sufficiently detected by the present invention.
以上のように、この発明によれば、第１段階で電力系統
の有効電力が過負荷であるか異常判定をし、この第１段
階で異常と判定されたときのみ、第２段階の電流算出を
行うように構成したので、算出に時間がかかる第２段階
の処理を低減することができ、模擬に要する処理量を少
なくし計算機の負荷を軽減することができる効果があ
る。As described above, according to the present invention, it is determined in the first stage whether or not the active power of the power system is overloaded, and the abnormality is calculated only in the first stage when the abnormality is determined in the first stage. Since it is configured to perform the above-described processing, it is possible to reduce the processing in the second stage, which requires a long time for calculation, reduce the processing amount required for simulation, and reduce the load on the computer.
第１図は過負荷検出リレーの回路図、第２図はこの発明
の一実施例による模擬方法を説明するフローチャートで
ある。 １−１〜１−３……過電流リレー、２−１〜２−３……
タイマ、３……電力方向リレー。 なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a circuit diagram of an overload detection relay, and FIG. 2 is a flowchart explaining a simulation method according to an embodiment of the present invention. 1-1 to 1-3 ... Overcurrent relay, 2-1 to 2-3 ...
Timer, 3 ... Power direction relay. In the drawings, the same reference numerals indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−92715（ＪＰ，Ａ) 特開 昭57−91623（ＪＰ，Ａ) 特開 昭58−151813（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-92715 (JP, A) JP 57-91623 (JP, A) JP 58-151813 (JP, A)
Claims (1)
記電流が過電流となったときに応動する複数の過電流リ
レーと、対応する上記過電流リレーの出力を導入し、所
定のオンディレー時間を有する複数のタイマと、上記電
力系統の有効電力を導入した電力方向リレーと、上記タ
イマの各出力の論理和と上記電力方向リレーの出力との
論理積をとり過負荷検出信号を発生する回路とを備えた
過負荷検出リレーの模擬方法において、上記電力系統の
有効電力が過負荷であるか異常判定をする第１段階と、
上記第１段階で異常と判定されたときに上記電流を所定
の演算により算出する第２段階と、上記第２段階で算出
された上記電流の異常判定をする第３段階と、上記第３
段階で異常と判定されたときに過負荷検出信号を発生す
るための処理を実行する第４段階とを含むことを特徴と
する過負荷検出リレーの模擬方法。1. A predetermined on-delay is introduced by introducing a plurality of overcurrent relays that receive a current derived from a power system as an input and respond when the current becomes an overcurrent, and outputs of the corresponding overcurrent relays. A plurality of timers having time, a power direction relay introducing active power of the power system, a logical sum of outputs of the timers and an output of the power direction relay, and an overload detection signal is generated. A method of simulating an overload detection relay including a circuit; a first step of determining whether or not the active power of the power system is overloaded;
A second step of calculating the current by a predetermined calculation when it is determined to be abnormal in the first step, a third step of determining abnormality of the current calculated in the second step, and the third step.
And a fourth step of executing a process for generating an overload detection signal when it is determined to be abnormal in the step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63268567A JPH0685617B2 (en) | 1988-10-25 | 1988-10-25 | Method of simulating overload detection relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63268567A JPH0685617B2 (en) | 1988-10-25 | 1988-10-25 | Method of simulating overload detection relay |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02114818A JPH02114818A (en) | 1990-04-26 |
| JPH0685617B2 true JPH0685617B2 (en) | 1994-10-26 |
Family
ID=17460315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63268567A Expired - Lifetime JPH0685617B2 (en) | 1988-10-25 | 1988-10-25 | Method of simulating overload detection relay |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685617B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5791623A (en) * | 1980-11-28 | 1982-06-07 | Tokyo Shibaura Electric Co | Protecting relay |
| JPS58151813A (en) * | 1982-03-02 | 1983-09-09 | 株式会社東芝 | Polyphase multistage relay unit |
| JPS5992715A (en) * | 1982-11-17 | 1984-05-29 | 東京電力株式会社 | High speed simulator system for overload detection relay |
-
1988
- 1988-10-25 JP JP63268567A patent/JPH0685617B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02114818A (en) | 1990-04-26 |
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