JPH0687223B2 - Processing time monitoring method - Google Patents

Description

DETAILED DESCRIPTION [Overview] An improvement of a processing time monitoring system of a computer system having a processing device in which a scalar processing device and a vector processing device are combined. There are provided a busy signal of the scalar processing device, a busy signal of the vector processing device, a signal indicating a total processing time which is a logical sum of the two, and a signal indicating an overlap time of both processing devices which is a logical product of the both. By taking account of the mutual relationship between both processing devices by timing those signals by an appropriate means,
It is possible to accurately monitor the processing time.

[Industrial application field]

The present invention relates to a processing time monitoring system for a computer system having a processing device in which a scalar processing device and a vector processing device are combined.

In a system in which a scalar processing device and a vector processing device are connected, a program is executed by the scalar processing device, vector instructions in the program are transferred from the scalar processing device, and executed by the vector processing device, For performance evaluation and the like, it is necessary to have an appropriate processing time monitoring method that can grasp the mutual relationship between both processing devices.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a block diagram showing a configuration example of a computer system having a vector processing device and a scalar processing device.

The vector processing device 1 reads a required portion of the array data in the main storage device 2 into the vector register 3 and processes the data on the vector register 3 by the operation pipeline 4. It is output to the storage device 2.

The instruction executed by the vector processing device 1 is extracted from the program executed by the scalar processing device 7, for example,
By being passed to the instruction control unit 5 of the vector processing device 1, execution control is performed in the instruction control unit 5, and required control information by the operation instruction is sent to the vector register 3 and the operation pipeline 4.

Further, in the case of an access instruction to the main memory device 2, information regarding the access destination address and the like are sent to the access control unit 6, and data transfer between the main memory device 2 and the vector register 3 is executed.

In order to monitor the processing time, as shown in FIG. 3, the busy state of each stage of a known so-called arithmetic pipeline that constitutes the arithmetic mechanism of the scalar processing unit 7 and the vector processing unit 1 is displayed. The busy display outputs are taken out from the flip-flops 10 and 11, and the logical sum of them is generated by the logical sum gate circuit 13 and used as the in-process display signal 12.

The in-process display signal 12 is input to, for example, the performance analysis device 14, and during execution of a required program, the in-process display signal 12 measures and accumulates the time in the ON state,
It is possible to know the time when the scalar processing device 7 or the vector processing device 1 is used for the execution processing of the program.

As illustrated in FIG. 4, for example, the instructions of the program to be executed are sequentially started to be executed in the arithmetic pipeline of the scalar processing unit 7 in the instruction steps S ₁ , S ₂ , S ₃ , and S ₄ .
If the instruction fetched next is the vector instruction V ₁ , this instruction is passed to the vector processing device 1 and execution of the vector data for a relatively long time is started.

In parallel with the execution of the vector processing device 1, the scalar processing device 7
, The instruction steps S ₅ , S ₆ and S ₇ are started to be executed,
The next vector instruction V ₂ is passed to the vector processing device 1 and executed by overlapping V ₁ . And so on
S _8, S _9, V ₃ or the like is started running.

When the program is executed at such timing, the in-process display signal 12 displays the period shown by lines 20 and 21 in the example of FIG.

Here, the period in which the processing of the scalar processing device 7 and the processing of the vector processing device 1 overlap and are executed in parallel (for example, the period shown by lines 22, 23, 24 in FIG. 4) should be long. Obviously, the total processing time of the program will be shortened, and it is desirable to improve the processing time by changing the order of the program instructions as much as possible.

However, with the processing time measured by the above method,
Since only the total processing time can be obtained and the overlap time and the like of both processing devices cannot be identified, there is a problem in that accurate data for evaluating the effect of program improvement cannot be obtained.

[Means for solving problems]

 FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 10 and 11 are busy flip-flops and 30, 3
Reference numerals 1 and 32 are OR gate circuits, and 33 is an AND gate circuit.

[Work]

The output of the busy flip-flop 10 of the scalar processing unit 7 is logically ORed in the OR gate circuit 30 to generate the scalar processing unit busy signal 34, and the vector processing unit 1
The output of the busy flip-flop 11 is ORed in the OR gate circuit 31 to generate the vector processor busy signal 35.

The scalar processor busy signal 34 and the vector processor busy signal 35 are processed by the logical sum gate circuit 32 to indicate that the display signal 12 is being processed.
And the AND gate circuit 33 generates the overlap display signal 36.

By measuring the above-described four signal states by, for example, the performance analysis device 14, it is possible to obtain data that allows the performance evaluation of the program to be performed accurately.

〔Example〕

In FIG. 1, the busy flip-flops 10 and 11 are
Similar to the above-mentioned conventional description, the use of each stage of the arithmetic pipelines of the scalar processing device 7 and the vector processing device 1 is displayed.

The output of the busy flip-flop 10 of the scalar processing unit 7 is logically ORed by the OR gate circuit 30, and a scalar processing unit busy signal 34 indicating that the scalar processing unit 7 is in the process of executing an instruction is turned on. To generate. This is a signal indicating the period of the lines 25, 26 and 27 in the example of FIG.

The outputs of the busy flip-flops 11 of the vector processing device 1 are logically ORed by the OR gate circuit 31 to generate a vector processing device busy signal 35 indicating that the vector processing device 1 is in the process of executing instructions. This signal is line 2 in Figure 4.
It corresponds to 8 and 29.

The scalar processor busy signal 34 and the vector processor busy signal 35 are processed by the logical sum gate circuit 32 to indicate that the display signal 12 is being processed.
(Lines 20, 21 in FIG. 4) are generated. This signal is the same as the conventional signal.

The scalar processor busy signal 34 and the vector processor busy signal 35 generate an overlap display signal 36 by the AND gate circuit 33. This signal indicates the period during which the instruction executions of the scalar processing unit 7 and the vector processing unit 1 are being processed in parallel, and corresponds to the lines 22 to 24 in FIG.

By measuring the above-described four signal states by, for example, the performance analysis device 14, it is possible to obtain data that allows the performance evaluation of the program to be performed accurately. Further, since the busy state of each processing device can be timed, it is possible to obtain materials for proper management such as charging by the unit price of each processing device.

〔The invention's effect〕

As is clear from the above description, according to the present invention, in a computer system having a processing device in which a scalar processing device and a vector processing device are combined, accurate processing time data of the processing device for performance analysis etc. As a result, there is a remarkable industrial effect that it is easy to improve the use efficiency of the computer system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of the present invention, FIG. 2 is a block diagram showing a configuration example of a computer system, FIG. 3 is a block diagram showing a conventional configuration example, and FIG. It is an explanatory view of timing of execution. In the figure, 1 is a vector processing device, 2 is a main memory device, 3 is a vector register, 4 is a calculation pipeline, 5 is an instruction control unit, 7 is a scalar processing device, 10 and 11 are busy flip-flops, and 12 is processing. Display signal, 13, 30, 31, 32 are logical sum gate circuits, 14 is a performance analyzer, 33 is an AND gate circuit 34 is a scalar processor busy signal, 35 is a vector processor busy signal, and 36 is an overlap display signal. Indicates.

Claims (1)

[Claims] 1. A scalar processing unit (7) having a processing unit comprising a scalar processing unit (7) and a vector processing unit (1) for executing a vector instruction designated by the scalar processing unit. ), The first signal means (34) for displaying the instruction execution, the second signal means (35) for displaying the instruction execution of the vector processing device (1), the first and second signal means (34, Third signal means (12) for outputting the logical sum of the outputs of 35), and fourth signal means (36) for outputting the logical product of the outputs of the first and second signal means (34, 35) A processing time monitoring method characterized by having.