JPH0687551B2 - Synchronous circuit of confidential communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication device for maintaining confidentiality (privacy) of a telephone call in wired or wireless communication. More specifically, the device will be described. The present invention relates to a synchronous signal detection circuit of.

(B) Conventional Technology In wired or wireless communication, if a proper receiving device is used, the content of communication is intercepted by anyone, and the confidentiality of a call is impaired. As a method to solve this problem, a circuit that scrambles the audio signal and sends it out, and even if this is received by a third party, the content is not understood as it is and the processed signal is reproduced (descrambling process). So-called scrambling technology has been conventionally used in which only a receiver having a circuit) can restore a voice signal. As a conventional confidential communication system,
For example, the journal of the Institute of Electronics and Communication Engineers (August 1982) "Secret Technology" (P8
32-P834) and IEICE Technical Report CS80-149 (1980 1
January) Various methods have been introduced in "About confidential methods". Since the voice information is composed of the spectrum and its change with time, the intelligibility as voice can be lowered by the scrambling process which changes the spectrum structure. From this point of view, examples of the scrambling method that has been practically used so far include a spectrum inversion method and a frequency division replacement method. For example, Japanese Patent Publication 58-8621
(H04K1 / 04) "Secret talk system with frequency correction function" and JP-A-58-148541 (H04K1 / 04) "Secret talk circuit" relate to the spectrum inversion secret talk system, and Japanese Patent Publication Sho-58-24984 (H04K1 / 06).
"Secret device" relates to a method of performing signal processing after dividing into a predetermined spectrum, and the technical report of the Institute of Electronics and Communication Engineers CS-80-14.
9 proposes a method for improving the frequency axis conversion processing by FFT processing after converting the audio signal into a digital signal once. Therefore, the spectrum inversion method cannot take a sufficient number of combinations (keys) for the secret story. The latter two methods have many keys,
It requires a lot of filters and requires an FFT processing circuit, resulting in a large circuit scale and high cost. There were also problems such as high power consumption. From this point of view, as a scramble system in which the number of keys is large and the confidential communication performance is excellent, and the circuit configuration is simple, the applicant of the present application has previously described Japanese Patent Application No. 57-164763 "Secret communication method and its device" (September 1982). Application on 20th a month),
Proposed Japanese Patent Application No. 57-184916 "Clock circuit for confidential communication system" (filed on October 20, 1982) and Japanese Patent Application No. 58-19702 "application for confidential communication" (filed on October 20, 1983) . This uses a variable delay circuit to periodically change the frequency of the clock that controls the delay time, compressing the time axis.
This is a method in which expansion is repeated to scramble the audio signal and send it out, and the receiving side performs descrambling processing.
In this method, in order to correctly restore the original voice on the receiving side, it is necessary to perform signal processing reverse to that on the receiving side.
It is necessary to synchronize the operation of the clock applied to the variable delay circuit on the transmitting side and the receiving side. For that purpose, the synchronization signal may be provided on the high frequency side outside the voice band and the synchronization signal may be constantly sent from the transmission side to the reception side, but the transmission band is widened. Therefore, a method of synchronizing the transmitting and receiving sides without widening the transmission band is required.

As a circuit system for synchronizing the transmitting and receiving sides without expanding the transmission band in response to such a request, the present applicant has previously filed Japanese Patent Application No.
-115070 "Synchronous circuit of confidential communication device" (H04K1 / 06)
We proposed "Application on May 20, 1986." This method compresses the audio signal transmission section on the transmitting side, superimposes the synchronous signal by time division multiplexing, and then transmits the signal. This is a method of expanding the time axis of the voice signal section based on the above, and performing the restoration process of the secret story.

(C) Problems to be Solved by the Invention The present invention provides a circuit that synchronizes on the transmitting and receiving sides without widening the transmission band in such a secret communication system, and therefore, as a variable delay circuit such as a RAM. Provided is a sync signal determination circuit of a circuit which uses a memory element to periodically change the frequency of a clock for writing and reading, scrambles an audio signal, and at the same time transmits a sync signal by a time division multiplexing method. . The present invention also provides a synchronizing circuit capable of achieving more accurate synchronization in such a synchronizing signal circuit.

(D) Means and Actions for Solving Problems and Their Embodiments FIGS. 1 and 2 show the configuration of a confidential communication circuit which is the basis of the present invention. First, the structure of the transmitting side will be described with reference to FIG. (1) is a sample and hold circuit for audio signals,
(2) is an A / D conversion circuit, (3) is storage means such as RAM,
(4) is a D / A conversion circuit, (5) is an LPF, (6) is a clock frequency control circuit, (7) is a synchronization signal generation circuit, (8) is an addition circuit of a synchronization signal and a scramble signal, (9) Is a transmission circuit.

Next, the configuration of the receiving side will be described with reference to FIG. (1
(0) is the receiving circuit, (11) is the sample and hold circuit, and (1
2) A / D conversion circuit, (13) storage means such as RAM, (14)
Is a D / A conversion circuit, (15) is an LPF, and (16) is a clock frequency control circuit. (17) is a synchronizing signal discriminating circuit, and the present invention is characterized by this synchronizing signal discriminating circuit.

Next, the operation when RAM is used as the storage means will be described. A clock frequency f ₁ (t) when a signal is sampled by the output of the clock frequency control circuit (6) on the transmitting side and written to the RAM (3) and a clock frequency f ₂ (when reading from the RAM (3) ( The scrambling process is performed by changing t), and on the contrary, the receiving side reverses the RA at the clock frequency f ₂ (t) by the clock frequency control circuit (16).
The signal is restored by writing to M (13) and reading at the clock frequency f ₁ (t). f ₁ (t) and f
₂ (t) is changed with a cycle of the sum of the delay times in the transmitting and receiving RAMs (3) and (13).

Here, consider the case where f ₁ (t) and f ₂ (t) are changed as shown in FIG. f ₁ (t) and f ₂ (t) are changed in a triangular wave form with time as a cycle from f _{1L to} f _1H and f _{2L to} f _{2H with} time. However, time t _{1 to} t ₂ ,
Since _{t 4 ~t 6, t 8 ~} 10 is used as a synchronization signal section to be described later, f ₂ (t) shall not be fed. The data stored in the storage means (3) between the time (t ₁ ) and the time (t ₃ ) at the clock frequency f ₁ (t) is the clock frequency f ₂ (t).
Is read from the storage means (3) from time (t ₃ ) to (t ₄ ). Also, at clock frequency f ₁ (t), time (t ₃ )
The data taken into the storage means (3) during the period from (t ₅ ) to (t ₅ ) is read from the storage means (3) at the clock frequency f ₂ (t) during the time (t ₆ ) to (t ₇ ). And time (t ₄ )
The synchronization signal is superimposed in the section from (t ₆ ) to.

On the receiving side, conversely, at the clock frequency f ₂ (t), time (t ₃ ) ~
The data taken into the RAM (13) between (t ₄ ) and (t ₆ ) to (t ₇ ) is clocked at the clock frequency f ₁ (t) at time (t ₅ ) to (t ₅ ).
During (t ₉ ) it is read from RAM (13) and restored to the original signal. At this time, the section of the synchronization signal is ignored.

Synchronization signal synchronizing signal generating circuit (7) from the synchronizing signal section (t ₄ ~t _6), and output signals of a predetermined waveform (t ₈ ~t ₁₀₎ (e.g., a sine wave, etc.). This control is performed by the clock frequency control circuit (6).

Next, the structure and operation of the synchronizing signal discriminating circuit (17) in the present invention will be described with reference to FIG. (17-1) is the storage circuit (A) of the output of the A / D conversion circuit (12) at a certain time (tn), and (17-2) is the A / D at the time (tn-1).
The storage circuits (B) and (17-3) of the output of the conversion circuit (12) are the values of the storage circuits (A) and (17-1) and the storage circuits (B) and (17-).
The magnitude comparison circuit that compares the values of 2) and outputs binary signals of "1" and "0" according to the magnitude of the values, (17-4) is the number of samples in the synchronization signal section, It is a shift register that sequentially stores the outputs of the magnitude comparison circuit (17-3). (17-5) is a coincidence determination circuit, which compares the output of the shift register (17-4) with a predetermined data string preset from a storage element separately provided for detecting the synchronization signal, If the similarity is high, it is determined to be a synchronization signal. (17-6) is a pulse generation circuit that generates a pulse according to the output of the match determination circuit (17-5), and (17-7) is
A gate signal generation circuit for generating a gate signal for masking a voice signal section other than the synchronization signal section of the received signal, which is initialized by the output pulse from the synchronization pulse generation circuit in (17-6). . The relationship between the gate signal and the synchronizing pulse is shown in time chart in FIG. (17−
8) is a synchronizing pulse and gate signal generating circuit (17-7)
With a gate signal from the input, in the synchronization state determination circuit that determines whether the clock is synchronized on the transmitting and receiving side,
Here, it is assumed that “H” level is output at the time of synchronization and “L” level is output at the time of asynchronous.

Next, FIG. 6 shows an example of a circuit of the synchronization state judging circuit (17-8). (17-8a) and (17-8b) constitute a counter that advances in synchronization with the rising edge of the gate signal from the gate signal generating circuit (17-7) in the case of loss of synchronization. It is reset by the sync pulse from (17-10).

The operation of the synchronization state judgment circuit (17-8) will be described with reference to the time chart of FIG. In the synchronous state (a, b, c), the output of D flip-flop (17-8b) is always "H".
However, when the sync pulse is missing (d), the output becomes "L" at the next rising edge (e) of the gate signal.
At the same time, the output of the D flip-flop (17-8b) becomes "H", and no clock is input to the D flip-flop (17-8a) by the OR gate (12-8c). Therefore, if there is no sync pulse, the output remains "L". When the sync pulse arrives again (g), the D flip-flop (17-8)
b) is reset and the output returns to "H" (at this time, since the D flip-flop (17-8a) is in the reset state,
You don't have to reset it). That is, the output of the D flip-flop (17-8b) becomes "H" at the time of synchronization and "L" at the time of asynchronous, and is used as the output of the synchronization state determination circuit (17-8).

The output pulse from the pulse generator (17-6) is (17-
Controlled by the gates 9) and (17-10), the output pulse becomes effective only in the synchronizing signal section by the gate signal from the gate signal generating circuit (17-7) during synchronization. Also, when asynchronous, the output pulse is valid in all sections.

The structure of the coincidence determination circuit (17-5) is shown in FIG. (17−
5a) shows the output of the shift register (17-4) and the data string (Da) corresponding to the preset synchronization signal pattern.
Circuit that uses Exclusive OR gate, (17-5b) is shift register, (17-5c) is shift register (17-5b) "1"
The counter (17-5d) counts two types of preset data (L ₁ , L ₂ ) and the synchronization state determination circuit (17-8)
The multiplexer (17-5e) for switching and outputting according to the output from the counter (17-5c) is a subtraction circuit between the output of the counter (17-5c) and the output data of the multiplexer (17-5d). ) Is the multiplexer (17-5
When it is less than the value of the data in d), the pulse generation request signal is output.

Next, the operation of the synchronization determination circuit will be described in detail with reference to FIGS. 4 and 8. When the output of the A / D conversion circuit (12) is stored in the storage circuit (A) (17-1), the value of the storage circuit (B) (the immediately preceding A / The output of the D conversion circuit (12) is stored), and if [value of memory circuit (A)] ≧ [value of memory circuit (B)], then “1”, [memory circuit In the case of (value of (A)) <[value of memory circuit (B)], "0" is output (or vice versa). The output of the magnitude comparison circuit (17-3) is sequentially stored in the shift register (17-4) to obtain a K-bit data string (K is the number of stages of the shift register and is equal to the number of samples in the synchronization signal section. ). Every time new data is taken into the shift register (17-4), the K-bit data string (denoted as Db) and the data string (Da) corresponding to the sync signal pattern are detected by the coincidence determination circuit (17-5). Exclusive-OR to find the correlation with
Both data are input to the gate (17-5a) and the output is loaded to the shift register (17-5b). After that, the mismatch count counter (17-5c) is generated by the separately provided clock (CK ₁ )
Output to. The disagreement counter (17-5c) counts "1" in the shift register, that is, the number of disagreements between Da and Db.
Let M be the obtained number of mismatch bits. Since the multiplexer (17-5d) outputs L (the above L ₁ or L ₂ ) which is the allowable value of the number of unmatched bits in consideration of the influence of noise and the like, the subtraction circuit (17-5e) outputs (M- L),
If M ≦ L, it is determined that the signal is a synchronization signal, and a pulse request signal is output. When the pulse generation circuit (17-6) receives the pulse generation request signal, it outputs a pulse. When the data strings within the allowable value are adjacently obtained two or more times, the case where the number of mismatch bits is the minimum is selected and it is determined that the data is a synchronization signal. The receiving side clock frequency control circuit (16) is initialized by the output pulse from the pulse generating circuit (17-6) to synchronize the clocks on the transmitting and receiving sides.

The value of the L is output to by connexion control from the synchronization state determination circuit (17-8), the time synchronization L _1, the asynchronous time is switched by a multiplexer (17-5D) to L ₂ is output.
Set L ₁ and L _{2 so} that L ₁ > L ₂ . That is, the allowable value of the number of unmatched bits becomes smaller in the asynchronous case than in the synchronous case, and as a result, the criterion for determining the synchronous signal becomes stricter.
Since the coincidence determination between the received signal and the synchronization pattern is always performed at the time of non-synchronization, if the allowable value of the number of non-coincidence bits is increased, the audio signal is erroneously determined as the synchronization signal and it takes time to pull in the synchronization. On the other hand, during synchronization, the gate signal generator (17
Since the voice signal section is masked by the output gate signal from -7) and the coincidence judgment with the sync pattern is performed only in the expected sync signal section, a correct sync signal can be judged even if the allowable value of the number of mismatch bits is large. There is less synchronization loss.

(E) Effect of the Invention As described above, according to the synchronizing circuit of the present invention, it is possible to prevent the spread of the transmission band and the mixing of the synchronizing signal component into the voice band,
In addition, since it can be accurately synchronized, it is very useful as a confidential communication device.

[Brief description of drawings]

1 and 2 are block diagrams of the transmitting side and the receiving side of the confidential communication device which is the basis of the present invention, FIG. 3 is an explanatory diagram of a clock frequency change, and FIG. 4 is a synchronizing signal discriminating circuit of the present invention. FIG. 5, FIG. 5 is a timing diagram of a gate signal and a synchronization pulse, FIG. 6 is a configuration diagram of a synchronization state determination circuit, FIG. 7 is a timing diagram showing the operation of the synchronization state determination circuit, and FIG. It is a block diagram of a circuit. (1) ・ (11) ... Sample and hold circuit, (2) ・
(12) ... A / D conversion circuit, (3). (13) ... storage means,
(4) / (14) ... D / A conversion circuit, (5) / (15) ... LPF,
(6) / (16) ... Clock frequency control circuit, (7) ... Synchronous signal generation circuit, (8) ... Addition circuit, (17) ... Synchronous signal determination circuit, (17-1) ... Storage circuit (A), (17-2) ...
Storage circuit (B), (17-3) ... Size comparison circuit, (17-
4) ... shift register, (17-5) ... match determination circuit,
(17-6) ... Pulse generation circuit, (17-7) ... Gate signal generation circuit, (17-8) ... Synchronized state determination circuit, (17-9)
... AND gate, (17-10) ... OR gate, (17-5a) ... Exc
lusive OR gate, (17-5b) ... shift register, (17
-5c) ... Mismatch counter, (17-5d) ... Multiplexer, (17-5e) ... Subtraction circuit, (18-8a), (17-8b) ...
D flip-flop, (17-8c) ... OR gate.

Claims (1)

[Claims] 1. A sample hold circuit for sequentially sampling and holding an audio signal in accordance with a clock pulse, an A / D conversion circuit for A / D converting an output signal of the sample hold circuit, and an output of the A / D conversion circuit. Storage means for storing and outputting, a D / A conversion circuit for D / A converting the output signal of the storage means, and a clock frequency control circuit for controlling the frequency of the clock pulse, and a receiving side of a communication system The output of the A / D conversion circuit on the receiving side is further compared with the output of the A / D conversion circuit immediately before the output, and "1" or "0" is set to 2 depending on the magnitude. A magnitude comparison circuit for converting to value data, a storage circuit for sequentially storing the output of the magnitude comparison circuit and obtaining a predetermined data string according to the length of the synchronization signal section,
A coincidence determination circuit that compares the output of the storage circuit with a predetermined data string preset for synchronization signal detection, a synchronization state determination circuit that determines whether or not a synchronization state is present, and a synchronization signal that is expected during synchronization. A gate signal generating circuit for setting only a section as a synchronizing signal detection section, and changing the sampling clock frequency at the time of writing and the sampling clock frequency at the time of reading of the storage means by the clock frequency control circuit. To restore the confidential signal transmitted from the transmitting side, and to synchronize the clock operation of the transmitting and receiving sides with the synchronizing signal transmitted by time division multiplexing from the transmitting side during the time interval of the voice signal from the transmitting side. At this time, the predetermined data sequence for detecting the synchronization signal and the output data sequence of the storage circuit are compared by the coincidence determination circuit, and both data sequences are compared. When the frequency is high, the output data string of the storage circuit is determined to be a synchronization signal, and the determination reference of the synchronization signal when the synchronization timing of the clock operation of the transmission / reception side is set is switched according to the output signal from the synchronization state determination circuit. ,
In the asynchronous state, the judgment criterion in the asynchronous state is stricter than that in the synchronous state, and in the synchronous state, only the expected synchronous signal section is set as the synchronous signal detection section by the output of the gate signal generation circuit. A synchronization circuit for a confidential communication device, which reduces misjudgment of a synchronization signal to shorten a pull-in time to a synchronization state and reduces loss of synchronization in the synchronization state.