JPH0690715B2 - Mask pattern verification method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a mask pattern verification method, and more particularly to a method for verifying layout data of a mask pattern for manufacturing integrated circuits such as LSIs at high speed and reliably.

[Prior Art] An integrated circuit, particularly a large scale integrated circuit (LSI) is usually manufactured through the following processes.

(B) Create LSI functional specifications based on system specifications,
A functional design process that designs the behavioral details.

(B) A logic design process for designing with a focus on the connection relationship between gates, that is, the logic circuit configuration.

(C) A device design process that designs the shape and electrical characteristics of the transistors used based on the LSI manufacturing conditions.

(D) A circuit design process in which the basic logic unit used for the logic cell library and the transistor library obtained by device design are combined to design a basic circuit or circuit cell, and the performance is predicted by a circuit simulator.

(E) A layout design process that creates LIS mask patterns.

(F) A manufacturing process for manufacturing an LSI using the mask pattern of the layout design process.

Of these processes, the layout design process is the most important design process in LIS design, and the placement of logic gates is performed using the connection information obtained by logic design and the logic cell library prepared by circuit design. It is the process of wiring, and is said to be the work of controlling the death of the performance of LSI.

Therefore, it is necessary to verify the electrical performance of the data after the layout design again with a logic simulator, a circuit simulator, or the like. Of course, if layout can be done automatically using a computer, verification is unnecessary, but human intervention is required to obtain a highly complete layout, or by partially correcting the result of automatic layout. Inevitably, there is a risk that errors will be mixed in, so verification is essential.

Errors in the mask pattern data include errors that violate geometrical design rules that are determined by the manufacturing conditions of the LSI, errors that the given logical connection is not realized, and various types of errors for detecting these errors. A method can be considered.

As a method of detecting a logical connection error, a method of detecting a logical connection information from a mask pattern, collating it with the logical connection data extracted from the circuit diagram data, and performing verification is widely used.

[Problems to be Solved by the Invention] However, the conventional mask pattern verification method has some problems. In FIG. 3 (A), the substrate 10
An analog circuit area 12 composed of a plurality of elements, a digital circuit area 14, and an analog GND pad A-GND16 and a digital GND pad D-GND18 for connecting to the substrate 10 on the GND line are formed on the top. The circuit area 12, 1
As shown in FIG. 3B, 4 are separated from each other by a PN junction or the like, and the separation regions are electrically connected to each other via the substrate 10.

When verifying a mask pattern corresponding to such an element layout, for example, one element u in the analog circuit area 12 and A-GND are connected, and one element x and D- in the digital circuit area 14 are connected. When the GND is connected, the A-GND and the D-GND are connected via the substrate 10, so that it is erroneously verified that the element u and the element x are short-circuited.

Therefore, conventionally, the above-mentioned problem has been solved by dividing the verification process into two. That is, first, A-GN
Assuming that D and D-GND are not electrically connected, verify the connection between each element and between element u and A-GND or element x and D-GND, and then name the GND pads the same. By doing so, the connection relation between A-GND and D-GND is recognized and the connection relation is verified, and the connection between each element and the connection between each element and the GND line are correctly verified.

Of course, when there is only one type of GND pad, short-circuiting with other GND lines via the substrate 10 does not occur as described above, but in this case as well, it is necessary to divide the verification process into two. Becomes That is, when the circuit I area 20, the circuit II area 22 and the GND pad 24 are formed on the substrate 10 as shown in FIG. Although the wiring 26 shown by the alternate long and short dash line is not connected, the circuit I region 20 and the circuit II region 22 are connected via the substrate contact 28 of each circuit.
Is connected, and it is impossible to detect this even though there is an error originally. Therefore, even in this case, first, it is necessary to verify the connection between the elements without recognizing the connection relationship via the substrate.

As described above, conventionally, in order to correctly verify the logical connection of the mask pattern, the verification process has to be performed twice, and this has been a cause of an increase in LSI development time and development cost.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a mask pattern verification method capable of surely verifying a logical connection of a mask pattern by a single process, aiming at reduction in development period and cost. Especially.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides mask pattern data for manufacturing an integrated circuit in which a plurality of elements are formed on a substrate, and circuit diagram data given in advance. And the GN between each element and each element in the mask pattern.
In a mask pattern verification method for verifying a connection state with a substrate on a D line, an element having two terminals is virtually provided at a connection portion between each element and a GND line, and one terminal of the virtual two-terminal element is provided on the substrate. It is characterized by verifying the connection between each element and between each element and the substrate on the GND line by verifying the connection between each element and the other terminals of the virtual two-terminal element with the connected GND terminal. .

[Operation] As described above, the present invention treats the connection between each element and the GND line as the connection between the metal wiring and the GND line of the substrate when verifying the connection state between each element and between each element and the GND line. Instead, a two-terminal element, one terminal of which is a GND terminal connected to the substrate, is virtually introduced and treated as a connection between this virtual element and each element.

Then, since each element connected to the substrate is not directly electrically connected via the substrate, it is not erroneously verified as short-circuited, and the connection between each element and this virtual element is prevented. By performing the verification, it is possible to verify that each element is connected to a predetermined GND line, and it is possible to reliably verify the connection between each element and the connection between each element and the GND line in one process.

[Embodiment] A preferred embodiment of a mask pattern verification method according to the present invention will be described below with reference to the drawings. In addition, in the present embodiment, in order to clarify the difference from the conventional method, the conventional method has to be verified twice separately in FIGS. 3 (A) and 3 (B).
It was decided to verify the mask pattern shown in.

FIG. 1 is a flow chart in this embodiment. The mask pattern data 30 created through the above-mentioned processes (a) to (e) and desired circuit diagram data 32 given in advance are stored in the memory. Then, the logical connection information of each element is extracted from the data stored in these memories (process 100, process 110). And
Both extracted information are collated (process 120), and the result is output (process 140).

Here, a characteristic of this embodiment is that, when extracting logical connection information from each data, as shown in FIG. 2, a connection portion between each element of the analog circuit 12 and an analog GND pad and a digital circuit. 14 elements and digital GND
The element 34 and the element 36 each having two terminals are virtually set at the connection portion with the pad, and the connection information is extracted assuming that the connection between each element and the GND line is performed through this virtual element. Is what you are doing.

That is, in the mask pattern in which one element u in the analog circuit 12 is connected to A-GND, the connection information of element u → A-GND is not extracted, but the two terminals 34a, 34b of the virtual element 34 are extracted. The connection with one terminal 34a (not shown) is extracted as element u → element terminal 34a.

Similarly, when one element x in the digital circuit 14 is connected to D-GND, the connection information of element x → D-GND is not extracted but the two terminals 36a, 36b ( The connection with one terminal 36a (not shown) is extracted as element x → element terminal 36a. And these virtual elements 34,
The other terminals 34b and 36b of the 36 are used as GND terminals and are electrically connected to each other through the substrate 10 to extract information.

Even when extracting the logical connection information from the circuit diagram data given in advance, if each element is in contact with the substrate and is on the GND line in the original circuit diagram, it is connected via the two terminals of the virtual element. Information as if it exists.

The connection information of the mask pattern data and the circuit diagram data extracted in this way is then stored in the LVS (Layout Versus S
chematic) and other layout verification programs are used to check whether they match each other.

Then, the connection information between each element is, for example, element u → terminal 34a of element 34 element x → terminal 36a of element 36 element terminal 34b → (substrate) → element terminal 36b. Can be treated as a connection between the virtual element and the virtual element. Therefore, unlike the conventional case, it is not erroneously verified that the element u and the element x are short-circuited via the substrate, and the logical connection can be reliably verified by one process.

In this embodiment, two Gs of A-GND and D-GND are used.
Two virtual two-terminal elements are set in correspondence with the presence of the ND pad, but the present invention is not limited to this, and the necessary number of virtual two-terminal elements are provided at the connection portion with the GND line. , Can be verified.

[Effects of the Invention] As described above, according to the present invention, the mask pattern can be verified by a single process, and the development period and cost of the LSI can be reduced.

[Brief description of drawings]

FIG. 1 is a flow chart of an embodiment of a mask pattern verification method according to the present invention, FIG. 2 is an illustration of a virtual two-terminal element in the same embodiment, and FIG. 3 is an illustration of a conventional mask pattern verification method. is there. 10 …… Board 12 …… Analog circuit area 14 …… Digital circuit area 16 …… Analog GND pad 18 …… Digital GND pad 20 …… Circuit area I 22 …… Circuit area II 24 …… GND pad

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/027 21/82

Claims (1)

[Claims] 1. A mask pattern data for manufacturing an integrated circuit in which a plurality of elements are formed on a substrate is collated with circuit diagram data given in advance, and between the elements and in the mask pattern. In a mask pattern verification method for verifying a connection state with a substrate on a GND line, an element having two terminals is virtually provided at a connection portion between each element and the GND line, and one terminal of the virtual two-terminal element is provided on the substrate. The connected GND terminal is used, and the connection state between each element and between each element and the substrate on the GND line is verified by verifying the connection between the other terminals of the virtual 2-terminal element and each element. Mask pattern verification method.