JPH0616062B2 - Circuit connection verification device - Google Patents

Description

The present invention relates to a layout design of an LSI and a verification system for artwork data after the design.

(Prior Art) At present, a wiring check for artwork data is performed by manually tracing a basic circuit diagram and a plot diagram on which artwork data is drawn, by tracing each other's wiring with a colored pencil or the like. However, because the verification itself is manual,
There are so many oversights, and the fact is that checks are repeated many times.

In addition, with the increase in VLSI, it is becoming more difficult to perform manual checks, and the number of man-hours and the number of revisions of mask manufacturing in several steps are large, resulting in a large mask cost.
It goes without saying that the development period will be long.

(Object of the Invention) An object of the present invention is to provide a collation system for artwork data of an LSI that can eliminate the need for a large number of steps and manual checks.

(Structure of the Invention) The present invention is generally a method of electronically storing a basic circuit diagram when checking artwork data for an LSI (for example, a method of reading the coordinates of the circuit diagram by a digitizer or the like and storing it in a disk or the like) The artwork data to be checked is also stored electronically and collated by a computer. Especially, after making a tree representation of the basic circuit diagram data, It is characterized by matching.

Here, the tree expression means the following. That is, a state in which some points are arranged in a line and the points are connected by one line is called a branch. In this case, when the end point is the root, the other end point is the leaf. Further, similar branches are branched from each point to form some branches. What is expressed in this way is called a tree expression. In the present invention, the wiring and the element on the circuit diagram are associated with each other and expressed as one point.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 shows a system configuration according to an embodiment of the present invention.
This system includes a digitizer 101 for inputting LSI artwork data to the system, a workstation 102 for inputting circuit diagram data, storage media 13 and 104 for electronically storing each of them, and a computer for the entire system. The system controller 105 for controlling by, the plotter 106 for plotting and outputting the defective data after verification, the printer 107 for outputting the list, and the pass line 108 for electronically transferring the data. Further, a is a drawing in which artwork data is drawn, b is a circuit drawing in which a circuit is drawn, and C and D are plots and lists output after processing from this system, respectively.

The collating process of this system will be described in detail below based on an example of the bipolar transistor circuit shown in FIG. In the circuit configuration of FIG. 2, external terminals 1 to 5 are shown with text. The capacitor 6 is connected to the external terminal 1 and the wiring 8. Resistor 7 is external terminal 3 and wiring 8
The resistor 9 is connected to the wiring 8 and the external terminal 5, and the resistor 10 is connected to the external terminal 3 and the wiring 11. The base of the transistor 12 is connected to the wiring 8, the emitter wiring 13 is connected to the collector 11, and the collector is connected to the wiring 11. The resistor 14 connects the wiring 13 and the external terminal 2 to the resistor 15
Are connected to the wiring 11 and the external terminal 4, respectively.

When the circuit diagram is represented by the tree described above, common conditions common to all the circuits are given. The first condition is to weight the terminals connected to the wiring and elements of the circuit diagram. In the case of wiring, the order is transistor terminal, diode terminal, resistance terminal, and capacitor terminal. further,
For transistors and diodes, the base, emitter, collector, anode, and cathode are weighted in that order. The second condition is that the transistor in terms of circuit operation has a transfer function (processing operation until a signal is input and output in terms of circuit operation), so that the directionality of this transfer is weighted. When the processed signal is input from the base terminal, it is transferred to the collector terminal and the emitter terminal. In this case, the collector terminal side is given priority. Then, when input from the collector terminal, it is transferred to the emitter terminal. When input from the emitter terminal, collector transfer is performed. The transfer routes are weighted in the above order.

Next, the following conditions are given for each circuit diagram. The first condition is
Designate DC stable wiring and external terminals such as power supply and ground wiring. In the case of FIG. 2, the external terminal 3 is the power supply V _CC and the external terminal 5 is the ground GND. The second condition is that an external terminal (hereinafter, I
A combination of an N terminal) and an external terminal (hereinafter referred to as an OUT terminal) to which the signal is transferred and output is designated. In the case of FIG. 2, the IN terminal is the external terminal 1 or 2.
(2 may double as an input terminal and an output terminal, but is assumed to be an IN terminal in this circuit), and an OUT terminal is an external terminal 4. Such a condition is such that the text (IN1, IN2, IN2) added to the external terminal for each condition item.
OUT, V _CC , GND) is given as a card image.

The tree expression process is performed using the above-mentioned common condition and condition condition for each circuit diagram. This processing traces the route (hereinafter referred to as AC line) to which the signal is transferred from any IN terminal (1 or 2 IN terminals in FIG. 2).
At this time, the DC stable wiring is not traced.

In the case of FIG. 2, tracing is started from the external terminal 1 (additional text is IN1), and goes through the capacitor 6 to the wiring 8 as it is. Although the resistors 7 and 9 and the base terminals of the transistor 12 are connected to the wiring 8, the transistor terminal reaches the transistor 12 because the transistor terminal has a higher weighting rank than the resistance terminal. In the transistor 12, since it is input from the base terminal, it is transferred to the collector terminal and reaches the wiring 11. In the wiring 11, the resistors 10 and 15 are connected, but the terminal of the resistor 15 is selected. This is because when the resistance 10 is traced, a DC stable line is reached. From the resistor 15 to the OUT terminal (the additional text is OUT) 4. The AC line traced in this way is represented as a tree as shown in FIG.

In the tree representation of FIG. 3, A to E represent branches and 1 to
Reference numeral 15 corresponds to the elements and wirings in FIG. The DC stable line is divided and expressed as shown in FIG. 3 by two branches showing the power source. The AC line traced first with respect to FIG. 2 is represented by a tree having the external terminal 1 as a root and the external terminal 4 as a leaf, as shown in FIG.

Next, the same tracing is performed from the remaining IN terminal (external terminal 2) to the line that first becomes the AC line. This branch is shown as branch B in FIG. After tracing the AC line, the untraced portion is set as the DC line and traced from the AC line toward the DC stable line. The branches established at this time are shown in FIG. 3, branches C, D and E.

In this way, the circuit diagram is represented as a tree. The tree-represented data is stored electronically like the circuit diagram.

Next, the artwork data that is the target of the connection check is
Perform circuit restoration processing before verification.

An example of the artwork data stored electronically is shown in FIG. In FIG. 4, 21 to 25 indicate external terminals to which a test is added according to the circuit diagram, and 26 indicates a resistance pattern. Reference numeral 27 indicates a contact for resistance. 28 indicates a contact for the capacitor. Reference numerals 29, 30, and 31 denote collector, base, and emitter contacts for the transistor, respectively. Reference numerals 32 and 33 denote electrode patterns for capacitors. 34-42 show aluminum wiring patterns.
42 shows an example of a portion in which a wiring mistake is made in the circuit diagram of FIG. Reference numeral 43 indicates a recognition pattern of the capacitor element.

The first method of restoring a circuit is to recognize an element by logical operation of graphic data. For example, in the case of a capacitor, reference numeral 43 in FIG. 4 is a recognition-dedicated pattern, and this can be done by ANDing the recognition-dedicated pattern 43 and the aluminum wiring pattern. Resistors can be processed in the same way. For complicated transistors, etc., the entire device is made into cells, and the contacts with aluminum wiring define contacts 29, 30, 31 as respective terminals (base, emitter, collector). It becomes possible by doing.

The element is recognized by such a method, and the circuit is restored for each aluminum pattern to be the wiring on the circuit by associating the contact pattern included in the aluminum pattern as the terminal of each element. Further, the text (21 to 25 in FIG. 4) showing the external terminals is added to the restored circuit diagram as it is. The circuit diagram restored in this way is
Shown in the figure. 34 to 41 and 42 shown in the same circuit diagram correspond to 34 to 41 and 42 shown in FIG. 4. Before the collation, this circuit is also electronically stored.

The above pre-processing is performed to perform connection verification processing. The collation is performed between the basic circuit diagram data (FIG. 2) and the circuit diagram (FIG. 5) restored from the artwork data.
The collation is performed from the root toward the leaf for each tree-shaped branch (FIG. 3). At the beginning of collation, the texts added from the IN terminal to the external terminal at the beginning have the same expression, so that there is a one-to-one correspondence. In the verification, the number of connecting terminals and the type of terminal are checked for each wiring and each element. When matching is performed on the branch A shown in FIG.
First, the IN terminal 1, which is the root, is checked. This IN terminal 1
The number and types of terminals connected to the
Since both of the figures are capacitor terminals, the external terminal 1 (with text: IN1) is judged to be the same for the artwork data. Next, the number and type of terminals of the capacitor 6 are determined. Also in this case, since the number of terminals is 2 and the type is a capacitor, it can be determined that the artwork data is the same. Next, the wiring 8 is checked. In this case, the number of terminals is the same, but the type of terminals is different. Therefore, the ray mount data (FIG. 35) corresponding to this wiring and the element to which different terminals are connected (in FIG. 5). Wiring 35 and 41
The artwork data (capacitor connected to the capacitor) (Fig. 33, 28 in Fig. 4) is plotted and output. in this case,
Since the wiring 8 is different, the element 12 cannot be collated with the branch A in FIG. 3, and the same collation is performed from the leaf side (4 in FIG. When the matching of the branch A is completed, the branch B is similarly subjected from the root to the leaves. In this way, each branch is collated.

As described above, the basic circuit diagram is represented as a tree,
The collation can be easily performed by restoring the artwork data to the circuit. 5 is different from FIG. 2 in the wirings 35 and 41, and the device patterns connected to the wirings 35 and 41 are output from the system as a plot and as a list with the same contents. FIG. 6 shows an example of plotting output of different artwork data as a result of collation.

In the figure, 26, 27, 28, 33, 35 and 41 correspond to the artwork data shown in FIG.

(Effects of the Invention) As described above, according to the present invention, it is possible to easily output the check results as they are without any manual check of the circuit connection of the artwork data, which was conventionally done manually. For artwork data and circuit diagram data, the data expressed by the conventional design can be used as it is. In this way, the system should easily solve the above-mentioned problems. The applicable circuit can be easily applied not only to the bipolar circuit but also to a circuit using MOS and I ² L devices generally used as a logic circuit, and a circuit composed of these.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a bipolar transistor circuit. FIG. 3 is a diagram when FIG. 2 is represented by a tree. FIG. 4 shows an example of artwork data for FIG. 2, and FIG. 2 shows an example of connection error. FIG. 5 is a circuit diagram in which the circuit is restored from the artwork data. FIG. 6 shows an example of data in which different artworks are plotted and output by this system. 101 ... Digitizer, 102 ... Workstation, 103, 104 ... Storage device, 105 ... System controller, 106 ... Plotter, 107 ... Printer, 108 ... Bus line.

Claims (1)

[Claims] 1. A circuit connection collation device for performing circuit connection collation between circuit diagram data and artwork data, wherein a circuit representation of the circuit diagram data is performed and a circuit connection with the artwork data is made for each branch of the tree. In the tree expression, the route in which the signal processing is performed from the input terminal of the signal to the output terminal of the signal is defined as the first branch in the tree expression, and from this route, the route toward the DC stable wiring is defined. A circuit connection matching device, wherein each branch is expressed as a branch, and the input terminal side is defined as a root and the output terminal side is defined as a leaf for each branch.