JPH0690729B2 - Microprocessor and output port - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and an output port configuration, and provides a microprocessor and an output port with less time base error of a signal output through the output port. .

2. Description of the Related Art In recent years, Neumann microprocessors have been widely used in all fields, and their configurations include a program storage means for storing a program consisting of a series of instructions to be sequentially executed and a data storage for reading / writing digital data. Means, an arithmetic means for executing arithmetic operation of digital data, a data bus connecting the input / output terminal of the data storage means and the input / output terminal of the arithmetic means, and the above-mentioned means based on an instruction sent from the program storage means. Control means for controlling the operations of the data storage means and the arithmetic means, a timing generator for generating an instruction execution timing signal, and a specific instruction stored in the program storage means based on the output of the timing generator. Characterized by having instruction selection means To be In addition, the typical structure is Japanese Patent Publication Sho 58-33.
No. 584 (hereinafter referred to as Document 1).

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, since the Neumann type microprocessor as described in Document 1 executes data processing in a predetermined order, it is asynchronously input as the program becomes huge. The cycle of capturing external data and processing of data based on it becomes long, and as a result, the time variation from the occurrence of an event to the output signal from the microprocessor, that is, the time base error is considerably large. I have a problem. Conventionally, a means called an interrupt has been used to deal with such a problem. However, even if an interrupt request is made, it cannot move to the interrupt process unless the instruction being executed at that time is processed. There is a problem that a timebase error occurs in the time itself from when an interrupt is accepted until the interrupt service routine is actually started.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an output port and a microprocessor capable of outputting a series of signal patterns with a small time base error.

Means for Solving the Problems To achieve this object, a microprocessor of the present invention includes a free-running counter that performs a cyclic counting operation based on a specific clock signal, and time data that stores at least two or more types of digital data. Storage means, time data selection means for selecting any one of the time data storage means, count data storage means for storing count data of the free running counter in synchronization with an external input signal, and count data storage An adder for adding the data of the means and the data of the time data storage means, a comparison means for comparing the count data of the free running counter and the addition data of the adder, and for outputting a coincidence signal when they coincide. , A cyclic counting operation based on the coincidence signal output from the comparison means. And a master latch section for storing any one of the master latch sections, a master latch section for storing the same number of digital data as the time data storage section, and data for the master latch section. It has an output port including a slave latch unit for taking in a match signal output from the comparing means.

The output port of the present invention includes a free-running counter that performs a cyclic counting operation based on a specific clock signal, an adder that adds the count data of the free-running counter and time data prepared in advance, and the free-running counter. Comparing the count data of the running counter with the output data of the adder, comparing means for outputting a coincidence signal when they coincide, a pointer for performing a cyclic counting operation based on the coincidence signal output from the comparing means, The master latch unit for storing at least two kinds of digital data, the master latch selecting unit for selecting one of the master latch units according to the content of the pointer, and the data for the master latch unit are compared. The slave latch that is acquired based on the coincidence signal output from And a part.

Effect of the Invention The present invention can obtain a microprocessor and an output port having a time base error of a signal output through the output port with the above-described configuration.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the microprocessor of the present invention.

In FIG. 1, TMGR100 is a timing generator that generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and its output signal is supplied to the PC200, ICR900 and FRC1000. P
The LA300 is a programmable logic array, and stores a program including a group of instructions that are sequentially executed.
PC200 is a program counter, and selects a specific instruction stored in PLA300 based on the output signal of TMGR100.
FRC1000 is a free-running counter, which performs a cyclic counting operation using the output signal of TMGR100 as a clock signal. The count data of FRC1000 is supplied to ICR900 and output port 1100 via local bus 1400. The ICR900 is an input capture register circuit, and when the edge of the input signal applied to the external signal input terminals 20 to 27 arrives, the count data of the FRC1000 at that time is ICR90.
Stored in a specific register within 0 (When multiple input signal edges arrive at the same time, FRC1
The count data of 000 is stored. ), And has a function of setting an input signal reception flag (not shown). The command transmitted from the PLA 300 is ALU 400, address decoder 600 (shown as address decoder A in the drawing), address decoder 800 (shown as address decoder B in the drawing) via command bus 1300. , ICR900 and output port 1100. Further, the data bus 1200 is connected to the ALU 400, ROM 500, RAM 700, ICR 900 and output port 1100. ALU400 is an arithmetic unit that executes arithmetic and logical operations on digital data. The ROM 500 is a read-only memory that sends digital data stored in advance to the data bus 1200. The RAM 700 is a random access memory that reads and writes digital data via the data bus 1200. The output port 1100 outputs a series of signal patterns that can be changed by a program from the signal output terminals 30 to 37 with reference to an external signal input from the signal input / output terminal 40. The address decoder 600 selects the address of the ROM 500, and the address decoder 800 selects the address of the RAM 700.

The operation of the microprocessor of the present embodiment configured as described above will be described below with reference to FIGS. 1 to 3.

The TMGR100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and supplies this signal to the PC200, ICR900 and FRC1000. PC200
Based on the output signal of TMGR100, a specific instruction is selected from the instruction group stored in PLA300, and PLA300 sends the instruction selected by PC200 to command bus 1300. ALU4
00 executes arithmetic and logical operations of the digital data sent via the data bus 1200 according to the command sent from the command bus 1300, and sends the result to the data bus 1200. The address decoder 600 selects a specific address based on an instruction sent via the command bus 1300, and the ROM 500 transfers the digital data stored in the storage means corresponding to the address selected by the address decoder 600 to the data bus 1200. Send to. The address decoder 800 selects a specific address based on an instruction sent via the command bus 1300, and the RAM 700 sends data from the data bus 1200 to the storage means corresponding to the address selected by the address data 800. It stores the incoming digital data or sends the already stored digital data to the data bus 1200.

Next, the output port 1100 will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing the internal structure of the output port 1100 of FIG. 1, and FIG. 3 is a timing chart of the main part.

In FIG. 2, when an external signal is input from the input terminal 40, the FRC register 1180 latches the count data of the FRC1000 at that time and supplies the latched data to the adder 1190.
The time data registers 1111 to 1114 (indicated as time data registers A to D in the figure) are registers for storing timing data for outputting data from the output port, and the time data selection circuit 1200 includes the time data register 1111.
Select one of the registers from 1 to 1114 and add the digital data stored in the selected register to the adder 1190
Supply to. The adder 1190 adds the data in the FRC register 1180 and the data in the time data register selected by the time data selection circuit 1120, and compares the result with the comparison circuit.
Supply to 1130. The comparator circuit 1130 receives the digital data supplied from the adder 1190 and a first bus via the local bus 1400.
The count data supplied from the FRC1000 in the figure is compared, and if they match, a match signal is output to the slave latch circuit 1160.
And to the pointer circuit 1170. Also, the comparison terminal 1130
Starts the comparison operation when an external signal is supplied from the input terminal 40, and performs the comparison operation until the pointer circuit 1170 supplies the overflow signal. The address decoder 1110 (indicated as an address decoder C in the drawing) stores the digital data in the time data registers 1111-1114 via the data bus 1200 according to the instruction sent from the command bus 1300. Select an address. Master latches 1141 to 1144 (indicated as master latches A to D in the figure) are latches for storing output data, and the master latch selection circuit 1150 is a master latch 1141.
~ 1144 is selected, and the digital data stored in the selected master latch is supplied to the slave latch circuit 1160. Further, the address data 1140 (indicated as an address decoder D in the figure) is transmitted via the command bus 1300 according to an instruction transmitted from the command bus 1300, and the master latches 1141 to 1141 are transmitted via the data bus 1200.
Select an address when storing digital data in 44. The pointer circuit 1170 performs a cyclic count operation based on the match signal of the comparison circuit 1130, and supplies the count data to the time data selection circuit 1120 and the master latch selection circuit 1150. Further, the pointer circuit 1170 supplies an overflow signal to the comparison circuit 1130 when the counting operation has completed one cycle. Further, the pointer circuit 1170 initializes the count data by the initialization instruction sent from the command bus 1300.

The operation of the output port 1100 configured as above will be described.

The time data registers 1111-1114 are programmed to
Arbitrary digital data is written. For example, when time data is written to the time data register 1111 by a program, first, the address decoder 11 is executed according to the instruction sent via the command bus 1300.
10 selects the time data register 1111, and the selected time data register 1111 stores the digital data sent via the data bus 1200. Similarly, arbitrary digital data is written in the time data registers 1112-1114. Further, the master latches 1141 to 1144 are similarly programmed with arbitrary digital data written by the program.

Time data selection circuit 1120 and master latch selection circuit 11
Reference numeral 50 selects the time data register and the master latch, respectively, according to the count data supplied from the pointer circuit 1170.

Count data “0”, “1” of the pointer circuit 1170,
For “2” and “3”, the time data selection circuit 1120 selects the time data registers 1111, 1112, 1113, 1114, and the master latch selection circuit 1150 selects the master latches 1141, 1142, 11
Select 43 and 1144 respectively.

Next, the operation of outputting a series of output patterns will be described with reference to FIG. In FIG. 3, a shows the change over time of the count data when the FRC1000 is an up counter, b shows the external signal input from the input terminal 40, and c shows the latch data of the FRC register 1180. , D represents output data of the pointer circuit 1170, e represents time data supplied from the time data selection circuit 1120 to the adder 1190, and f represents addition result data supplied from the adder 1190 to the comparison circuit 1130. , G represents output data supplied from the master latch selection circuit 1150 to the slave latch circuit 1160, h represents data output from the slave latch circuit 1160, and i represents a match signal output from the comparison circuit 1130. .

FRC1000 is up counter and time data register 1
It is assumed that 111 to 1114 store time data TA, TB, TC, TD, respectively, and master latches 1141 to 1144 store output data DA, DB, DC, DD, respectively.

In the initial state, since the count data of the pointer circuit 1170 is "0", the time data selecting means 1120 selects the time data register 1111 and sends the digital data TA stored in this register to the adder 1190 to be the master. The latch selection circuit 1150 selects the master latch 1141 and sends the digital data DA stored in this latch to the slave latch circuit 1160.

When the leading edge of the external signal input to the input terminal 40 arrives at time t1, the FRC register 1180 latches the count data N1 of the FRC1000 at that time, and the comparison operation of the comparison circuit 1130 is started. Adder 1190 is FRC
Latch data N1 of register 1180 and time data register 11
Addition with 11 time data TA and the addition result data
N2 (= N1 + TA) is supplied to the comparison circuit 1130. Comparison circuit 11
30 is the digital data N2 supplied from the adder 1190
And the count data of the FRC1000 shown in FIG. 1 sent via the local bus 1400 are compared, and the time t2 in FIG. 3 is compared.
When the count data of FRC1000 becomes equal to N2,
The match signal shown in FIG. I is sent to the slave latch circuit 1160 and the pointer circuit 1170. Slave latch circuit 1160
As shown in FIG. 3h, the master latch 11 is generated at the leading edge of the match signal sent from the comparison circuit 1130.
The digital data DA stored in 41 is latched, and as shown in FIG. 3d, the pointer circuit 1170 counts up the count data from "0" to "1" by the coincidence signal. When the count data of the pointer becomes "1", the time data TB is supplied from the time data selection circuit 1120 to the adder 1190 and the slave latch circuit 1160 is supplied to the master latch selection circuit as shown in FIGS. 1150
Output data DB is supplied from.

After that, similarly, count data of FRC1000 and adder 119
The data transmitted by 0 is compared with each other. At times t3, t4, and t5, since the count data of the FRC 1000 and the addition result data of the adder 1190 match, a match signal is sent from the comparison circuit 1130. Then, each time the match signal is sent from the comparison circuit 1130, the slave latch circuit 1160 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 1170 performs the counting operation.

At time t5, the pointer circuit 1170 makes a round from the count value of “3” to “0”, and therefore sends an overflow signal to the comparison circuit 1130.

The comparison circuit 1130 stops the comparison operation due to this overflow signal, and does not send the coincidence signal until the leading edge of the external signal input to the input terminal 40 arrives.

When the leading edge of the external signal input to the input terminal 40 arrives at the time t6, the FRC register 1180 latches the count data N6 of the FRC1000 at that time, the comparison operation of the comparison circuit 1130 is started, and then the time t1. The same operation as in the case of ~ t5 is repeated.

Therefore, with reference to the external signal input to the input terminal 40, the FRC1000 stores the counted data in the time data registers 1111-1114, and the master latches 1141-1144 corresponding to the time data registers 1111-1114. By storing arbitrary output data in the slave latch circuit 1160, a signal having a series of output patterns can be output.

In this way, the transfer of data from the master latches 1141 to 1144 to the slave latch circuit 1160 is performed by the comparison circuit 1 that compares the output data of the adder 1190 and the count data of the FRC1000.
By being configured to be automatically performed by the match detection signal of 130, after detecting the leading edge of the external signal that is asynchronously input from the input terminal 40, after a predetermined time, the output port 1100 outputs any When the signal of the signal pattern is transmitted, the time base error can be suppressed to the minimum.

As described above, the microprocessor of the present invention includes a free running counter (FRC1000) that performs a cyclic counting operation based on a specific clock signal, and time data storage means (time data register 1111) that stores at least two types of digital data. 1114), time data selecting means (time data selecting circuit 1120) for selecting any one of the time data storing means, and count data storing means for storing count data of the free running counter in synchronization with an external input signal. (FRC register 1180), an adder (adder 1190) for adding the data of the count data storage means and the data of the time data storage means, and the count data of the free running counter and the addition data of the adder are compared. , A comparison means (comparison circuit 1130) that outputs a coincidence signal when they match A pointer (pointer circuit 1170) that performs a cyclic count operation based on a match signal output from the master latch unit (master latch unit that stores the same number of digital data as the time data storage unit).
1141 to 1144), a master latch selection unit (master latch selection circuit 1150) for selecting one of the master latch units, and a slave latch for fetching the data of the master latch unit based on the coincidence signal output from the comparison unit. And an output port (output port 1100) composed of a unit (slave latch circuit 1160).

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily obtain a series of signal pattern outputs with less time base error.

Although the output timing is determined with reference to the leading edge of the external signal in the embodiment, the same effect can be obtained by using the trailing edge of the external signal or both edges as the reference.

Further, in the embodiment, the case where there are four types of output data output from the output port has been described, but the same operation is performed in any of the cases of 1 to 4 types, and further, the time data register and the master latch of the output port are 4 each
Although the configuration is such that two or more lines are provided depending on the complexity of the pattern of the signal output from the output port, the same effect can be obtained.

In the embodiment, the free running counter is the up counter, but in the case of the down counter, the sign of the data in the FRC register is made negative and the
The same effect can be obtained.

Next, FIG. 4 is a block diagram of the output port of the present invention.

In FIG. 4, the FRC4000 is a free-running counter, which performs a cyclic count operation using a signal supplied from the terminal 4020 as a clock, and the count data of the FRC4000 is supplied to the adder 4100 and the comparison circuit 4200. Further, the time data is supplied from the time data register 4300 to the adder 4100. When the external signal is input from the external input terminal 4030, the adder 4100 adds the count data of the FRC4000 and the time data of the time data register 4300,
The addition result data is supplied to the comparison circuit 4200. The comparison circuit 4200 compares the count data of the FRC 4000 with the addition result data of the adder 4100, and if they match, supplies a match signal to the pointer circuit 4400 and the slave latch 4700.
The pointer circuit 4400 performs a cyclic count operation based on the match signal from the comparison circuit 4200, and supplies the count data to the master latch selection circuit 4600. Master latch 4500-45
30 (indicated as master latches A to D in the figure)
Is a register for storing output data output from the output terminals 4010 to 4013. The master latch selection circuit 4600 selects one of the master latches 4500 to 4530 according to the count data of the pointer circuit 4400 and supplies the data of the selected master latch to the slave latch. The slave latch 4700 takes in the output data supplied from the master latch selection circuit 4600 in response to the match signal from the comparison circuit 4200, and outputs it from the output terminals 4010 to 4013.

The operation of the output port configured as above will be described with reference to the block diagram of FIG. 4 and the timing chart of FIG.

In FIG. 5, “a” shows a time change of the count data when the FRC4000 is an up counter, “b” shows an external signal input from the input terminal 4030, and “c” shows an adder 4100.
Shows the addition result data supplied to the comparison circuit 4200 from
d indicates the output data of the pointer circuit 4400, e indicates the output data supplied from the master latch selection circuit 4600 to the slave latch circuit 4700, and f indicates the slave latch circuit 47.
00 indicates data output from 00, and g indicates a coincidence signal output from the comparison circuit 4200.

FRC4000 is an up counter and time data register 4
It is assumed that 300 stores time data T, and master latches 4500 to 4530 store output data DA, DB, DC, and DD, respectively. Further, for the count data “0”, “1”, “2”, and “3” of the pointer circuit 4400, the master latch selection circuit 4600 has the master latches 4500, 4510,
Select 4520 and 4530 respectively.

Since the count data of the pointer circuit 4400 is “0” in the initial state, the master latch selection circuit 4600 selects the master latch 4500 and sends the digital data DA stored in this latch to the slave latch circuit 4700. .

When the leading edge of the external signal input to the input terminal 4030 arrives at time t1, the adder 4100 causes the count data N1 of the FRC4000 at that time and the time data register 430
The time data T stored in 0 is added, and the addition result data is supplied to the comparison circuit 4200. And adder
The 4100 continues to supply the addition result data at the time t1 to the comparison circuit 4200 until the leading edge of the external signal input to the input terminal 4030 newly arrives.

The comparator circuit 4200 compares the digital data N1 + T supplied from the adder 4100 with the count data of the FRC4000, and the count data of the FRC4000 becomes N1 + at time t2 in FIG.
When it becomes equal to T, the coincidence signal shown in FIG. 5g is sent to the slave latch circuit 4700 and the pointer circuit 4400.

The slave latch circuit 4700, as shown in FIG.
At the leading edge of the match signal sent from the comparison circuit 4200, the digital data DA stored in the master latch 4500 is latched, and as shown in FIG. 5d, the pointer circuit 4400 sets the count data to "0" by the match signal. From "" to "1".

After that, similarly to the addition result data from the adder updated at times t3, t5, and t7, FR is added at times t4, t6, and t8, respectively.
Since the count data of C4000 match, as shown in FIG. 5g, a match signal is sent from the comparison circuit 4200. Then, each time the match signal is sent from the comparison circuit 4200, the slave latch circuit 4700 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 4400 performs the counting operation.

Therefore, by storing the time data in the time data register 4300 in advance and storing any output data in the master latches 1141 to 1144, a series of output patterns can be set based on the external signal input to the input terminal 4030. The signal that the slave latch circuit 4700 has can be output.

As described above, the output port of the present invention is a free running counter (FRC4000) that performs a cyclic count operation based on a specific clock signal, and an adder that adds the count data of the free running counter and time data prepared in advance. Unit (adder 4100) compares the count data of the free-running counter with the output data of the adder, and outputs a match signal when they match, a match circuit (comparison circuit 4200) and a match output from the compare unit. A pointer (pointer circuit that performs a cyclic count operation based on a signal
4400) and a master latch unit (master latches 4500 to 453) that stores at least two types of digital data.
0), master latch selection means (master latch selection circuit 4600) for selecting any one of the master latch portions according to the content of the pointer, and data of the master latch portion based on the coincidence signal output from the comparison means. It is composed of a slave latch unit (slave latch circuit 4700) which is taken in by the device.

Although the number of output terminals of the output port is four in the embodiment, it can be realized in the same manner even if the number of output terminals is increased by increasing or decreasing the data length of the master latch and the slave latch.

EFFECTS OF THE INVENTION As described above, the present invention stores time timing data for sending an output signal from an output port in a time data register based on an external input signal, and outputs data at the time timing stored in the time data register. By storing in the master latch, when the edge of the input signal applied to the external signal input terminal arrives, the output timing of the signal is added from the count data of the free running counter at that time and the time data of the time data register. , When the output timing of the addition result and the count data of the free-running counter match, a signal is automatically output, so a series of signal patterns with less time base error can be output from the output port. large.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram showing a concrete configuration example of an output port unit in the embodiment, and FIG. 3 is a main part of FIG. 4 is a timing chart, FIG. 4 is a block diagram of the output port in one embodiment of the present invention, and FIG. 5 is a timing chart of the main part of FIG. 100 ... Timing generator, 200 ... Program counter, 300 ... PLA, 400 ... ALU, 500 ... ROM, 700 ... RAM, 900 ... I
CR, 1000, 4000 ... FRC, 1100 ... Output port, 1111-1114,4
300 ... Time data register, 1130, 4200 ... Comparison circuit, 1141
~ 1144, 4500 ~ 4530 ... Master latch, 1160, 4700 ... Slave latch, 1170, 4400 ... Pointer circuit, 1180 ... FRC register, 1190, 4100 ... Adder.

Claims (3)

[Claims] 1. A free running counter for performing a cyclic counting operation based on a specific clock signal, time data storage means for storing at least two kinds of digital data, and one of the time data storage means is selected. Time data selection means, count data storage means for storing count data of the free running counter in synchronization with an external input signal, and addition for performing addition of the data of the count data storage means and the data of the time data storage means And a comparing unit that compares the count data of the free running counter with the addition data of the adder and outputs a match signal when they match, and a cyclic counting operation based on the match signal output from the comparing unit. And the same number of digital devices as the time data storage means. Master latch section for storing data, master latch selection means for selecting any one of the master latch sections, and slave latch for taking in data of the master latch section based on a coincidence signal output from the comparison means. A microprocessor with an output port consisting of 2. The microprocessor according to claim 1, wherein the time data selecting means and the master latch selecting means change the selection based on the count data of the pointer. 3. A free running counter for performing a cyclic counting operation based on a specific clock signal, an adder for adding the count data of the free running counter and time data prepared in advance, and a free running counter for the free running counter. At least two types: a comparison unit that compares the count data with the output data of the adder and outputs a match signal when they match, a pointer that performs a cyclic count operation based on the match signal output from the comparison unit; A master latch unit that stores the digital data described above, a master latch selection unit that selects one of the master latch units according to the contents of the pointer, and data of the master latch unit is output from the comparison unit. Equipped with a slave latch unit that captures data based on a match signal Output port.