JPH0690730B2 - Microprocessor and output port - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a microprocessor and an output port, and provides a microprocessor and an output port in which a signal output through the output port has less time base error. .

2. Description of the Related Art In recent years, Neumann microprocessors have been widely used in all fields, and their configurations include a program storage means for storing a program consisting of a series of instructions to be sequentially executed and a data storage for reading / writing digital data. Means, an arithmetic means for executing arithmetic operation of digital data, a data bus connecting the input / output terminal of the data storage means and the input / output terminal of the arithmetic means, and the above-mentioned means based on an instruction sent from the program storage means. Control means for controlling the operations of the data storage means and the arithmetic means, a timing generator for generating an instruction execution timing signal, and a specific instruction stored in the program storage means based on the output of the timing generator. Characterized by having instruction selection means To be In addition, the typical structure is Japanese Patent Publication Sho 58-33.
No. 584 (hereinafter referred to as Document 1).

SUMMARY OF THE INVENTION However, the Neumann method microprocessor as shown in Document 1 executes data processing in a predetermined order, and thus asynchronously inputs data as the program becomes huge. The cycle of fetching external data and the processing of data based on it becomes longer, and as a result, the variation in the time from the occurrence of an event to the output signal from the microprocessor,
That is, there is a problem that the time base error becomes considerably large. Conventionally, a means called an interrupt has been used to deal with such a problem. However, even if an interrupt request is made, it cannot move to the interrupt process unless the instruction being executed at that time is processed. There is a problem that a timebase error occurs in the time itself from when an interrupt is accepted until the interrupt service routine is actually started.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a microprocessor and an output port capable of outputting a series of signal patterns with a small time base error.

Means for Solving the Problems To achieve this object, a microprocessor according to the present invention comprises a free running counter for performing a cyclic counting operation, a data storage means for storing two or more types of digital data, and a data storage means for storing the data. First and second data selecting means for selecting mutually different data, data switching means for outputting one of the data selected by the first and second data selecting means, and the external input A count data storage means for storing count data of the free running counter in synchronization with a signal, an adder for adding data of the count data storage means and output data of the data switching means, and a free running counter of the free running counter. Compare the count data and the addition data of the adder, and if they match, match Comparing means for outputting a signal, a pointer for performing a cyclic counting operation based on the coincidence signal output from the comparing means, a master latch section for storing the same number of digital data as the data storing means, and a master latch section First and second master latch selecting means for selecting mutually different master latches, and the first and second master latch selecting means.
Master latch selecting means for outputting data of either one of the master latches selected by the master latch selecting means, and a slave latch portion for fetching output data of the master latch switching means based on a coincidence signal output from the comparing means. It has an output port consisting of.

Further, the output port of the present invention includes a free-running counter for performing a cyclic counting operation, time data storage means for changing output data according to an external input signal, count data of the free-running counter, and output of the time data storage means. An adder that performs addition with data, a comparison unit that compares the count data of the free running counter and the output data of the adder, and outputs a match signal when they match, and a match output from the comparison unit A pointer that performs a cyclic count operation based on a signal, a master latch unit that stores at least two or more types of digital data, and a master latch selection that selects one of the master latch units according to the contents of the pointer. Means and data of the master latch section is output from the comparing means. Taking based on No. match signal and a slave latch portion.

Effect of the Invention With the above-described configuration, the present invention can provide a microprocessor and an output port in which a signal output via the output port has less time base error.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the microprocessor of the present invention.

In FIG. 1, TMGR100 is a timing generator that generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and its output signal is supplied to the PC200, ICR900 and FRC1000. The PLA 300 is a programmable logic array, and stores a program including a group of instructions that are sequentially executed. PC200 is a program counter, and selects a specific instruction stored in PLA300 based on the output signal of TMGR100. FRC1000 is a free running counter, TMGR1
The cyclic count operation is performed using the output signal of 00 as a clock signal. The count data of FRC1000 is supplied to ICR900 and output port 1100 via local bus 1400. ICR9
00 is an input capture register circuit, and when the edge of the input signal applied to the external signal input terminals 20 to 27 arrives, the count data of the FRC1000 at that time is ICR.
Stored in a specific register in 900 (FR is written in multiple registers when the edges of multiple input signals arrive at the same time.
The count data of C1000 is stored. ), And has a function of setting an input signal reception flag (not shown). The command transmitted from the PLA 300 is ALU 400, address decoder 600 (shown as address decoder A in the drawing), address decoder 800 (shown as address decoder B in the drawing) via command bus 1300. , ICR900 and output port 1100.
The data bus 1200 is ALU400, ROM500, RAM700, ICR900.
And connected to output port 1100. ALU400 is an arithmetic unit that executes arithmetic and logical operations on digital data. The ROM 500 is a read-only memory that sends digital data stored in advance to the data bus 1200. The RAM 700 is a random access memory that reads and writes digital data via the data bus 1200. The output port 1100 outputs a series of signal patterns that can be changed by a program from the signal output terminals 30 to 37 with reference to the external signal input from the signal input terminal 40. The address decoder 600 selects the address of the ROM 500, and the address decoder 800 selects the address of the RAM 700.

The operation of the microprocessor of the present embodiment configured as described above will be described below with reference to FIGS. 1 to 3.

The TMGR100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and supplies this signal to the PC200, ICR900 and FRC1000. PC200
Selects a specific instruction from the instruction group stored in PLA300 based on the output signal of TMGR100, and PLA300 sends the instruction selected by PC200 to command bus 1300. AL
The U400 executes arithmetic and logical operations of digital data sent via the data bus 1200 according to the command sent from the command bus 1300, and sends the result to the data bus 1200. The address decoder 600 selects a specific address based on an instruction sent via the command bus 1300, and the ROM 500 transfers the digital data stored in the storage means corresponding to the address selected by the address decoder 600 to the data bus 1200. Send to. The address decoder 800 selects a specific address based on the instruction sent via the command bus 1300, and the RAM 700 is sent from the data bus 1200 to the storage means corresponding to the address selected by the address coder 800. It stores the incoming digital data or sends the already stored digital data to the data bus 1200.

Next, the output port 1100 will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing the internal structure of the output port 1100 of FIG. 1, and FIG. 3 is a timing chart of the main part.

The external signal input from the signal input terminal 40 in FIG. 2 is supplied to the comparison circuit 1130, the FRC register 1180, the time data switching circuit 1175, and the master latch switching circuit 1176.

Time data registers 1111 to 1114, 1116 to 1119 (indicated as time data registers A1 to D1 and A2 to D2 in the figure)
Is a register that stores timing data for outputting data from the output port.

The time data selection circuit 1120 (indicated as time data selection circuit 1 in the figure) includes time data registers 1111-1114.
Among them, the time data selection circuit 1125 (shown as the time data selection circuit 2 in the figure) is a time data register.
Select one of the registers from 1116 to 1119,
The timing data stored in the selected register is supplied to the time data switching circuit 1175, respectively. The time data switching circuit 1175 selects one of the timing data supplied from the time data selection circuit 1120 and the time data selection circuit 1125 according to the signal level of the external signal,
Supply to the adder 1190.

When an external signal is input from the input terminal 40, the FRC register 1180 latches the count data of the FRC1000 at that time,
The latch data is supplied to the adder 1190. Adder 1190
Is the FRC register 1180 data and time data selection circuit 1175
The output data is added and the addition result data is supplied to the comparison circuit 1130. The comparison circuit 1130 compares the addition result data supplied from the adder 1190 with the count data supplied from the FRC 1000 of FIG. 1 via the local bus 1400, and if they match, outputs a match signal as a slave latch circuit 11
60 and pointer circuit 1170. Also, the comparison circuit
The 1130 starts the comparison operation when an external signal is supplied from the input terminal 40, and performs the comparison operation until the overflow signal is supplied from the pointer circuit 1170.

The address decoders 1110 and 1115 (indicated as address decoders C1 and C2 in the figure) follow the instructions sent from the command bus 1300 and send them to the time data registers 1111-1114 and 1116-1119 via the data bus 1200. Select an address when storing digital data.

Master latches 1141 to 1144 and 1146 to 1149 (indicated as master latches A1 to D1 and A2 to D2 in the figure) are latches for storing output data.

Master latch selection circuit 1150 (indicated as master latch selection circuit 1 in the figure) includes master latches 1141 ...
A master latch selection circuit 1155 (indicated as master latch selection circuit 2 in the figure) from 1144 selects any one of the master latches 1146 to 1149 and stores it in the selected master latch. The output data that has been output to the master latch switching circuit 1176. The master latch switching circuit 1176 selects one of the output data supplied from the master latch selection circuit 1150 and the master latch selection circuit 1155 according to the signal level of the external signal, and supplies it to the slave latch circuit 1160.
Also, the address decoders 1140 and 1145 (indicated as address decoders D1 and D2 in the figure) are command buses 1300.
An address is selected when digital data is stored in the master latches 1141 to 1144 and 1146 to 1149 via the data bus 1200 according to the instruction sent from the.

The pointer circuit 1170 performs a cyclic count operation based on the match signal of the comparison circuit 1130, and outputs count data to the time data selection circuits 1120 and 1125 and the master latch selection circuit 1150.
Supply to 1155. Further, the pointer circuit 1170 compares the overflow signal when the count operation has completed one cycle.
Supply to 1130. Further, the pointer circuit 1170 initializes the count data by the initialization instruction sent from the command bus 1300.

The operation of the output port 1100 configured as above will be described.

Arbitrary digital data is written in the time data registers 1111-1114 and 1116-1119 by a program. For example, the time data register 11
When time data is written to 11, the address decoder 1110 first selects the time data register 1111 according to the instruction sent via the command bus 1300,
The selected time data register 1111 stores the digital data sent via the data bus 1200. Similarly, time data registers 1112 to 1114 and 1116 to 1119
Arbitrary digital data is written in. Further, the master latches 1141 to 1144 and 1146 to 1149 are similarly programmed with arbitrary digital data by programming.

The time data selection circuits 1120 and 1125 and the master latch selection circuits 1150 and 1155 select respective time data registers or master latches according to the count data supplied from the pointer circuit 1170. That is, the pointer circuit
1170 count data "0", "1", "2", "3"
On the other hand, the time data selection circuit 1120 replaces the time data registers 1111, 1112, 1113, 1114 with the time data selection circuit 1125.
Selects the time data registers 1116,1117,1118,1119,
Similarly, the master latch selection circuit 1150
1141, 1142, 1143, 1144 as master latch selection circuit 1155
Selects master latches 1146, 1147, 1148, 1149, respectively.

Regarding the signal level, when the potential of the signal is low, it is expressed as “0”, and when it is high, it is expressed as “1”. When the signal level of the external signal input from the signal input terminal 40 is “1”, , The time data switching circuit 1175 outputs the output data of the time data selection circuit 1120, the master latch switching circuit 1176 outputs the output data of the master latch selection circuit 1150, and when the signal level of the external signal is “0”, The time data switching circuit 1175 outputs the output data of the time data selection circuit 1125, and the master latch switching circuit 1176 outputs the output data of the master latch selection circuit 1155.

Next, the operation of outputting a series of output patterns will be described with reference to FIG. In FIG. 3, a shows the change over time of the count data when the FRC1000 is an up counter, b shows the external signal input from the input terminal 40, and c shows the latch data of the FRC register 1180. ,
d indicates output data of the pointer circuit 1170, e indicates time data supplied from the time data switching circuit 1175 to the adder 1190, f indicates addition result data supplied from the adder 1190 to the comparison circuit 1130, g is a master latch switching circuit
1176 shows the output data supplied to the slave latch circuit 1160, h shows the data outputted from the slave latch circuit 1160, and i shows the coincidence signal outputted from the comparison circuit 1130.

FRC1000 is up counter and time data register 1
111 to 1114 and 1116 to 1119 have time data, respectively.
T _A1 , T _B1 , T _C1 , T _D1 and T _A2 , T _B2 , T _C2 , T _D2 are stored, and output data D _A1 , D _B1 , D are stored in master latches 1141 to 1144 and 1143 to 1149, respectively. _C1 , D _D1 and D _A2 , D _B2 , D _C2 , D
_{Suppose D2} is stored. In the initial state at time t0, the count data of the pointer circuit 1170 is "0".

When the count data of the pointer circuit 1170 is "0", the time data selection circuits 1120 and 1125 select the time data registers 1111 and 1116, respectively, and the time data T _A1 and T _A2 stored in the respective time data registers. Is supplied to the time data switching circuit 1175. Similarly, the master latch selection circuits 1150 and 1155 have master latches 1141 and 1146, respectively.
And supplies the output data D _A1 and D _A2 stored in the respective master latches to the master latch switching circuit 1176.

When the leading edge of the external signal input to the input terminal 40 arrives at time t1, the FRC register 1180 latches the count data N1 of the FRC1000 at that time, and supplies the count data N1 to the adder 1190. Further, since the signal level of the external signal becomes "1", the time data switching circuit 1175 supplies the time data T _A1 supplied from the time data register 1111 to the adder 1190, and the master latch switching circuit 1176 outputs the master latch. The output data D _A1 supplied from 1141 is supplied to the slave latch circuit 1160.

The adder 1190 adds the latch data N1 of the FRC register 1180 and the time data T _A1 supplied from the time data switching circuit 1175, and supplies the addition result data N2 (= N1 + T _A1 ) to the comparison circuit 1130. The comparator circuit 1130 starts the comparison of the digital data N2 supplied from the adder 1190 and the count data of the FRC1000 shown in FIG. 1 sent via the local bus 1400 with the arrival of the leading edge of the external signal. Then, when the count data of the FRC1000 becomes equal to N2 at the time t2 in FIG. 3, the match signal shown in FIG.
Send to 70. The slave latch circuit 1160 latches the output data D _A1 supplied from the master latch switching circuit 1176 at the leading edge of the coincidence signal sent from the comparison circuit 1130 as shown in FIG.
As shown in, the pointer circuit 1170 counts up the count data from "0" to "1" by the coincidence signal. When the count data of the pointer becomes "1", the time data T _B1 is supplied from the time data switching circuit 1175 to the adder 1190 and the master latch is supplied to the slave latch circuit 1160 as shown in FIGS. The output data D _B1 is supplied from the switching circuit 1176.

After that, similarly, count data of FRC1000 and adder 119
The data transmitted by 0 is compared with each other. At times t3, t4, and t5, since the count data of the FRC 1000 and the addition result data of the adder 1190 match, a match signal is sent from the comparison circuit 1130. Then, each time a match signal is sent from the comparison circuit 1130, the slave latch circuit 1160 latches the digital data stored in the master latch selected by the master latch selection circuit 1150, and the pointer circuit 1170 performs a counting operation.

At time t5, the pointer circuit 1170 makes a round from the count value of “3” to “0”, and therefore sends an overflow signal to the comparison circuit 1130. The comparison circuit 1130 stops the comparison operation due to this overflow signal, and does not send the coincidence signal until the trailing edge of the external signal input to the input terminal 40 arrives.

When the trailing edge of the external signal input to the input terminal 40 arrives at time t6, the FRC register 1180 latches the count data N6 of the FRC1000 at that time, and supplies the counter data N6 to the adder 1190. Further, since the signal level of the external signal becomes “0”, the time data switching circuit 1175 supplies the time data T _A2 supplied from the time data register 1116 to the adder 1190, and the master latch switching circuit 1176 outputs the master latch. The output data D _A2 supplied from the 1146 is supplied to the slave latch circuit 1160.

The adder 1190 adds the latch data N6 of the FRC register 1180 and the time data T _A2 supplied from the time data switching circuit 1175, and supplies the addition result data N7 (= N6 + T _A2 ) to the comparison circuit 1130. When the trailing edge of the external signal arrives, the comparator circuit 1130 starts comparing the digital data N7 supplied from the adder 1190 with the count data of the FRC1000 sent via the local bus 1400, and FIG. The count data of FRC1000 is N7 at time t7
When it is equal to, the coincidence signal shown in FIG. 3i is sent to the slave latch circuit 1160 and the pointer circuit 1170.
The slave latch circuit 1160, as shown in FIG.
At the leading edge of the match signal sent from the comparison circuit 1130, the output data D _A2 supplied from the master latch switching circuit 1176 is latched, and as shown in FIG. Is incremented from "0" to "1".

After that, the same operation as in the case of time t1 to t5 is repeated.

Therefore, with reference to the external signal input to the input terminal 40, the data after any counting of the FRC1000 is stored in the time data registers 1111-1114 and 1116-1119,
By storing arbitrary output data in the master latches 1141 to 1144, 1146 to 1149 corresponding to the time data registers 1111-1114, 1116 to 1119, it is possible to output a signal having a series of output patterns from the slave latch circuit 1160. it can.

In this way, the data transfer from the master latches 1141 to 1144 and 1146 to 1149 to the slave latch circuit 1160 is performed by the adder 11
The leading edge or trailing edge of the external signal that is asynchronously input from the input terminal 40 is configured by being configured to be automatically performed by the match detection signal of the comparison circuit 1130 that compares the output data of 90 and the count data of FRC1000. When a signal having an arbitrary signal pattern is transmitted from the output port 1100 after a predetermined time from the detection of the time base error, the time base error can be minimized. As described above, the microprocessor of the present invention includes the free running counter (FRC1000) that performs the cyclic counting operation and the data storage means (time data registers 1111 to 1111) that stores two or more types of digital data.
14, 1116 to 1119), first and second data selection means (time data selection circuits 1120, 1125) for selecting mutually different data from the data storage means, and first and second
Data switching means (time data switching circuit 11 for outputting either one of the data selected by the data selecting means).
75), a count data storage means (FRC register 1180) for storing the count data of the free running counter in synchronization with the external input signal, and an addition for adding the data of the count data storage means and the output data of the data switching means. Means (comparator circuit 1130) for comparing the count data of the free-running counter and the addition data of the adder with the adder (adder 1190) and outputting a match signal when they match.
And a pointer (pointer circuit 1170) that performs a cyclic counting operation based on the coincidence signal output from the comparison unit, and a master latch unit (master latches 1141 to 1144, 1146 to which stores the same number of digital data as the time data storage unit). 1
149) and first and second master latch selection means (master latch selection circuits 1150 and 115) for selecting different master latches from the master latch section.
5) and master latch switching means (master latch switching circuit 11) for outputting data of either one of the master latches selected by the first and second master latch selecting means.
76) and a slave latch unit (slave latch circuit 1160) which takes in the output data of the master latch switching means based on the coincidence signal outputted from the comparing means, and is provided with an output port (output port 1100).

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily obtain a series of signal pattern outputs with less time base error.

In the embodiment, the case where there are four types of output data output from the output port with reference to each of the leading edge and the trailing edge has been described.
The same operation is performed in any of 1 to 4 cases.
The output port time data register and the master latch each consist of two sets of four sets, but the same effect can be obtained when two or more sets are provided depending on the complexity of the pattern of the signal output from the output port. Is obtained.

In the embodiment, the free running counter is the up counter, but in the case of the down counter, the sign of the data in the FRC register is made negative and the
The same effect can be obtained.

Next, FIG. 4 shows a block diagram of the output port of the present invention.

In FIG. 4, the FRC4000 is a free-running counter, which performs a cyclic count operation using a signal supplied from the terminal 4020 as a clock, and the count data of the FRC4000 is supplied to the adder 4100 and the comparison circuit 4200.

The external signal input from the external input terminal 4030 is an adder 410.
0, time data registers 4300 and 4310 (indicated as time data registers 1 and 2 in the figure). The time data registers 4300 and 4310 are registers that store timing data for outputting data from the output port, and the time data register 430 corresponds to the signal level of the external input signal.
The data in either register 0 or 4310 is added to the adder 4100.
Is supplied to. When an external signal is input from the external input terminal 4030, the adder 4100 adds the count data of the FRC4000 and the time data of the time data register 4300 or 4310, and supplies the addition result data to the comparison circuit 4200. . The comparison circuit 4200 compares the count data of the FRC 4000 with the addition result data of the adder 4100, and if they match, supplies a match signal to the pointer circuit 4400 and the slave latch circuit 4700. The pointer circuit 4400 is the comparison circuit 4200
The cyclic count operation is performed based on the coincidence signal of and the count data is supplied to the master latch selection circuit 4600. Master latch 4500-4530 (in the figure, master latch A-
It is designated as D. ) Is a register for storing output data output from the output terminals 4010 to 4013. The master latch selection circuit 4600 selects one of the master latches 4500 to 4530 according to the count data of the pointer circuit 4400 and supplies the data of the selected master latch to the slave latch circuit 4700. The slave latch circuit 4700 receives the match signal from the comparison circuit 4200, and the master latch selection circuit 46
Output data supplied from 00, and output terminal 4010
Output from ~ 4013.

The operation of the output port configured as above will be described with reference to the block diagram of FIG. 4 and the timing chart of FIG.

In FIG. 5, a shows the time change of the count data when the FRC4000 is an up counter, b shows the external signal input from the input terminal 4030, and c is the addition from the time data registers 4300 and 4310. Indicates the time data supplied to the adder 4100, d indicates the addition result data supplied from the adder 4100 to the comparison circuit 4200, and e indicates the pointer circuit 4400.
Output data of the master latch selection circuit 4600
From the slave latch circuit 4700, g represents data output from the slave latch circuit 4700, and h represents a match signal output from the comparison circuit 4200.

FRC4000 is an up counter and time data register 4
Time data T1 and T2 are stored in 300 and 4310, respectively, and output data D _A , D _B , and master latches 4500 to 4530 are stored.
It is assumed that D _C and D _D are stored respectively.

Regarding the signal level, when the potential of the signal is low, it is expressed as “0”, and when it is high, it is expressed as “1”.
When the signal level of the external signal input from the 4030 is "0", the time data T1 stored in the time data register 4300 is supplied to the adder 4100, and when the signal level of the external signal is "1". The time data T2 stored in the time data register 4310 is supplied to the adder 4100. Also,
Count data “0”, “1” of the pointer circuit 4400,
Master latch selection circuit 4600 for "2" and "3"
Selects master latches 4500, 4510, 4520, 4530 respectively.

In the initial state, the count data of the pointer circuit 4400 is “0”, so the master latch selection circuit 4600 selects the master latch 4500 and sends the digital data D _A stored in this latch to the slave latch circuit 4700. There is.

Since the signal level of the external signal is “0” at time t0,
The adder 4100 stores the time data from the time data register 4300.
T1 is supplied.

When the leading edge of the external signal input to the input terminal 4030 arrives at time t1, the adder 4100 causes the count data N1 of the FRC4000 at that time and the time data register 430
The time data T1 supplied from 0 is added, and the addition result data N1 + T1 is supplied to the comparison circuit 4200. Then, the adder 4100 continues to supply the addition result data at the time t1 to the comparison circuit 4200 until the trailing edge of the external signal input to the input terminal 4030 arrives. Further, since the signal level of the external signal becomes "1", the time data T2 is supplied from the time data register 4310 to the adder 4100.

The comparator circuit 4200 compares the digital data N1 + T1 supplied from the adder 4100 with the count data of the FRC4000, and the count data of the FRC4000 is N1 + T at time t2 in FIG.
When it becomes equal to 1, the coincidence signal shown in FIG. 5h is sent to the slave latch circuit 4700 and the pointer circuit 4400.
The slave latch circuit 4700, as shown in FIG.
The digital data D _A stored in the master latch 4500 is latched at the leading edge of the coincidence signal sent from the comparison circuit 4200, and as shown in FIG. Count up from "0" to "1". Pointer circuit
By changing the count data of 4400 to "1", the master latch selection circuit 4600 becomes the master latch 4510.
Is selected, and the digital data D _B stored in this latch is sent to the slave latch circuit 4700.

When the trailing edge of the external signal input to the input terminal 4030 arrives at time t3, the adder 4100 causes the count data N2 of the FRC4000 at that time and the time data register 431.
The time data T2 supplied from 0 is added, and the addition result data N2 + T2 is supplied to the comparison circuit 4200. Then, the adder 4100 continues to supply the addition result data at the time t3 to the comparison circuit 4200 until the leading edge of the external signal input to the input terminal 4030 arrives. Further, since the signal level of the external signal has become "0", the time data T1 is supplied from the time data register 4300 to the adder 4100.

The comparison circuit 4200 compares the digital data N1 + T2 supplied from the adder 4100 with the count data of the FRC4000, and the count data of the FRC4000 is N2 + T at time t4 in FIG.
When it becomes equal to 2, the coincidence signal is sent to the slave latch circuit 4700 and the pointer circuit 4400. Slave latch circuit
The 4700 latches the digital data D _B stored in the master latch 4500 at the leading edge of the match signal sent from the comparison circuit 4200, and the pointer circuit 4400 changes the count data from “1” to “2” by the match signal. Count up.

After that, similarly to the addition result data from the adder updated at times t5, t7, and t9, F at times t6, t8, and t10, respectively.
Since the count data of RC4000 match, as shown in FIG. 5h, a match signal is sent from the comparison circuit 4200. Then, each time a match signal is sent from the comparison circuit 4200, the slave latch circuit 4700 becomes a master latch selection circuit.
The digital data stored in the master latches 4500 to 4530 selected by 4600 are latched, and the pointer circuit 4400 performs counting operation.

Therefore, the time data register 4300, 4310
By storing the time data in the master latches 1141 to 1144 and storing any output data in the master latches 1141 to 1144, a signal having a series of output patterns is generated based on the external signal input to the input terminal 4030. Can be output from.

As described above, the output port of the present invention includes a free running counter (FRC4000) that performs a cyclic counting operation, a time data storage unit (time data register 4300, 4310) that changes output data according to an external input signal, and a free running. An adder (adder 4100) that adds the count data of the counter and the output data of the time data storage means is compared with the count data of the free-running counter and the output data of the adder. A comparing means (comparing circuit 4200) for outputting, a pointer (pointer circuit 4400) for performing a cyclic counting operation based on the coincidence signal output from the comparing means, and a master latch section (master) for storing at least two kinds of digital data. Latch 4500 to 4530) and select one of the master latch parts according to the contents of the pointer. That the master latch selection means (master latch selection circuit 4600), the slave latch unit for taking on the basis of a match signal that is output data of the master latch portion from the comparison means (the slave latch circuit
4700) and.

Although the number of output terminals of the output port is four in the embodiment, it can be realized in the same manner even if the number of output terminals is increased or decreased by increasing or decreasing the data length of the master latch and the slave latch.

EFFECTS OF THE INVENTION As described above, the present invention stores time timing data for sending an output signal from an output port in a time data register based on an external input signal, and outputs data at the time timing stored in the time data register. By storing in the master latch, when the edge of the input signal applied to the external signal input terminal arrives, the output timing of the signal is added from the count data of the free running counter at that time and the time data of the time data register. , When the output timing of the addition result and the count data of the free-running counter match, a signal is automatically output, so a series of signal patterns with less time base error can be output from the output port. large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor in an embodiment of the present invention, FIG. 2 is a block diagram showing a concrete configuration example of an output port section in the embodiment, and FIG. 3 is a block diagram of FIG. 4 is a timing chart of the main part, FIG. 4 is a block diagram showing the configuration of the output port in one embodiment of the present invention, and FIG. 5 is a timing chart of the main part of FIG. 100 ... Timing generator, 200 ... Program counter, 300 ... PLA, 400 ... ALU, 500 ... ROM, 700 ... RAM, 900 ... I
CR, 1000,4000 ... FRC, 1100 ... Output port, 1111-1114,1
116 ~ 1119,4300,4310 ... Time data register, 1130,4200
… Comparison circuit, 1141 to 1144,1146 to 1149,4500 to 4530… Master latch, 1160,4700… Slave latch, 1170,4400…
Pointer circuit, 1180 ... FRC register, 1190,4100 ... Adder.

Claims (4)

[Claims] 1. A free running counter for performing a cyclic counting operation, a data storage means for storing two or more kinds of digital data, and first and second data selection for selecting mutually different data from the data storage means. Means, a data switching means for outputting one of the data selected by the first and second data selecting means, and a count for storing the count data of the free running counter in synchronization with the external input signal. The data storage means, an adder that adds the data of the count data storage means and the output data of the data switching means, and the count data of the free running counter and the addition data of the adder are compared and found to match. In the case of comparing means for outputting a coincidence signal, the coincidence signal output from the comparing means A pointer that performs a cyclic counting operation based on the above, a master latch unit that stores the same number of digital data as the data storage unit, and first and second master latches that select different master latches from the master latch unit. Selecting means, master latch switching means for outputting data of one of the master latches selected by the first and second master latch selecting means, and output data of the master latch switching means is output from the comparing means. A microprocessor having an output port composed of a slave latch unit for capturing on the basis of a match signal. 2. The microprocessor according to claim 1, wherein the data selection means and the master latch selection means change the selection based on an output signal of the count data of the pointer. 3. The microprocessor according to claim 1, wherein the data switching means and the master latch switching means switch the output data based on the signal level of the external input signal. 4. A free-running counter for performing a cyclic counting operation, time data storage means for changing output data according to an external input signal, and count data of the free-running counter and output data of the time data storage means. Comparing the count data of the free running counter with the output data of the adder, and outputting a match signal when they match, based on the match signal output from the comparing unit. A pointer for performing a cyclic counting operation; a master latch unit for storing at least two kinds of digital data; and a master latch selecting unit for selecting one of the master latch units according to the content of the pointer, The data in the master latch section is based on the coincidence signal output from the comparing means. An output port with a slave latch unit that captures the data.