JPH0690733B2 - Microcomputer - Google Patents

Description

The present invention relates to a microcomputer provided with two modes: operation using an accumulator, transfer mode and operation using a memory, and transfer mode.

(B) Conventional Technology Microcomputers are classified into accumulator system, general-purpose register system, and memory system depending on the register configuration. The accumulator system has the advantage that the instruction format is simple, and most of the 4- to 8-bit microcomputers belong to this. The general-purpose register system is a system that does not have an accumulator but has general-purpose registers for calculation, transfer, and address calculation, and performs data processing by the 2-address system.
Due to its high degree of freedom, it is often used in 16-bit microcomputers. In the memory system, all registers are mapped on the memory, and the calculation is performed between the memories. Therefore, in order to utilize the above-mentioned advantages of each method, in recent years, a microcomputer having both an accumulator-type instruction set and a memory-type instruction set has been provided.

A conventional microcomputer will be described with reference to FIG.

In the figure, (11) is an instruction decoder, (12) is a mode switching flag, (13) is a data switching circuit, (14) is an accumulator, and (15) is an arithmetic logic unit (hereinafter referred to as ALU).
, (16) and (17) are first and second memories, respectively, and (18) is an internal bus.

When performing a memory operation and transfer (memory) in the conventional microcomputer configured as described above, a mode set instruction described in a main memory circuit (not shown) is executed prior to the execution of the operation and transfer instruction. , SF _M is executed. Thus, the instruction decoder (11) outputs the memory mode flag F _M, sets the mode change flag (12). The set output of the mode switching flag (12) connects the b contact and the c contact of the data switching circuit (13), and the internal bus (18)
-B contact of data switching circuit (13) -C contact-ALU (15)
To form a bus consisting of, and enable operation and transfer without using the accumulator (14).

On the other hand, when performing an operation that uses an accumulator and transfer (accumulator mode), the operation,
Prior to the execution of the transfer instruction, the mode reset instruction RF _M described in the main memory circuit (not shown) is executed. Thus, the instruction decoder (11) outputs an accumulator mode flag F _A, and resets the mode change flag (12). The reset output of the mode switching flag (12) connects the a contact and the c contact of the data switching circuit (13) to the internal bus (1
8) -The accumulator (14) -a contact point-c contact point-ALU (15) path of the data switching circuit (13) is formed, and calculation and transfer using the accumulator (14) are performed.

In the microcomputer having the above-mentioned configuration, it is not determined whether it is in the accumulator mode or the memory mode except at the time of starting, so that it is necessary to pay close attention when creating software. In addition, large-scale software has a drawback in that the load on the software is heavy, such as the need to initialize the mode switching flag for each routine. Further, from the viewpoint of hardware, two instructions, that is, a flag reset instruction and a flag set instruction for changing the mode are required, so that the instruction decoder (11) has a complicated structure and this flag is saved at the time of interrupt processing. It has the drawbacks that it must be.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above points of the conventional microcomputer, and an object thereof is to provide a microcomputer which does not require execution of a flag reset instruction. It is to provide a microcomputer with simple hardware and light software load.

(D) Means for Solving the Problems The above problems are based on the means for decoding the mode setting instruction, the means for delaying the output of the means until the predetermined timing of the next instruction cycle, and the output of the delay means. This is solved by a microcomputer having a means for selectively outputting ram or register data and accumulator data to an input terminal of the ALU on the accumulator side.

(E) Operation The above-described configuration operates so that the execution of the flag reset instruction is not necessary because the memory mode is automatically released at the end of the instruction cycle next to the setting of the memory mode,
Therefore, the structure of the instruction decoder is simplified and the load on the software is reduced.

(F) Embodiment An embodiment of the present invention will be described with reference to FIG.

In the figure, reference numeral (1) is an instruction decoder and (2) is an RS.
A delay circuit composed of a flip-flop or a D flip-flop, which holds the input state during the next instruction cycle, (3) is a word-unit data switching circuit, (4) is an accumulator, (5) is an ALU, and (6) is And (7) are general-purpose registers or registers set to rams, or rams (in the following description, unified into memory), (8) is an internal bus, and the data switching circuit (3) has no control signal. In the state, the terminals a and c are closed, and the internal bus (8) -accumulator (4) -ALU (5) bus is formed, so that the operation operation (accumulator mode) using the accumulator is guaranteed. .

An example of an arithmetic instruction that can be executed by this embodiment is (1) first operand ← first operand + second operand + CF (2) second operand ← first operand + second operand (3) accumulator ← accumulator + second It has two operands. The operation of the embodiment will be described below by taking the second arithmetic operation as an example.

When the mode setting instruction SF _M is decoded by the instruction decoder (1), the instruction decoder (1) outputs a micro instruction F _M designating an operation between memories (memory mode) to the delay circuit (2). This microinstruction is simultaneously output to an interrupt prohibiting means (not shown), and the interrupt is held pending until the execution of the subsequent arithmetic instruction is completed. Further, the microinstruction F _M is transferred from the instruction decoder (1) to the accumulator (4) at the time of execution of the subsequent arithmetic instruction.
It also serves to change another microinstruction output for controlling the input gate (not shown) into the control signal of the input gate of the first operand.

This will be described in more detail with reference to the timing chart of FIG.

The microcomputer fetches an instruction from the main memory circuit and repeats instruction cycles for executing it. In a real microcomputer, both the fetch cycle and the instruction execution cycle are composed of more complicated sequences. However, if simplified, each cycle has two phases of a control pulse φ ₁ for Fitch and a control pulse φ ₂ for execution. It can be explained that two-phase operation is performed based on the pulse.

In FIG. 2 (A), when the mode setting command SF _M at timing t ₁ is decoded by the instruction decoder (1), microinstruction instruction decoder at a timing t ₂ (1) designates the memory mode F _M Is output. Enter this microinstruction F _M to the set terminal, the control pulse phi ₂ for the instruction execution
The RS flip-flop for inputting to the reset terminal is set at the falling edge of the microinstruction F _M and reset at the rising edge of the control pulse φ ₁ for the next instruction cycle, that is, the fetch / execution period t ₃ , t _{4 of the} arithmetic instruction. High level is output only during period. The output of the RS flip-flop controls the contact of the data switching circuit (3) so as to connect the terminals b and c, and the internal bus (8) -ALU (5)
Bus is formed.

As a result, at timing t ₄ , the data of the memory (6) and the memory (7) designated by the first operand and the second operand are sequential, or if the internal bus (8) is a multi-bus, the addition mode is simultaneously set. Input to an ALU (5). The addition result of this ALU (5) is the timing t
1st at the following subdivided timing within ₄
It is output to the memory (6) designated by the operand.

In the subsequent instruction cycle represented by the timings t ₅ and t ₆ , the output of the delay circuit (2) is at low level, so the accumulator (4) ← accumulator +
An operation using the accumulator as the second operand is executed.

FIG. 2B shows an execution control signal φ divided as a reset signal of the RS flip-flop which constitutes the delay circuit (2).
The timing of the embodiment using the rise of φ ₂₂ out of ₂₁ and φ ₂₂ will be described. In the figure, timing t ₁
When the mode setting instruction SF _M is decoded by the instruction decoder (1) at, the instruction decoder 1 outputs the micro instruction F _M designating the memory mode at timings t ₂₁ and t ₂₂ . Enter this microinstruction F _M to the set terminal, RS flip-flop for inputting the control pulse phi ₂₂ for the instruction execution to the reset terminal is set at the falling edge of the microinstruction F _M, at the rising edge of the control pulse phi ₂₂ After reset, the next instruction cycle, that is, fetching an arithmetic instruction
Only the period of time t _3, t ₄₁ run outputs a high level.
The output of the RS flip-flop controls the contact of the data switching circuit (3) so as to connect the terminal b and the terminal c, and the internal bus (8) -ALU (5) bus is formed.

As a result, at the timing t _41, the first operand and the second operand
ALU (5) that is in addition mode at the same time if the data in the memory (6) and memory (7) specified by the operands are sequential, or if the internal bus (8) is a multibus
Entered in. The addition result of this ALU (5) is output to the memory (6) designated by the first operand at timing t ₄₂ . If other microinstructions are modified, it is possible to change so that the instruction of accumulator ← first operand + second operand is executed.

In the subsequent instruction cycle represented by the timings t ₅ and t ₆ , the output of the delay circuit (2) is at the low level, so that the accumulator 4 ← the accumulator + the second
An operation is performed using the accumulator that is the operand.

The example of using the RS flip-flop as the delay circuit (2) has been described above, but it is obvious to those skilled in the art that the D flip-flop can be used similarly.

(G) Effect of the Invention As described above, according to the present invention, since the mode setting instruction can be only the flag setting instruction, the number of instruction sets is reduced, the configuration of the instruction decoder is simplified, and the mode setting is performed. Therefore, it is possible to provide a microcomputer that has a remarkable effect such that the flag reset program is unnecessary and the burden on the software is light, and that the flag saving is not required at the time of interrupt processing.

[Brief description of drawings]

FIG. 1 is a partial block diagram of an embodiment of the present invention, FIGS. 2A and 2B are timing charts of different embodiments, and FIG. 3 is a partial block diagram of a conventional example. (1), (11) ... Instruction decoder, (2) ... Delay circuit,
(3), (13) ... Data switching circuit, (4), (14) ... Accumulator, (5) (15) ... ALU, (6), (7),
(16), (17) ... Memory, (8) (18) ... Internal bus,
(12) ... Mode switching flag, (F _M ) ... memory mode flag, (F _A ) ... accumulator mode flag.

Claims (2)

[Claims] 1. A means for decoding a mode setting instruction, a means for delaying the output of said means until a predetermined timing of the next instruction cycle, and a ram or a register at an accumulator side input terminal of an ALU based on the output of this delay means. And a means for selectively outputting the data of the above and the data of the accumulator. 2. The microcomputer according to claim 1, wherein said delay means is an RS flip-flop which is set at the fall of the output of the means for decoding the mode setting instruction and which is reset by the instruction execution control signal.