JPS6041767B2 - Instruction execution method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction execution method for a microprocessor system.

Generally, in the development of microprocessor systems, improvements in LSI technology have led to greater integration and lower prices of hardware such as memory and CPUs, and the proportion of software costs including maintenance in development costs has increased.

Against this background, it is necessary to simplify the program configuration or provide more advanced functions with limited C-shaped functions and memory capacity. In this case, the configuration of the processor, the instruction execution method, etc. have been determined at the time of process design by the manufacturer, and it is almost impossible for the user to change them. Figure 1 is a block diagram of the conventional method, and Cp
ul is connected to the program memory 2 via an address bus 7, and the signals of the program memory 2 are connected to cpul via an instruction bus 8. 9 is an I/0 port.

Here, the instructions output from memory 2 (
iNST) is directly taken into Cpul through the instruction bus 8, and its instructions are executed.
The present invention aims to eliminate such inconveniences, add additional functions to the instruction execution method on the user side, simplify the program, improve visibility, and reduce the program capacity.

This will be explained with reference to FIG. 2, which is an embodiment of the present invention.

It is assumed here that the specific instruction is an LAi instruction (loads the accumulator with a direct numerical value indicated in the operand section of the instruction), and the format of the instruction is shown in FIG. In FIG. 2, 1 is a cp man, 2 is a program memory, and 3 is an instruction switching unit, which selects whether the contents of the program memory or the contents of the instruction register 6 are to be used as instructions to be executed by the cpul. 4 is the upper 4 bits of instruction bus 8 (instruction code) 12
A latch circuit that holds the set pulse 1 from the CPU.
It is set at 6.

5 is a D-flip-flop that generates an instruction switching signal; 6 is an instruction set register that sets a NOP instruction (no operation); 7 is an address bus; 8
is an instruction bus, 9 is an I/0 port, 10 is an inverter, 11 is an AND gate, 12 is the upper 4 bits of instruction bus 8 (instruction code), 13 is a CPU synchronization clock that outputs one pulse for each CPU instruction, 14 is a specific instruction (LAi instruction) detection signal;
When the LAi instruction code (4) 110) is set in the latch circuit 4, the gates 10 and 11 turn 0N, and the D
- connected to the D input and clear input of flip-flop 5;

Reference numeral 15 denotes an instruction switching signal generated by the CPU clock 13 and the specific instruction detection signal 14, the state of which is shown in the timing chart of FIG.

Reference numeral 16 is a latch set signal for causing the latch circuit 4 to set the upper 4 bits (instruction code) of the instruction bus when a correct instruction is being output to the instruction bus.

The operation of the present invention will be explained below with reference to FIGS. 2 and 3.

In the normal CPU RLIN state, as mentioned above, the instruction (INST) output from memory 2
However, through instruction bus 8, Cp
ul and the instruction is being executed. Here, when executing a program with two consecutive LAi instructions as shown in Figure 3a, first 1NST1 (LAi
/1) is output to the instruction bus 8, and when the LAi instruction code (a) 110) is set in the latch circuit 4 by the latch set signal 16, it is determined that a specific command has been detected, and the signal 14 is becomes. However, at this time, the signal 15 is still in the dark FF state, so the instruction switching unit 3 selects the contents of the program memory, and the IN
STl is executed. Next, INST2 (LAi/4)
is output to the instruction bus, and the latch circuit 4 receives the LAi instruction code (A) by the latch set signal 16.
110) is set, it is determined that a specific command has been detected, and the signal 14 further maintains the locked N state. However, at this time, the switching signal 15 is the CPU clock 131 (FIG. 3b) and is already 0N, so the instruction switching section 3
As a result, the contents of the instruction set register (NOP instruction) are selected and taken into the CPU, and INST2 is not executed. Next, INST3 (ADD) is output to the instruction bus, and when the latch set signal 16 sets the ADD instruction code in the latch circuit 4,
It is determined that a specific command is not detected, signal 14 becomes 0FF, and D
- the flip-flop is cleared and the switching signal 15 is 0
The instruction switching unit 3 selects the contents of the program memory, and INST3 is loaded into the CPU and executed. In addition, due to jump commands etc.
If execution moves directly to 1NST2 from another routine in the program, INST2 (L
Ai/4) instruction code (a) 110) is latch circuit 4
When set to , the specific detection signal 14 becomes 0N, and (
At this time, the switching signal 15 is still in the 0FF state, so the INS
T2 is executed.

) The switching signal 15 becomes 0N at the next CPU clock 132, but when the next instruction code of INST3 (ADD) is set in the latch circuit 4, the specific instruction detection signal 14 becomes 0N.
At the same time, the D-flip-flop 5 is cleared and the switching signal 15 becomes 0FF again, so when the CPU instruction is fetched, the switching unit 3 is switched to the program memory side, so INST3 (ADD) is fetched. and executed. Note that the instruction code is 0 of the latch set signal 16.
It is set for the N period, and the CPU takes in the command at the falling edge of the latch set signal 16. As described above, according to the present invention, it is possible to improve the functionality of the system by determining specific instructions according to each application without being limited to the functionality of an off-the-shelf processor.

Specifically, by specifying the LAj instruction as a specific instruction as described above, the program capacity is halved and the program structure becomes easier to read, as shown in the example of FIG. As a result, the overall program capacity can be reduced, and more processing can be performed with the same capacity. Furthermore, software development, including debugging and specification changes, can be made more efficient.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example of a microprocessor system, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a timing chart, and Fig. 4 shows the instruction format of the LAi instruction. Figure 5 shows the program. 1...CpUl2...Program memory, 3...Instruction switching unit, 4...
(instruction code) latch circuit, 5...D-flip-flop, 6...instruction set register, 7.
... Address bus, 8 ... Instruction bus, 9 ... I/0 boat, 10 ... Inverter, 11 ...... AND gate, 12...
... Upper 4 bits of instruction bus (instruction code), 13...CpU clock, 14...
... Specific instruction detection signal, 15 ... Instruction switching signal, 16 ... Set signal to latch circuit.

Claims (1)

[Claims] 1. In a microprocessor system having an external program memory separate from a CPU, and in which the CPU and memory are connected by an address bus and an instruction bus, a latch circuit that latches an instruction code on an instruction bus, and the instruction code is a specific instruction code; and a circuit that generates a prohibition signal for prohibiting a specific instruction on an instruction bus based on the determination signal and a CPU clock, and when the specific instructions are consecutive, the first specific instruction An instruction execution method that executes only one instruction, and disables subsequent identical instructions.