JPH0691085B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to miniaturization of its metal wiring, and further to prevent deformation of the metal wiring due to stress of a sealing resin. The present invention relates to an improved semiconductor process technology.

[Conventional technology]

In recent years, miniaturization of semiconductor integrated circuits has progressed rapidly. In particular, with the advent of the reduction projection type exposure apparatus, a mask which is 5 times or 10 times as large as an integrated circuit chip has been used, and the miniaturization of the mask and the dimensional accuracy have been remarkably improved.

In resist exposure, EB exposure equipment and X-ray lithography equipment have emerged, and a minimum line width of about 0.5 μm has been realized. However, the width and the interval of the metal wiring in the integrated circuit chip are currently limited to about 2.0 to 2.5 μm. This is because the probability of short-circuiting between metal wirings due to wholly of the metal wirings increases, and the yield decreases significantly. Further, there has been a problem that the metal wiring is deformed by the stress of the resin after resin sealing, and eventually the wiring is short-circuited to cause a failure of the integrated circuit.

For references on the above, see Nikkei Electronics Micro Devices, June 11, 1984, pp.82-9.
2There is "epoxy encapsulant for VLSI that can reduce stress."

FIG. 3 (a) is a plan view of metal wiring of a conventional semiconductor integrated circuit device, and FIG. 3 (b) is a sectional view taken along the line IV-IV of FIG. 3 (a). In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a phosphosilicate oxide film (PSG film), 4 is a passivation film, 5 is a metal wiring, 6 is a short circuit due to the sag of the metal wiring 5, and 7 is a PSG film. It is a defective part.

In this conventional device, when the PSG film 3, the metal wiring 5, etc. are formed, the shape of these is broken by dust and the like, and the metal wiring 5
Many shorts 6 due to sagging.

FIG. 4 shows a plan view and a side cross-sectional view of a conventional device in which metal wires are short-circuited due to resin stress. In the figure, 8 is a short-circuited portion between metal wirings, and 9 is a sealing resin. In this device, the metal wiring 5 is deformed by the stress of the resin 9 in the direction of the arrow Z, and a short circuit occurs at the position 8.

[Problems to be Solved by the Invention]

In such a conventional device, the smaller the spacing between the metal wirings, the higher the probability of short-circuiting the metal wirings due to defects in the PSG film and the field oxide film. As a measure against this, it is necessary to widen the metal wiring interval, but this causes a problem that the chip size becomes large and the cost increases.

Also, as a measure against deformation of resin due to stress, there is a method of coating the surface of the integrated circuit chip with resin such as polyimide before resin sealing, but this method increases the number of processing steps, mass productivity is not good, and cost is increased. There was a drawback that led to.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable semiconductor integrated circuit device capable of preventing deformation of metal wiring.

[Means for Solving the Problems]

A semiconductor integrated circuit device according to the present invention is a semiconductor device in which a field oxide film, a phosphosilicate oxide film, a metal wiring and a passivation film are sequentially laminated on a semiconductor substrate on which a transistor having a gate electrode is formed. A conductor layer in the same layer as the gate electrode of the transistor above the flat surface of the transistor and below the region where the metal wiring is to be formed, and the conductor layer causes a phosphosilicate oxide film to form. Further, the metal wiring is arranged in the concave portion in the step of the unevenness.

[Action]

In the present invention, since the unevenness is formed on the phosphosilicate oxide film so as to fill the concave portion of the metal wiring, the short circuit between the metal wiring due to the dripping of the metal wiring is unlikely to occur, and the metal wiring is It becomes difficult to deform under stress.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 1 (a) is a plan view thereof and FIG. 1 (b) is a first view thereof.
A sectional view taken along the line III-III of FIG. In the figure, 14
Is a polycrystalline silicon layer formed in the same layer as the gate electrode of the transistor and made of the same material as the gate electrode, and is buried below the region where the metal wiring is to be formed. Reference numeral 13 is a silicon oxide film formed of the same material as the silicon gate oxide film of the transistor and covering the polycrystalline silicon layer 14. The same reference numerals as those in FIGS. 3 and 4 denote the same parts.

To facilitate understanding of the present invention, a general N-channel MOS
The process of this embodiment will be described with reference to FIG. 2 showing the process flow.

First, as shown in FIG. 2 (a), the surface of the P-type silicon substrate 1 is thermally oxidized to form a 200-800 Å silicon oxide film 11 on the entire surface.
To form. Next, a silicon nitride film (not shown) is formed on the silicon oxide film 11 by the CVD method, leaving the case corresponding to the activation region formed by the transistor and the region where metal wiring is to be patterned on the upper portion, The silicon nitride film is selectively removed. In this figure, the case corresponding to the region where the metal wiring is patterned is left. Next, as shown in FIG. 2B, boron is ion-implanted using the silicon nitride film as a mask to form a P ⁺ type region 12 for preventing the generation of parasitic MOS on the substrate surface. Further, as shown in FIG. 2 (c), thermal oxidation is performed with the silicon nitride film as a mask to 0.7 to 1.4.
A field oxide film 2 of about μm is formed, and the silicon nitride film and the silicon oxide film are entirely removed. Further, in the case where a transistor of the peripheral circuit section is formed, a silicon oxide film of 300 to 1000 Å is formed in the activation region by thermal oxidation, and a polycrystalline silicon layer is further formed in a vacuum CVD method at 3000
It is formed on the entire surface with a thickness of up to 6000 Å, and is selectively removed leaving a portion to be the gate and wiring of the MOS transistor, and a silicon oxide film is formed on the surface of the polycrystalline silicon layer with a thickness of 300 to 800 Å. Next, as shown in FIG. 2D, the N-type impurity diffusion layer 10 is formed using the field oxide film 2 as a mask. At the same time, the impurity diffusion layers of the source / drain of the transistor are formed. Next, as shown in Fig. 2 (e), CV
The phosphorus silicate oxide film (PSG film) 3 by D method is 5000-11
000Å is formed, and the metal wiring 5 is further patterned and formed. Finally, the passivation film 9 is completely stacked.

In this process step, in this embodiment, there is a polycrystalline silicon layer 14 formed in the same layer as the gate electrode of the transistor below between the metal wirings 5 and a silicon oxide film covering the polycrystalline silicon layer 14, and the PSG film on the upper part thereof. 3 is provided with uneven steps of about 4000 to 7,000 Å, and the metal wiring 5 is patterned in this recess 3a. The thickness of the metal wiring 5 is from 7,000
Since it is 1000Å, it will be sufficiently filled in the recess 3a of the PSG film 3.

By doing so, the contact area between the PSG film 3 and the metal wiring 5 becomes larger than in the conventional case, and the metal wiring 5 is PS
Since it is buried in the G film 3, it is unlikely to be deformed by a lateral stress. Even if there are some defects in the PSG film 3 and the field oxide film 2, a short circuit of the metal wiring 5 occurs unless the depth of the defect is more than 7,000 Å which is far beyond the recess of the recess 3a of the PSG film 3. It gets harder. As described above, a short circuit between the metal wirings is unlikely to occur, and the metal wirings are also less likely to be deformed due to the stress from the lateral direction. Therefore, the short circuit between the metal wirings is caused by the distortion of the resin due to a change in the temperature environment during the resin sealing process and after the product is completed. The deformation of the metal wiring can be significantly reduced.

If the present invention is further applied to roughen the peripheral pattern as in the prior art, or use a highly refined low stress resin,
A short circuit between metal wirings can be prevented without requiring coating of the silicon chip surface with polyimide or the like, and a highly reliable device can be obtained at a lower cost.

Further, in this embodiment, since the polycrystalline silicon layer can be made of the same material as that of the gate of the transistor, there is an advantage that the device can be realized at low cost without adding any semiconductor process to the conventional method. is there.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit of the present invention,
In a semiconductor device in which a field oxide film, a phosphosilicate oxide film, a metal wiring and a passivation film are sequentially stacked on a semiconductor substrate on which a transistor having a gate electrode is formed, a metal on a flat surface of the field oxide film is formed. A conductor layer in the same layer as the gate electrode of the transistor is buried below the region where the wiring is to be formed, and metal wiring is provided in the concave portion of the unevenness of the silicate oxide film formed by the conductor layer. Since it is arranged, short circuit between metal wiring due to sagging of metal wiring is unlikely to occur, and it is also difficult to deform due to stress from the lateral direction, so temperature during resin sealing process and after product completion There is an effect that the deformation of the metal wiring caused by the distortion of the resin due to the change in the environment can be significantly reduced.

[Brief description of drawings]

1 (a) and 1 (b) are pattern plan views of one embodiment of the present invention and a sectional view taken along the line III-III in FIG. 1 (a), and FIGS. 2 (a) to 2 (e) are general. FIG. 3A is a plan view of a conventional metal wiring, and FIG. 3A is a sectional view taken along the line IV-IV of FIG. 3A, and FIGS. FIG. 4B is a plan view of the metal wiring deformed by the resin stress and a sectional view taken along line VV of FIG. 4A. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Phosphorus gate oxide film (PSG film), 4 ... Passivation film, 5 ... Metal wiring, 6,8 ... Short part between metal wiring, 7 ... … Defective portion of phosphoric oxide film, 9 …… Sealing resin, Z …… Resin stress, 10 …… Impurity diffusion layer, 11
...... Silicon nitride film, 12 …… P ⁺ type region, 13 …… Silicon gate oxide film, 14 …… Polycrystalline silicon layer. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A semiconductor device in which a field oxide film, a phosphosilicate oxide film, a metal wiring, and a passivation film are sequentially stacked on a semiconductor substrate on which a transistor having a gate electrode is formed, and a flat surface of the field oxide film. A conductor layer in the same layer as the gate electrode of the transistor is buried below the region where the metal wiring is to be formed, and the step of the unevenness formed in the phosphosilicate oxide film by the conductor layer is buried. A semiconductor integrated circuit device, wherein metal wiring is provided in the concave portion of the. 2. The semiconductor integrated circuit device according to claim 1, wherein the conductor layer is made of polycrystalline silicon. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is sealed with resin.
The semiconductor integrated circuit device according to the paragraph.