JPH0691132B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention uses a new method for electrode wiring inside a semiconductor chip such as an integrated circuit and wiring on a wiring board on which the semiconductor chip is installed. The present invention relates to a semiconductor device to be connected.

<Prior art> In recent years, with the rapid progress of microfabrication technology in integrated circuits, the element density in the chip has dramatically improved, and along with that, the electrical characteristics such as signal transmission speed have improved, and the yield has improved, etc. The effect of was combined and greatly developed. As the device density in the chip increases, the rent (Ren
t) rule of thumb As the number of input / output terminal pads on the chip, G: the number of logic gates on the chip), the number of input / output terminals increases, and a large number of input / output electrode pads are required even with the same chip shape as the conventional one. Came.

Usually, when connecting an electrode pad of an integrated circuit or the like to an external lead, wiring on a wiring board, or the like, a wire bonding method, a tape carrier method, a flip chip method, or another wireless bonding method is used.

<Problems to be Solved by the Invention> However, according to these methods, since the electrode pad and the connection terminal are metallurgically connected, it is necessary to sufficiently consider the reliability and to maintain the strength thereof. In addition, the size of the pad needs to be about 80 to 100 μm square, and the gap between the pads needs to be several tens of μm in consideration of the positional deviation of terminals such as wires.

Therefore, when the element is miniaturized and the element density is improved, the ratio of the electrode pad and the like is increased compared to the area of the chip incorporating the element, the pattern shape becomes inconsistent, and the cost becomes high. was there.

When a large number of chips are installed on a wiring board, etc., the wiring of the board and the pads of the electrodes must be connected in electrode pad units or individual chip units. The work man-hour becomes large,
There is a drawback that the manufacturing cost becomes high.

Also, when multiple chips are installed on the same substrate, use a connecting means in the wire bond method or tape carrier method, or use a jig such as a collet to hold the chips during bonding in the flip chip method. Therefore, it is difficult to install the chips densely, and the wiring between the chips becomes long, which may cause wiring delay.
Further, in these methods, it is necessary to provide the electrode pads in the peripheral portion of the chip, which makes the pattern design complicated.

Furthermore, in the above-mentioned conventional method, wiring of a predetermined pattern is required on the substrate on which the chip is placed in advance, and the substrate cost is high.

<Means for Solving the Problems> In order to solve the above problems, in the semiconductor device of the invention of claim 1, a semiconductor chip is adhered to an insulating substrate and electrically connected to the electrode wiring of the semiconductor chip, and the electrode It is characterized in that a conductor layer extending from the wiring side to the insulating substrate through the side surface of the semiconductor chip is integrally formed.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming at least electrode wiring on a semiconductor substrate, forming a recess having a predetermined depth at a chip boundary portion of the semiconductor substrate, and then forming the recess. A step of forming an insulating film along the inner peripheral surface, a step of adhering a protective base to the semiconductor substrate via a first adhesive layer on the insulating film, and a smoothing process for the back surface of the semiconductor substrate, A step of opening the bottom of the recess to separate the semiconductor substrate into a predetermined semiconductor chip including the electrode wiring; and a step of adhering a back surface of the semiconductor chip and a front surface of an insulating substrate via a second adhesive layer. After removing the first adhesive layer and the protective substrate, the whole surface of the insulating substrate and the semiconductor chip is covered with a conductive thin film, and then electrically connected to the electrode wiring. Side of chip Through, it is characterized by a step of forming integrally a predetermined conductor layers deriving on the insulating substrate.

<Operation> According to the semiconductor device of the first aspect, the semiconductor chip is formed by forming the conductor layer which is connected to the electrode wiring on the semiconductor chip and extends on the insulating substrate through the side surface of the semiconductor chip. The upper electrode wiring can be easily led out as a wiring on the insulating substrate by the conductor layer. Further, since the conductor layer has a high density and can be formed in a small area, the space for wiring is reduced. Also, because no metallurgical connection is required, the electrode pad is no longer needed,
Therefore, it can be manufactured at low cost, and restrictions on the pattern design of the integrated circuit are reduced. Further, since a large number of chips can be arranged at high density on the insulating substrate and processed at the same time, they can be manufactured at low cost and wiring delay is eliminated. Also,
Since the conductor layer derived from the electrode wiring on the semiconductor chip is not a metallurgical connection as in the conventional case, the reliability is high. Further, since the derived conductor layer is used as the substrate wiring of the insulating substrate, it is not necessary to perform the substrate wiring in advance on the insulating substrate on which the chip is placed, so that the cost of the insulating substrate is reduced. Further, the production of the substrate wiring on the insulating substrate is simultaneously performed in the step of forming the conductor layer, so that the manufacturing cost can be reduced.

According to the semiconductor device manufacturing method of the second aspect, the circuit element and the electrode wiring are formed on the semiconductor substrate, for example, as in the case of forming a normal integrated circuit. Then, after forming a recess having a predetermined depth in the chip boundary portion of the semiconductor substrate, an insulating film such as SiO ₂ is formed on the semiconductor substrate. Next, the protective substrate is bonded to the semiconductor substrate on the insulating film via the first adhesive layer. The back surface of the semiconductor substrate is smoothed, the bottom of the recess is opened, and the semiconductor substrate is separated for each predetermined semiconductor chip including electrode wiring. The back surface of the semiconductor chip and the front surface of an insulating substrate made of, for example, glass ceramic or the like are adhered via a second adhesive layer. Then, after removing the first adhesive layer and the protective substrate, the entire surface of the insulating substrate and the semiconductor chip is covered with a conductive thin film, and then electrically connected to the electrode wiring and passed over the side surface of the semiconductor chip. Forming a predetermined conductor layer to be led out on the insulating substrate.

In the above case, the case where a recess is formed on the front surface side of the semiconductor substrate before the back surface of the semiconductor substrate is smoothed and the semiconductor chip is separated by the recess is described. After thinning the semiconductor substrate, the semiconductor substrate and the protective substrate are cut at the same time, the semiconductor chip is bonded to the insulating substrate, the insulating layer is formed on the side surface, and the conductor layer can be derived in the same manner as above. it can.

Furthermore, only the part where the conductor layer is led out from the semiconductor chip is etched into the semiconductor chip, and before and after the smoothing process from the back surface, the side surfaces of the semiconductor chip boundary are separated into vertical shapes. Therefore, when a large number of chips are mounted on the same substrate, even if the end faces of the semiconductor chips are adjacent to each other and are densely arranged, the conductor layer is led out from the semiconductor chip to the insulating substrate through the side surface of the semiconductor chip. You can also

Thus, the electrode wiring on the semiconductor chip can be easily led out as a substrate wiring on the insulating substrate by the conductor layer. In addition, the conductor layer is formed with high density,
The space for wiring can be reduced. Further, the electrode pads used for the connecting means such as the wire bond method and the tape carrier method are not required, and the restrictions on the pattern design of the integrated circuit of the semiconductor chip can be reduced. In addition, since a large number of semiconductor chips can be densely arranged on the insulating substrate and can be processed at the same time, the number of assembling steps can be reduced and the semiconductor chips can be densely installed, which shortens the wiring between the semiconductor chips, Wiring delay can be eliminated. Further, since the conductor layer derived from the electrode wiring on the semiconductor chip is not a metallurgical connection as in the conventional case, stable connection can be achieved and reliability is improved. Further, since it is not necessary to perform board wiring in advance on the insulating substrate, the cost of the insulating substrate is reduced. Further, the production of the substrate wiring on the insulating substrate is simultaneously performed in the step of forming the conductor layer, so that the manufacturing cost can be reduced.

<Examples> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

Example 1 Example 1 of the present invention is described below with reference to FIGS. 1 to 6.

In the first embodiment, a conductor layer is led out on an insulating substrate from the electrode wiring of a semiconductor chip such as an integrated circuit. As shown in FIG. ₂ , SiO ₂ and SiN were formed on the surface of the (100) silicon single crystal 51.
An insulating film 52 of the same type, an electrode wiring 53, an insulating film 54 made of SiO ₂ , SiN, etc. for surface protection and a chip boundary portion 55 are formed. SiO formed on the silicon single crystal 51 by thermal oxidation or a CVD method.
Various circuit elements such as MOSFETs are formed in the same manner as when manufacturing an ordinary integrated circuit using the insulating film 52 made of ₂ , SiN or the like. The electrode wiring 53 is made of Al, Mo, W, WSi, etc., and is formed into a predetermined pattern by a photoetching technique or a selective etching technique after covering the entire surface of the wafer with a metal film by an electron beam evaporation method, a sputtering method, a CVD method or the like. It The insulating film 54
It is made of SiO ₂ , SiN or the like, and is formed by low temperature CVD, plasma CVD or the like. The chip boundary portion 55 is a portion which is separated when the chip is divided, and the insulating film 52 and the insulating film 54 are removed by the photoetching technique and the selective etching technique.

Thereafter, as shown in FIG. 3, a multiple metal film 56 such as a TiAu film or a CrAu film is continuously formed on the entire surface of the wafer by an electron beam evaporation method, a sputtering method or the like, and a chip is formed by a photoetching technique or a selective etching technique. After removing the boundary portion 55, a groove 57 as a recess is formed by anisotropic etching of Si with an alkali etching solution such as KOH or NaOH. At this time, since a (100) silicon wafer is used, the silicon is
1) It is etched along the surface and the chip boundary part 55 on the surface
The depth shape of the groove 57 is naturally controlled by the pattern shape.

Next, after sequentially removing the multiple metal film 56 made of Ti, Au, etc. with aqua regia, concentrated sulfuric acid, etc., as shown in FIG. 4, an insulating film made of SiO ₂ , AiN, etc. by low temperature CVD, plasma CVD, etc. Five
After coating the side surface of the groove 57 with 8 and the like, an insulating film 58 at a predetermined portion on the electrode wiring 53 is formed by a photoetching technique and a selective etching technique.
The insulating film 54 is sequentially removed to form an electrode window 59, and a protective substrate 61 made of glass or the like is adhered with wax 60 or the like.

Next, lapping from the back surface side of the silicon single crystal 51, a mechanical method such as polishing, or a chemical method using KOH, NaOH is processed into a predetermined thickness smoothly,
After reaching the bottom of the groove 57 and separating each chip, a predetermined position of the protective substrate 61 is diced and divided into chips as shown in FIG.

Then, as shown in FIG. 6, ceramic, beryllia,
An adhesive made of epoxy, polyimide resin, or the like is applied to a predetermined position of the insulating substrate 62 such as glass or the like on the back surface of the chip or the insulating substrate 62 as necessary, and the adhesive layer is formed under predetermined pressure and temperature conditions.
Bond the chips through 63. After that, the adhesive layer 60 made of wax or the like shown in FIG. 5 is melted at a predetermined temperature to remove the protective substrate 61 as shown in FIG.

After that, as shown in FIG. 1, a conductive film of TiAu, CrAu, Al, etc. is coated on the entire surface of the insulating film 58, the insulating substrate 62, etc. by electron beam evaporation, sputtering, etc. A conductive layer, that is, a conductor layer 64, is formed through the electrode window 59 of the pattern and passes over the side surface of the semiconductor chip and is led out onto the insulating substrate 62 to be the substrate wiring. At this time,
Since the silicon single crystal 51 has a sufficiently small thickness, no disconnection or the like is observed even at the step portion of the chip end surface. Furthermore, the width of the conductor layer 64 can be made extremely thin by using a photoetching technique or the like, and a large number of conductor layers 64 can be led out from the end surface of each semiconductor chip. Thus, the desired semiconductor device in Example 1 shown in FIG. 1 was obtained.

Further, FIG. 7 shows a plurality of semiconductor chips 66 in this embodiment.
-1, 66-2, 66-3 is shown as an example in which an insulating substrate is processed at the same time, and semiconductor chips 66-1, 66-2, 66- are formed on an insulating substrate 65 such as ceramic, beryllia or glass. 3 are each bonded via an adhesive layer in a predetermined positional relationship, and are composed of a conductor layer 67 to which the electrode wiring inside each semiconductor chip is connected, and the insulating substrate 65 is an insulator under the conductor layer 67. It has a multi-layered wiring body (not shown) via the wiring board, and is in a state of being connected to the conductor layer 67 in the window opening portion 68 in the substrate.

The manufacturing method of this semiconductor device is that each semiconductor chip 66-1, 66-2, 66-
3 is put in the state of FIG. 5 of the above-mentioned embodiment, and after being bonded to the insulating substrate 65 in a predetermined positional relationship, it is manufactured in exactly the same manner as the above-mentioned embodiment. When manufactured in this manner, since a plurality of chips 66-1, 66-2, 66-3 are processed at the same time in the same process, the number of manufacturing steps per chip is reduced, and the conductor layer 67 is also formed simultaneously. The cost was drastically reduced.

Second Embodiment In the second embodiment, a plurality of semiconductor chips are densely arranged so as to be adjacent to the same substrate.

FIG. 8 shows a conceptual diagram of an embodiment in which the semiconductor chips 70-1 and 70-2 are adhered to the insulating substrate 69 in a state of being adjacent to each other and the conductor wiring 71 leads to the insulating substrate 69 from the electrode wiring in each chip. The chip side surface portion 72 from which the conductor layer 71 is led out is inside the chip end surface.

FIG. 2 shows the semiconductor device according to the first embodiment in which the groove is formed.
In the step shown in FIG. 3, a predetermined pattern is formed so that the side surface portion 72 is on the inner side, after alkali etching, the chip boundary portion is cut with a dicing saw or the like to form a concave groove. It can be manufactured by the same process as in the first embodiment.

In the second embodiment, since the conductor layer 71 between adjacent chips on the same substrate can be made short, there is no fear of wiring delay.
Further, a semiconductor device having a high element density can be manufactured.

In Examples 1 and 2 above, the side surface of the chip that leads out the conductor layer on the insulating substrate from the electrode wiring in the semiconductor chip is inclined in consideration of disconnection and the like. It is possible to lead out the conductor layer on the vertical side surface by taking into consideration such as making the thickness thinner.

Further, although the case where the silicon single crystal is used is described in this embodiment, it is obvious that the present invention can be applied to other materials such as GaAs and InP.

<Effects of the Invention> As is apparent from the above, according to the semiconductor device of the invention of claim 1, the thin film technology, the plating technology, the photoetching technology, the selection technology, along the side surface of the semiconductor chip rather than the electrode wiring in the semiconductor chip. By deriving the conductor layer produced by the etching technique or the like to the insulating substrate, the width of the conductor layer and the distance between the conductor layers can be reduced, and therefore a large number of conductor layers can be led out from the peripheral portion of the semiconductor chip.

Further, even when the elements in the semiconductor chip are miniaturized, a large number of elements are incorporated in a small semiconductor chip, and a large number of conductor layers leading to an insulating substrate are required, a conductor occupying in the semiconductor chip The area of the layer forming portion can be reduced, so that the entire semiconductor chip can be downsized, and a low-cost semiconductor device can be realized.

Further, since a large number of semiconductor chips bonded to the insulating substrate can be processed at the same time, the number of assembling work steps is small and the manufacturing cost can be reduced.

Further, when a plurality of semiconductor chips are arranged on the same insulating substrate, the side surface of the semiconductor chip leading out the conductor layer can be provided inside the end surface of the semiconductor chip. The wiring connecting the chips can be shortened and the wiring delay can be reduced.

Further, the conductor layer derived from the electrode wiring in the semiconductor chip can be produced by a thin film technique such as sputtering, a photoetching technique, etc., and a metallurgical connection by pressure bonding or metal fusion such as the conventional wire bond system or flip chip system. Therefore, high reliability can be expected.

Further, the conductor layer led out from the electrode wiring in the semiconductor chip to the insulating substrate becomes the substrate wiring on the insulating substrate,
Since it is not necessary to separately prepare wiring on the insulating substrate in advance, the insulating substrate used is inexpensive.

Further, since the substrate wiring on the insulating substrate is processed at the same time in the step of forming the conductor layer, the manufacturing cost can be reduced as compared with the case of performing the processing separately.

Further, according to the method of manufacturing a semiconductor device of the invention of claim 2, after forming at least electrode wiring on the semiconductor substrate and forming a recess of a predetermined depth at the chip boundary portion of the semiconductor substrate, the recess of the recess is formed. An insulating film is formed along the inner peripheral surface, a protective base is adhered to the semiconductor substrate via a first adhesive layer on the insulating film, and the back surface of the semiconductor substrate is smoothed to form the recess The bottom is opened to separate the semiconductor substrate into predetermined semiconductor chips including the electrode wiring, and the back surface of the semiconductor chip and the front surface of the insulating substrate are bonded to each other via a second adhesive layer, and the first adhesive layer is formed. After removing the protective substrate,
After covering the entire surface of the insulating substrate and the semiconductor chip with a conductive thin film, a predetermined conductor layer that is electrically connected to the electrode wiring, passes over the side surface of the semiconductor chip, and is led out onto the insulating substrate is integrally formed. Therefore, the width of the conductor layers and the distance between the conductor layers can be reduced, and thus a semiconductor device can be manufactured in which a large number of conductor layers are led out from the peripheral portion of the semiconductor chip.

Further, even when the elements in the semiconductor chip are miniaturized, a large number of elements are incorporated in a small semiconductor chip, and a large number of conductor layers leading to the insulating substrate are required, the conductor layers occupying in the semiconductor chip The area of the forming portion can be reduced, and therefore the entire semiconductor chip can be reduced, and an inexpensive semiconductor device can be manufactured.

Further, since a large number of semiconductor chips bonded to the insulating substrate can be processed at the same time, it is possible to manufacture a semiconductor device with a small number of assembling steps and a low manufacturing cost.

Further, when a plurality of semiconductor chips are arranged on the same insulating substrate, the side surface of the semiconductor chip leading out the conductor layer can be provided inside the end surface of the semiconductor chip. It is possible to manufacture a semiconductor device in which wiring connecting chips is shortened and wiring delay is reduced.

Further, the conductor layer derived from the electrode wiring in the semiconductor chip can be produced by a thin film technique such as sputtering or a photoetching technique, and is not a metallurgical connection by pressure bonding or metal melting like the conventional wire bond system and flip chip system. Therefore, a highly reliable semiconductor device can be manufactured.

Further, the conductor layer led out from the electrode wiring in the semiconductor chip to the insulating substrate becomes a substrate wiring on the insulating substrate, there is no need to separately prepare wiring on the insulating substrate in advance, and the insulating substrate to be used becomes inexpensive, A low-cost semiconductor device can be manufactured.

Furthermore, since the substrate wiring on the insulating substrate is simultaneously processed in the step of forming the conductor layer, the manufacturing cost can be reduced as compared with the case of separately processing.

[Brief description of drawings]

1 to 7 show an embodiment of the present invention. FIG. 1 is a partial sectional view of a semiconductor device after completion, and FIGS. 2 to 6 are respective parts in the manufacturing process thereof. FIG. 7 is a cross-sectional view, and FIG. 7 is a conceptual diagram of the completed semiconductor device when a plurality of chips are simultaneously processed. FIG. 8 is a partial conceptual view of a semiconductor device after completion of another embodiment of the present invention. 51 …… silicon wafer, 52,54,58 …… insulating film, 53,59 …… electrode wiring, 60,63 …… adhesive layer, 61 …… protective substrate, 62,65 …… insulating substrate, 64 …… conductor layer.

Claims (2)

[Claims] 1. A conductor having a semiconductor chip adhered to an insulating substrate, electrically connected to electrode wiring on the semiconductor chip, and led out from the electrode wiring side onto the side surface of the semiconductor chip onto the insulating substrate. A semiconductor device in which layers are integrally formed. 2. A step of forming at least electrode wiring on a semiconductor substrate, and forming a recess having a predetermined depth at a chip boundary portion of the semiconductor substrate, and then forming an insulating film along the inner peripheral surface of the recess. And a step of adhering a protective substrate to the semiconductor substrate on the insulating film via a first adhesive layer, and smoothing the back surface of the semiconductor substrate to open the bottom of the recess, A step of separating the semiconductor substrate into a predetermined semiconductor chip including the electrode wiring, a step of adhering a back surface of the semiconductor chip and a front surface of an insulating substrate via a second adhesive layer, the first adhesive layer and the protection After removing the base body, after covering the entire surface of the insulating substrate and the semiconductor chip with a conductive thin film, the substrate is electrically connected to the electrode wiring, passes through the side surface of the semiconductor chip from the electrode wiring side, and the insulating substrate Derived above The method of manufacturing a semiconductor device characterized by a step of forming integrally a predetermined conductor layers.