JPH0691166B2 - Integrated circuit board - Google Patents
Integrated circuit boardInfo
- Publication number
- JPH0691166B2 JPH0691166B2 JP60258846A JP25884685A JPH0691166B2 JP H0691166 B2 JPH0691166 B2 JP H0691166B2 JP 60258846 A JP60258846 A JP 60258846A JP 25884685 A JP25884685 A JP 25884685A JP H0691166 B2 JPH0691166 B2 JP H0691166B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- cob
- circuit board
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/401—Resistive arrangements
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路搭載基板に関し、特に絶縁体基板の
一部領域を除く全面に高抵抗の印刷抵抗膜を形成した集
積回路搭載基板に関する。Description: TECHNICAL FIELD The present invention relates to an integrated circuit mounting board, and more particularly to an integrated circuit mounting board in which a high resistance printed resistance film is formed on the entire surface of an insulating substrate except a part thereof. .
従来、この種の集積回路搭載基板（以下COBと略記す
る）は表面処理は行なわずにそのまま時計などに用いら
れてきた。Conventionally, this type of integrated circuit board (hereinafter abbreviated as COB) has been used as it is as a watch without surface treatment.
上述した従来のCOBは、絶縁体となっているので、COB基
板上又はIC上で、電荷が、局在しやすく、その結果、IC
又はCOB基板上にて局部的に高電位となり、そこから放
電することによってICが絶縁破壊を起こすといった欠点
がある。Since the conventional COB described above is an insulator, the electric charges are likely to be localized on the COB substrate or on the IC, and as a result, the IC
Alternatively, there is a drawback in that the high potential is locally generated on the COB substrate and the IC causes dielectric breakdown by discharging from there.
本発明の目的は、集積回路搭載基板及びICの全面に均一
に電荷を分散させ電荷の局在を防ぎ局部的に高電位にな
るのを防ぐことができる集積回路搭載基板を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit mounting board and an integrated circuit mounting board which can evenly disperse electric charges over the entire surface of the IC to prevent the localization of the electric charges and locally prevent the electric potential from becoming a high potential. .
本発明の集積回路搭載基板は、絶縁体基板上に集積回路
チップを搭載し、集積回路チップより引き出した電極を
絶縁基板上に配置した集積回路搭載基板において、前記
基板の電極および集積回路チップ取付部を除く基板全面
に高抵抗の印刷抵抗膜を形成することによって構成され
る。The integrated circuit mounting board of the present invention is an integrated circuit mounting board in which an integrated circuit chip is mounted on an insulating substrate and electrodes drawn from the integrated circuit chip are arranged on the insulating substrate. It is configured by forming a high resistance printed resistance film on the entire surface of the substrate excluding the parts.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ），（ｃ）は本発明の一実施例の平
面図、応用例の斜視図及び第１図（ｂ）の断面図であ
る。1 (a), (b), and (c) are a plan view of an embodiment of the present invention, a perspective view of an application example, and a sectional view of FIG. 1 (b).
第１図（ａ）及び第１図（ｃ）に示すように、本実施例
のCOBは絶縁体基板１上に集積回路チップ２を搭載し集
積回路チップより引き出した電極３を絶縁基板上（第１
図（ａ）では集積回路搭載面の反対面）に配置する集積
回路搭載基板において、基板の集積回路チップ取付部お
よび電極３を除く全面に亘って高抵抗の印刷抵抗膜７を
形成して構成されている。なお本実施例では集積回路チ
ップ２はモールド樹脂８により被覆されており、該被覆
部及び電極３を除く全面が印刷抵抗膜で被覆されてい
る。なお第１図（ａ）では印刷抵抗膜は図示していな
い。As shown in FIGS. 1 (a) and 1 (c), in the COB of this embodiment, an integrated circuit chip 2 is mounted on an insulating substrate 1 and an electrode 3 extracted from the integrated circuit chip is placed on the insulating substrate ( First
In the integrated circuit mounting substrate arranged on the surface opposite to the integrated circuit mounting surface in FIG. 2A, a printed resistance film 7 having a high resistance is formed over the entire surface of the substrate excluding the integrated circuit chip mounting portion and the electrode 3. Has been done. In this embodiment, the integrated circuit chip 2 is covered with the mold resin 8, and the entire surface except the covering portion and the electrode 3 is covered with the printed resistance film. The printed resistance film is not shown in FIG.
第１図（ｂ）及び第１図（ｃ）は本実施例の応用例で、
プラスチック性のカードに実装した斜視図及び断面図で
あるが、カード４にはCOB1をはめ込むための凹部があ
り、接着面５においてカード４と印刷抵抗膜７により大
部分がおおわれたCOB1が接着剤６により接着されてカー
ドが形成されている。FIG. 1 (b) and FIG. 1 (c) are application examples of this embodiment.
1A and 1B are a perspective view and a cross-sectional view mounted on a plastic card. The card 4 has a recess for fitting the COB1, and the COB1 which is mostly covered with the card 4 and the printed resistance film 7 on the adhesive surface 5 is an adhesive. The card is formed by bonding with 6.
なお、本実施例に使用する印刷抵抗膜は高抵抗である必
要があるが実験の結果10kΩ〜10MΩ／□のものが本目的
を達成することが出来るが、10kΩ／□以下の低抵抗に
なるとリーク電流が多くなり、この面で製品規格に不適
合となり易く、また10MΩ以上になると本発明の効果が
すくなくなる。以上のことから10MΩ／□程度が好都合
である。It should be noted that the printed resistance film used in this example needs to have a high resistance, but as a result of an experiment, a film having a resistance of 10 kΩ to 10 MΩ / □ can achieve this object, but if the resistance becomes 10 kΩ / □ or lower, In this respect, the leak current increases, and the product standard is liable to be incompatible with this. In addition, when the leak current is 10 MΩ or more, the effect of the present invention becomes poor. From the above, about 10 MΩ / □ is convenient.
なお、COBの製作工程にレジスト塗布というのがある
が、このレジストを1MΩ／□程度のものを用いても全く
同じ効果を発揮することができる。Although there is a resist coating process in the COB manufacturing process, the same effect can be achieved by using a resist of about 1 MΩ / □.
以上説明したように、本発明は、COBの全面に亘って、
高抵抗（1MΩ／□程度）の印刷抵抗を塗布することによ
り、COB基板及びICが、ほぼ同電位となる。もし、COB基
板のある部分に、又はICのある部分に誘電電荷が蓄積し
ても、COB基板又はICの全面に均一に電荷が分散するの
で、電荷の局在を防ぐことができ、つまり、局部的に高
電位になるのを防ぐ効果がある。As described above, the present invention, across the entire surface of the COB,
By applying a high resistance (about 1 MΩ / □) printing resistor, the COB substrate and the IC have almost the same potential. Even if a dielectric charge is accumulated on a part of the COB substrate or a part of the IC, the charge is evenly distributed over the entire surface of the COB substrate or the IC, so that the localization of the charge can be prevented, that is, It has the effect of preventing the potential from becoming locally high.
第１図（ａ），（ｂ），（ｃ）はそれぞれ本発明の一実
施例の平面図、第１図（ａ）の応用例の斜視図及び断面
図である。 １……集積回路搭載基板（COB）、２……集積回路、３
……電極、４……カード、５……接着面、６……接着
剤、７……印刷抵抗膜、８……モールド樹脂。1 (a), (b) and (c) are respectively a plan view of an embodiment of the present invention, a perspective view and a sectional view of an application example of FIG. 1 (a). 1 ... Integrated circuit board (COB), 2 ... Integrated circuit, 3
...... Electrode, 4 ... Card, 5 ... Adhesive surface, 6 ... Adhesive, 7 ... Printed resistance film, 8 ... Mold resin.
Claims (1)
集積回路チップより引き出した電極を絶縁体基板上に配
置した集積回路搭載基板において、前記基板の電極およ
び集積回路チップ取付部を除く基板全面に高抵抗の印刷
抵抗膜を形成したことを特徴とする集積回路搭載基板。1. An integrated circuit chip is mounted on an insulating substrate,
In an integrated circuit mounting substrate in which electrodes drawn from an integrated circuit chip are arranged on an insulating substrate, a high resistance printed resistance film is formed on the entire surface of the substrate excluding the electrodes of the substrate and the integrated circuit chip mounting portion. Integrated circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60258846A JPH0691166B2 (en) | 1985-11-18 | 1985-11-18 | Integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60258846A JPH0691166B2 (en) | 1985-11-18 | 1985-11-18 | Integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62118548A JPS62118548A (en) | 1987-05-29 |
| JPH0691166B2 true JPH0691166B2 (en) | 1994-11-14 |
Family
ID=17325839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60258846A Expired - Lifetime JPH0691166B2 (en) | 1985-11-18 | 1985-11-18 | Integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691166B2 (en) |
-
1985
- 1985-11-18 JP JP60258846A patent/JPH0691166B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62118548A (en) | 1987-05-29 |
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