JPH0691264B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a junction field effect transistor, and a p channel field effect transistor which forms a complementary circuit together with an n channel Schottky barrier field effect transistor. A suitable manufacturing method.

Microelectronics has become the foundation of modern industrial development and has great social effects. At present, the leading role of this microelectronics is a silicon (Si) integrated circuit device, but a complementary MOS (CMOS) circuit has been very effective in reducing power consumption.

On the other hand, gallium arsenide (GaAs), which has a high electron mobility, is used to achieve higher speeds that exceed the limits based on the physical properties of silicon.
Although a semiconductor device using a compound semiconductor such as the above has been developed, it is conventionally limited to the n-channel type.

However, it is desired to reduce the power consumption by forming a complementary circuit also in this compound semiconductor device.

[Conventional technology]

A CMOS inverter is represented by the circuit diagram shown in FIG. 2A as an example of a complementary circuit that has a large effect of reducing power consumption because it does not consume power in principle in a steady state.

In the figure, T ₁ and T ₂ are enhancement mode MOS field effect transistors (MOS FEs) that operate in opposite polarities.
T), for example, the driver T ₁ is an n channel and the load T ₂ is a p channel.

If the input voltage V _IN is made sufficiently low in this circuit, the load T ₂ is turned on and the driver T ₁ is turned off, and the output voltage V _OUT becomes a high voltage almost equal to V _DD , and if the input voltage V _IN is made sufficiently high. , The driver T ₁ is turned on, the load T ₂ is turned off, and the output voltage V _OUT becomes a low voltage almost equal to V _SS . In these two states, almost no current flows, and only when the states transit, both MOSFETs T ₁ and T ₂ are turned on and a current flows.

As described above, the complementary circuit has the advantages of extremely low static power consumption, small power consumption and operating time product, and large noise margin. Currently, it is widely used in Si semiconductor devices. However, in order to configure this, for example, a structure whose side cross section is shown in FIG. 2B is performed.

In the figure, 31 is an n-type Si substrate, and a field oxide film
32 defines n-channel and p-channel FET regions, and the p ^- type well layer 33,
n ⁺ type source and drain regions 34 and p ⁺ channel cuts 35
However, p ⁺ type source and drain regions 36 and n ⁺ type channel cuts 37 are formed in the p channel FET region, respectively.

In addition, a gate electrode 39 is formed on the Si substrate 31 via a gate oxide film 38.
Are provided respectively, and each source and drain region 34 and
36 and the gate electrode 39 through the insulating film 40, the metal wiring 41
Is provided.

On the other hand, as a compound semiconductor transistor, a field effect transistor is being developed due to the fact that the manufacturing process is simple, and the like. It is difficult to realize the Schottky barrier type and the junction type, and the Schottky barrier type having the simplest structure is most commonly used.

The first reason for using a compound semiconductor in a transistor is that its electron mobility is as large as 6 times that of Si in GaAs,
Moreover, since the saturation drift velocity is also high, it is possible to achieve higher speed than Si. However, the mobility of holes in compound semiconductors is much smaller than that of electrons.
It is smaller than Si. Therefore, the conventional compound semiconductor field effect transistors are almost limited to the n-channel type. Particularly, in the Schottky barrier type, the p-type semiconductor is less attractive because the barrier height of the p-type semiconductor is smaller than that of the n-type semiconductor.

[Problems to be solved by the invention]

Although the compound semiconductor device is in the situation as described above, it is necessary to realize a complementary circuit in order to promote the energy reduction.

The n-channel element of the complementary circuit is preferably the Schottky barrier type, which has the simplest structure and a large amount of technical accumulation, and the p-channel element is preferably the junction type, and it is necessary to develop the optimum structure. .

[Means for solving problems]

The above-mentioned problem is a method of manufacturing a semiconductor device having a complementary structure by combining a p-channel junction field effect transistor and an n-channel Schottky barrier field effect transistor, which is a p-type on a semi-insulating compound semiconductor substrate. On the p-channel junction type field effect transistor formation region, and a step of stacking the first compound semiconductor layer and an n-type second compound semiconductor layer which is joined to the p-type first compound semiconductor layer, Forming a p-channel gate electrode in ohmic contact with the n-type second compound semiconductor layer on the n-type second compound semiconductor layer; and forming a p-channel gate electrode on the n-channel Schottky barrier type field effect transistor forming region. forming a gate electrode in Schottky contact with the n-type second compound semiconductor layer on the n-type second compound semiconductor layer; Patterning the n-type second compound semiconductor layer on the field effect transistor formation region in alignment with the gate electrode, and on both sides of the p channel junction type field effect transistor formation region with the gate electrode interposed therebetween. Forming a p-type region having a higher impurity concentration than the p-type first semiconductor layer so as to reach the semi-insulating substrate to form a source and drain region of the p-channel junction field effect transistor; The n-type second electrode is provided on both sides of the n-channel gate electrode.
The n-type region having a higher impurity concentration than the semiconductor layer reaches the semi-insulating substrate to serve as the source and drain regions of the n-channel Schottky barrier field effect transistor. This is solved by the method of manufacturing the device.

[Action]

A method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor substrate provided with a second semiconductor layer of a second conductivity type, especially an n-type, in contact with an upper surface of a first semiconductor layer of a first conductivity type, especially a p-type. To use.

A gate electrode that makes ohmic contact with the second semiconductor layer is provided, and the second semiconductor layer is patterned using the gate electrode as a mask to define a pn junction region. Then, a first-conductivity-type high impurity concentration region is formed in the first semiconductor layer in alignment with the gate electrode by an ion implantation method or the like using the gate electrode as a mask.

In the above structure, the region under the pn junction of the first semiconductor layer is the channel, the high impurity concentration region is the source and drain, and the depletion layer formed in the channel region by the pn junction is controlled by the voltage applied to the gate electrode. By
A junction field effect transistor in which the impedance of the channel is controlled is realized.

The present semiconductor substrate is provided with another gate electrode that makes Schottky contact with the second semiconductor layer and source and drain electrodes that make ohmic contact, so that the Schottky barrier having a channel whose conductivity type is opposite to that of the junction field effect transistor. The field effect transistor can be easily formed, and the two can be combined to form a complementary circuit.

The junction field-effect transistor according to the present invention has a small junction capacitance and a reduced source resistance to obtain a high operation speed, and can be combined with an n-channel Schottky barrier field effect transistor as a p-channel element of a complementary circuit. Has optimal properties.

〔Example〕

The present invention will be specifically described below with reference to examples. FIG. 1 is a cross-sectional view in order of steps of an embodiment in which the present invention is applied to a complementary circuit. A region labeled p-ch on the right side of the figure is a p-channel junction field effect transistor according to the present invention, and an n-type on the left side is n- ch
The region indicated by represents an n-channel Schottky barrier field effect transistor.

See FIG. 1 (a). For example, the impurity concentration is 1 × 10 ¹⁷ on the semi-insulating GaAs substrate 1.
The p-type GaAs layer 2 having a thickness of about cm ^{−3 is formed} to have a thickness of about 0.2 μm,
Next, for example, n-type GaAs with an impurity concentration of about 5 × 10 ¹⁷ cm ^-3
The layer 3 is sequentially epitaxially grown to have a thickness of, for example, about 0.05 μm.

Then, a p-channel gate electrode 4 and an n-channel gate electrode 5 are provided respectively. In order to make ohmic contact with the n-type GaAs layer 3, the p-channel gate electrode 4 is provided with, for example, a tungsten silicide (WSi) layer 4b via a germanium (Ge) layer 4a having a thickness of about 20 nm. The n-channel gate electrode 5 is directly formed of, for example, WSi so as to make Schottky contact with the n-type GaAs layer 3.

See FIG. 1 (b). N in the p-channel junction field effect transistor formation region
The type GaAs layer 3 is selectively removed by using the gate electrode 4 as a mask. N-type left under the gate electrode 4 by this treatment
A pn junction is defined by the GaAs layer 3A.

See FIG. 1C. Impurities are introduced into the source and drain regions 6 and 7 of both the p-channel and n-channel transistor elements, respectively.

For p-channel devices, acceptor impurities such as magnesium (Mg), zinc (Zn) or beryllium (B
e) to a dose of about 1 × 10 ¹⁵ cm ^-2 , and for n-channel devices, donor impurities such as silicon (Si).
Are ion-implanted at a dose of about 1 × 10 ¹³ cm ^-2 and an activation heat treatment is performed.

As a result, the source and drain regions 6 of the p-channel device
Is 1 × 10 ¹⁹ cm ^-3 , n-channel source and drain region 7
^Has a maximum impurity concentration of about 1 × 10 ¹⁹ cm ^-3 .

See Fig. 1 (d). The element isolation region 8 has oxygen ions (O ⁺ ) and protons (H ⁺ )
Etc. are formed by ion implantation.

The insulating film 9 is provided and the source and drain electrodes are provided. The source and drain electrodes 10 of the p-channel element are made of, for example, gold / zinc (Au / Zn), and the source and drain electrodes 11 of the n-channel element are made of, for example, gold germanium / gold (AuGe).
/ Au) and can be formed by a conventional technique.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a high-speed junction field effect transistor having a small junction capacitance and parasitic resistance.

Further, the junction field-effect transistor of the present invention can be easily formed on the same semiconductor substrate as the Schottky barrier field-effect transistor, and a p-type which is combined with the n-channel Schottky barrier field-effect transistor to form a complementary circuit. As a channel field effect transistor, it is possible to obtain the effect of a p-channel Schottky barrier type or higher in which it is difficult to secure the gate breakdown voltage, and it is possible to contribute to the energy reduction of the compound semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view in order of steps showing an embodiment of the present invention, FIG. 2 (a) is a circuit diagram of a complementary inverter, and FIG. 2 (b) is a sectional view showing a conventional example of a CMOS structure. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a p-type GaAs layer, and 3 and 3A are n.
Type GaAs layer, 4 is a gate electrode in ohmic contact, 5 is a gate electrode in Schottky contact, 6 is a p-type source and drain region, 7 is an n-type source and drain region, 8 is an element isolation region, 9 is an insulating film , 10 and 11 denote source and drain electrodes.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a complementary structure by combining a p-channel junction field effect transistor and an n-channel Schottky barrier field effect transistor, comprising: a semi-insulating compound semiconductor substrate (1). A step of laminating a p-type first compound semiconductor layer (2) and an n-type second compound semiconductor layer (3) that is bonded to the p-type first compound semiconductor layer (2), A p-channel gate electrode (4) in ohmic contact with the n-type second compound semiconductor layer (3) on the n-type second compound semiconductor layer (3) on the p-channel junction field effect transistor formation region. And a Schottky contact with the n-type second compound semiconductor layer (3) on the n-type second compound semiconductor layer (3) on the n-channel Schottky barrier field effect transistor formation region. A step of forming a gate electrode (5) according to the present invention, and patterning the n-type second compound semiconductor layer (3) on the p-channel junction type field effect transistor forming region in alignment with the gate electrode (4). And a p-type region having a higher impurity concentration than the p-type first semiconductor layer (2) on both sides of the gate electrode (4) on the p-channel junction field effect transistor formation region. Source and drain regions (6) of the p-channel junction field effect transistor formed so as to reach the insulating substrate (1)
And an n-type region having a higher impurity concentration than the n-type second semiconductor layer (3) on both sides of the n-channel gate electrode (5) on the semi-insulating substrate (1). And a source region and a drain region (7) of the n-channel Schottky barrier field effect transistor.