JPH0691442B2 - Level shift circuit - Google Patents

Description

The present invention relates to a level shift circuit for converting a signal having a certain voltage amplitude into a signal having another voltage amplitude, and particularly to a level shift circuit for driving a flat panel or the like. The present invention relates to a level shift circuit of a high voltage IC that converts a logic signal into a high voltage flat panel drive signal.

[Conventional technology]

Conventionally, this main level shift circuit has one CMOS circuit in which the drains of an N-type MOS FET and a P-type MOS FET are connected to each other and an element size (so-called dimension) as shown in FIG.
Another CMOS circuit with the same value is prepared, and the gate of the P-type MOS FETO of one CMOS circuit is alternately connected to the common drain of the other CMOS circuit. The low voltage signal was input and the high voltage signal was taken out from the drain.

[Problems to be Solved by the Invention]

In the above-described conventional technique, the dimensions of N-type and P-type of each CMOS are different, but the two corresponding CMOSs are the same.

Dimensions such as gate length L and gate width W are N type and P
Type MOS FETs have different current capabilities, so the dimension ratio between N type and P type is changed in one common CMOS circuit. Usually, this kind of level shift circuit takes out one common drain to the output as shown in FIG. 3 or another CM.
Connect to the gate of the OS circuit, do not connect the other common drain to the outside. In this way, since the loads connected to the common drain are different in the two-stage CMOS, when the dimensions of the two-stage CMOS are set to the same dimension, the dimensions are determined so that a heavy load can be sufficiently driven. It is too large and wasteful, and the element area increases.

Further, when a signal changes, a through current flows from the P-type to the N-type, but the larger the dimension is, the larger this current is. Therefore, the extra large dimension leads to an increase in power consumption.

[Means for Solving the Problems]

The level shift circuit of the present invention is provided with two stages of CMOS circuits in which drains of N-type and P-type MOS FETs are connected to each other.
Level shift of the type that connects the gate of P-type MOS FET of the CMOS circuit alternately to the common drain of the other CMOS circuit, inputs the low voltage signal to the gate of the N-type MOS FET, and takes out the high voltage signal from the common drain. In the circuit, of the two-stage CMOS circuits, the one with the smaller load connected to the drain is set to have a relatively smaller dimension.

〔Example〕

 The present invention will now be described in more detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. MN1 and MN2 are N-type MOS FETs, and because a high voltage is applied to the drain on the circuit, a so-called offset that puts a low concentration layer in the drain
The MOS structure is used to increase the breakdown voltage of the drain. MP1 and MP2 are P-type MOS FETs, and since a high voltage is applied to the drain and gate on the circuit as well, the gate oxide film is thickened in addition to the above-mentioned offset structure, and the breakdown voltage of the gate is also increased. The load capacity CI represents the load connected to the outside or the equivalent capacity of the circuit in the next stage. Normal MO
Since the gate length L of the S FET is determined by the process, the dimension of the element changes the gate width W. MOS FET MN1, MP1
Of the first CMOS dimension X _N1 , X _P1
The double dimension nX _N1 and nX _P1 are the dimensions of the second CMOS composed of MOS FETs MN2 and MP2. n is almost determined by the ratio of the load capacitance C _L1 and the parasitic capacitance C _P1 n ≈ C _L1
/ C _P1 . Normally C _L1 >> _P1 , so n> 1. X
The absolute values of _N1 and _XP1 are the required speed and power consumption M
Determined by the current capability of OS FET.

The low voltage signal IN and the low voltage signal IN are signals of opposite polarities and are input to the terminals 3 and 4, respectively. Now, when the signal IN is at the logic level L and the signal IN is at "H", the MOS FET MN1 is off, the MOS F
ET MN2 is turned on, the gate potential of MOS FET MP1 is lowered, MOS FET MP1 is turned on, the drain potential of MOS FET MP1 is raised, MOS FET MP2 is turned off, and 5 of the high voltage signal terminal is “H”. Becomes Conversely, signal IN is "H", signal IN
Is "L", the terminal 5 for the high voltage signal is "L". In this way, the high voltage signal at the terminal 5 can be controlled by the low voltage signals IN, IN .

As mentioned above, load capacitance C _L1 >> Parasitic capacitance C _P1
The dimensions of FET MN1 and MP1 can be driven sufficiently fast even if they are small. When MOS FET MN1 changes from off to on, the MOS
Since the FET MP1 is still on, it is in the on / on period temporarily and a through current flows through the MOS FET MP1 and MN1. By reducing the dimensions of MOS FET MN1 and MP1, this through current can be reduced and power consumption can be reduced. Further, by reducing the dimension, it is possible to significantly reduce the element area.

FIG. 2 is a circuit diagram of another embodiment of the present invention. Similar to the embodiment shown in FIG. 1, the drains of the MOS FETs MN3, MN4, MP3 and MP4 all have high breakdown voltage, and the gates of the MOS FETs MN3 and MN4 also have high breakdown voltage. In this embodiment, since a low voltage signal is input to the P-type MOS FET side, it can be converted into a negative high voltage signal. As with the embodiment of FIG. 1, a small level shift circuit with low power consumption can be constructed.

〔The invention's effect〕

As described above, the present invention uses the MOS in the embodiment of FIG.
According to the dimensions of FET MN1, MP1, MN2, MP2 to the capacitance connected to the drain, the dimensions of MOS FET MN1, MP1 connected with a capacitance as small as the parasitic capacitance should be small,
By increasing the dimension of MOS FET MN2, MP2, which is connected to a large load capacitance, the optimum dimension for obtaining a certain speed can be configured, and the element area and power consumption are significantly reduced compared to the level shift circuit of the prior art. it can.

[Brief description of drawings]

1 is an equivalent circuit diagram of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of another embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of a conventional circuit. MN1 to 6 ... N type MOS FET, MP1 to 6 ... P type MOS FET, C
_{P1 to} C _P3 …… Parasitic capacitance, C _{L1 to} C _L3 …… Load capacitance. 1 ... Ground, 2 ... High-voltage power supply, 3 ... Low-voltage signal IN , 4 ... Low-voltage signal IN, 5 ... High-voltage signal, 6 ...
Ground, 7 ... High voltage negative power supply, 8 ... Low voltage signal I
N, 9 ... Low voltage signal IN , 10 ... High voltage signal, 11 ... Ground, 12 ... High voltage power supply, 13 ... Low voltage signal IN, 14
…… Low voltage signal IN , 15 …… High voltage signal.

Claims (1)

[Claims] 1. A two-stage CMOS circuit in which drains of an N-type MOS FET and a P-type MOS FET are connected to each other is prepared, and a gate of one conductivity type MOS FET of one CMOS circuit is used as a common drain of the other CMOS circuit, respectively. In a level shift circuit that connects alternately, inputs a signal of voltage amplitude at the gate of the opposite conductivity type MOS FET, and takes out a signal of another voltage amplitude from the common drain, the load connected to the drain of the two-stage CMOS circuit A level shift circuit characterized by relatively reducing the element size of the smaller CMOS circuit.