JPH0691555B2 - Transmitter / receiver of serial data - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication device, and provides a transmission / reception device that is simple in structure and capable of handling advanced communication, and is particularly suitable for a microprocessor. It realizes the device.

2. Description of the Related Art Conventionally, a serial data communication device that has been frequently used in a one-chip microprocessor or the like is composed of a shift register, a shift counter, and a buffer register, and a typical example thereof is Japanese Patent Publication No. 60-58482. (Hereinafter abbreviated as Document 1).

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, since the device as described in the above-mentioned document 1 is mainly composed of the random logic circuit, the number of wirings between the respective circuit blocks is large and the circuit structure becomes complicated. However, if a large amount of data is to be communicated at one time, most of the processing must rely on software, and the circuit configuration must be changed each time for higher-level communication or high-speed data transfer. there were.

Means for Solving the Problems In order to solve the above-mentioned problems, in a serial data transmitting / receiving apparatus of the present invention, a counter to which a transmission / reception clock is supplied and an output of the counter are supplied and increment or decrement of the counter is supplied. An incrementing means or a decrementing means for controlling, a control means for activating the incrementing means or the decrementing means at the time of transmission or reception, and parallel data are transmitted and received between the data bus,
The communication means comprises a memory for transmitting / receiving the data of the bit position decoded by the output of the increment means or the decrement means to / from the serial input / output terminal.

Action In the present invention, the above-mentioned configuration provides a simpler configuration,
Moreover, it is possible to realize a versatile communication device.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a case in which a serial data transmitting / receiving apparatus according to an embodiment of the present invention is applied to a microprocessor, and a 4-bit down signal to which a transmission / reception clock is supplied via a serial clock terminal 10. counter
100 and the incrementer 15 that is supplied with the output of the down counter 100 and increments the count data thereof.
0, the NAND gate 1 that activates the increment 150 at the time of reception, and parallel data is transmitted and received between the data bus 200, and the data at the bit position decoded by the output of the incrementer 150 is the serial input / output terminal. Random access memory 300 exchanged with 20
The main part is composed of. The output of the down counter 100 is supplied to the D terminal of the D flip-flop 4 via the AND gate 2 and the OR gate 3, and the output signal of the D flip-flop 4 is a transmission / reception operation completion notification terminal.
It is configured to be supplied to 30 and to be an interrupt request signal to the microprocessor via the NOR gate 5 and the interrupt output terminal 31. Further, the reset terminal 40 and the clear terminal 50 are connected to a non-latch type output port of the microprocessor to be supplied with a reset signal by software, and the interrupt prohibition terminal 60 and the frame length selection terminal 70 of transmission / reception data are both latched by the microprocessor. It is connected to the output port of the format and used for interrupt control by software and switching of interrupt timing. The signal supplied to the serial input / output terminal 20 is applied to the serial data input terminal 310 of the random access memory 300 via the Schmidt type inverter 6 and the inverter 7.
The D terminal of the D flip-flop 8 for waveform shaping is connected to the serial data output terminal 320 of the random access memory 300, and the output signal of the D flip-flop 8 is passed through the 3-state inverter 9 to the serial input / output terminal 20. Is configured to be delivered to. Meanwhile, the timing signal generated by the timing signal generating circuit 500 from the clock signal supplied to the serial clock terminal 10 and the clock signal supplied to the system clock input terminal 90 is the serial data read clock input of the random access memory 300. It is supplied to the terminal 330. A transmission / reception switching terminal 80, to which the control terminal of the 3-state inverter 9 and the input terminal of the NAND gate 1 are connected, is connected to a latch-type output port of the microprocessor and is used for switching transmission / reception by software. The control signal by the micro instruction is supplied to 81, and the block select terminal
A selection signal for activating the parallel input / output unit of the random access memory 300 is supplied to 82.

The operation of the transmitter / receiver configured as described above will be described based on the timing charts of the main parts shown in the configuration diagram of FIG. 1 and FIG.

First, FIG. 2A shows a clock signal waveform supplied to the serial clock terminal 10, and FIG. 2B shows a reset signal waveform supplied to the reset terminal 40. C, D, E, and F are output signal waveforms of each bit of the down counter 100, and are shown in FIG.
H shows the output signal waveforms of the NAND gate 1 and the AND gate 2, respectively, FIG. 2I shows the output signal waveform of the D flip-flop 4, and FIG. 2J shows the serial input / output terminals. The change of the serial data sent to 20 is shown in Fig. 2K.
20 shows the timing at which the data supplied to 20 is read into the random access memory 300.

In order to transmit serial data by the device shown in FIG. 1, as shown in FIG. 2, the state of the down counter 100 is set to [1111] and the D flip-flop 4 is reset in advance. 16 bits or 8 bits of transmission bits are written from the bus 200 to the random access memory 300. Next, if the level of the transmission / reception switching terminal 80 is shifted to '1' in the transmission state and the clock signal for transmission is supplied to the serial clock terminal 10, the down counter is reached every time its leading edge arrives.
As shown in FIGS. 2C to 2F, the count value of 100 is [111
0], [1101], and so on.
The bit position of the data of the random access memory 300 sent to the D terminal of the D flip-flop 8 is also switched. As a result, transmission data is sent to the serial input / output terminal 20 each time the leading edge of the clock signal supplied to the D flip-flop 8 arrives, but when the count value of the down counter 100 becomes [1111], AND The output level of the gate 2 shifts to "1", and the output level of the D flip-flop 4 shifts to "1" at the trailing edge of the clock signal supplied to the serial clock terminal 10 as shown in FIG. 2I. Then, the interrupt request signal is sent to the interrupt output terminal 31. As a result, the microprocessor initiates the interrupt handling routine, and the data bus 200 drives the random access memory 3 as needed.
16-bit or 8-bit transmission data is rewritten to 00 to prepare for transmission of the subsequent data.

As can be seen from FIGS. 1 and 2, when the level of the frame length selection terminal 70 is "1", the D flip-flop 4 is activated when 16 bits of data are transmitted.
The output of the D flip-flop 4 shifts to "1", but when the level is "0", the output of the D flip-flop 4 shifts to "1" when 8 bits of data are transmitted.

By the way, the output signal from the timing signal generation circuit 500 is supplied to one input terminal of the NAND gate 1 of FIG. 1 and the serial data read clock input terminal 330 of the random access memory 300. The operation of 500 will be described with reference to the timing chart shown in FIG.

3A shows a clock signal supplied to the system clock input terminal 90, and FIG. 3B shows a clock signal for transmission / reception applied to the serial clock terminal 10. FIGS. C, D, and E show output signal waveforms of the D flip-flops 501, 502, and 503, respectively, and FIG. 3F shows output signal waveforms sent to the serial data read clock input terminal 330 via the NOR gate 504. It is a thing. When the level of the transmission / reception switching terminal 80 is "1" in the transmission state, the signal waveform of FIG. 1G and the signal waveform of FIG. 3E are the same.

Now, when the level of the transmission / reception switching terminal 80 in FIG. 1 is "1", the output level of the NAND gate 1 is the D flip-flop 5 which constitutes the timing signal generating circuit 500.
Depending on the output of 03, as shown in FIG. 3E, after the leading edge of the clock signal for transmission / reception applied to the serial clock terminal 10 arrives, it shifts to '1' and trailing '0' after the edge (trailing edge) arrives
Return to. On the other hand, when the output level of the NAND gate 1 shifts to "1", the incrementer 150 becomes active, and the incrementer 150 sends out to the random access memory 300 data larger by 1 than the count value of the down counter 100 at that time. The serial data read clock input terminal 330 is supplied with a read clock signal as shown in FIG. 3F while the output level of the NAND gate 1 is shifting to "1". Therefore, in the device shown in FIG. 1, even when the level of the transmission / reception switching terminal 80 is "1", that is, in the serial data transmission mode, the leading edge of the clock signal applied to the serial clock terminal 10 is Random access memory immediately after arrival
After the data stored in 300 is transmitted, the down counter 100 counts down to prepare for the selection of the next bit data of the random access memory 300, but immediately after the trailing edge of the same clock signal arrives. Then, the previous bit position is selected by the incrementer 150, and then the read clock signal is supplied from the timing signal generation circuit 500 to the serial data read clock input terminal 330. as a result,
After transmitting data to each bit position of the random access memory 300, the data of the serial input / output terminal 20 is read at the trailing edge of the transmission clock applied to the serial clock terminal 10. Such an echo back function of the transmission data can be used not only for confirming the collision of the transmission operation when many transmission / reception blocks are connected to the same serial data line, but also for determining the number of bits in one frame. Complex communications such as assigning to transmission and assigning the rest to reception can be easily performed.

As described above, the timing signal generation circuit 500 is used to set the timing of reading serial data from the serial input / output terminal 20 to the random access memory 300.

To receive normal serial data, set the state of the down counter 100 to [111
1] and the D flip-flop 4 is reset and the level of the transmission / reception switching terminal 80 is shifted to '0' in the receiving state, the incrementer 150 is always in the active state and the serial clock terminal 10 is for receiving. When the clock signal is supplied, the count value of the down counter 100 changes each time its leading edge arrives, and the bit position of the data written from the serial input / output terminal 20 to the random access memory 300 also changes accordingly. Timing signal generation circuit that is switched
When the read clock is supplied from 500 to the serial data read clock input terminal 330, the received data is written in the bit position selected. Down counter
When the count value of 100 becomes [1111], the interrupt request signal is sent to the interrupt output terminal 31 at the trailing edge of the clock signal supplied to the serial clock terminal 10 as in the case of transmission. As a result, the microprocessor starts an interrupt processing routine, which causes the random access memory 30 to operate.
Parallel data may be read from 0 via the data bus 200.

In this way, the serial data transmitting / receiving apparatus shown in FIG. 1 can transmit / receive serial data in the same manner as the conventional apparatus. However, as can be seen from the configuration of FIG. In contrast to this, both a counter and a shift counter are required, whereas the serial data transmitting / receiving apparatus of the present invention transmits / receives serial data of 16 or 8 bits per frame by the down counter 100 and incrementer 150 of only 4 bits. can do. Further, in the conventional device, since the contents of the shift register change when the first leading edge of the serial clock arrives during transmission, the data itself is shifted by one bit when the transmission data is set in the shift register. In the serial data transmitting / receiving apparatus of the present invention, switching between transmission and reception is performed depending on whether the incrementer 150 is activated or not. Therefore, the bit positions of the transmission data and the reception data can be easily set. Correspondence can be taken. Along with that, the circuit configuration is simplified and the proportion occupied by the random logic circuit is reduced, so that the layout can be easily performed when constructing a one-chip LSI, and it is also suitable for the inspection of the LSI in the production process.
Further, since the transmission / reception data is directly transmitted from the random access memory 300 at the time of transmission and is directly read at the time of reception without passing through the shift register, it is possible to process a large amount of data at higher speed. That is, in the embodiment shown in FIG. 1, since the total number of bits of the random access memory 300 is 16 bits, if one frame of data to be transmitted / received has a structure of 8 bits, the random access memory 300 has a double buffer function. However, when one frame transmits / receives 16-bit data, it does not have a double buffer function, so parallel data is exchanged with the data bus 200 every time one frame is transmitted / received. Need to give and receive. However, by increasing the number of bits of the down counter 100 and the random access memory 300, a multi-stage buffer configuration can be easily obtained, which allows more information to be handled at once and advanced communication can be performed.

Note that FIG. 4 is a circuit connection diagram showing a specific configuration example of the random access memory 300, and a unit memory cell is composed of an inverter 301 and a three-state inverter 302. For example, if the level (CK) of the serial data read clock input terminal 330 of FIG. 1 is '1', the output of the down counter 100 is supplied to the AND gate 30.
If the level of 3 is also '1', the 3-state inverter 3
04 becomes active and the data (SDA) of serial input / output terminal 20 is written to the memory cell via the SI terminal in FIG. If the level of the transmission / reception switching terminal 80 is "1" in the transmission state, the output side of the 3-state inverter 9 in FIG. 1 is connected to the serial input / output terminal 20, and thus the reading of the serial clock signal is performed. At the edge, the output of the memory cell at the bit position selected by the decoder including the AND gate 303 is sent to the serial input / output terminal 20 via the SO terminal in FIG. Further, when writing parallel data, the 3-state buffer 305 becomes active, and when reading parallel data, the 3-state inverter 306 becomes active.

As is apparent from the above description, the serial data transmission / reception apparatus of the present invention has a counter to which a transmission / reception clock is supplied (in the embodiment, the down counter 100 constitutes this counter, but of course, the up counter). The output of the counter is supplied and the incrementing or decrementing means for incrementing or decrementing the output (in the embodiment, the incrementing means by the incrementer 150 for incrementing the count output of the down counter 100 is However, if the counter is an up-counter, decrement means for decrementing the count output of the up-counter is used instead of the increment means), and either before transmission or reception. The parallel data is transferred between the control means (which is constituted by the NAND gate 1 in the embodiment) for activating the increment means or the decrement means and the data bus 200, and the increment means or the decrement means. Memory means for transmitting / receiving the bit position data decoded by the output of the means to / from the serial input / output terminal (in the embodiment, the random access memory 300 is used, but a latch type memory may be used). In addition to being able to realize a communication device with a simple configuration, by applying the present invention, it is also possible to obtain a communication device capable of relatively advanced processing, It has a great effect.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a serial data transmitting / receiving apparatus according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts of main parts of FIG. 1, and FIG. 4 is a configuration example of a random access memory. It is a circuit connection diagram. 1 ... NAND gate, 20 ... Serial input / output terminal, 100 ...
… Down counter, 150 …… Incrementer, 200 …… Data bus, 300 …… Random access memory, 1 …… NAN
D gate, 20 ... serial input / output terminal, 100 ... down counter, 150 ... incrementer, 200 ... data bus,
300 ... Random access memory.

Claims (2)

[Claims] 1. A counter to which a transmission / reception clock is supplied,
The output of the counter is supplied and increment means or decrement means for incrementing or decrementing the output, control means for activating the increment means or the decrement means at either transmission or reception, and parallel data A serial data transmission / reception device comprising memory means for exchanging data at a bit position, which is transmitted / received to / from a data bus and decoded by the output of the increment means or the decrement means, to / from a serial input / output terminal. 2. A read / write switching terminal and a block select terminal, wherein when the block select terminal is activated, parallel data is transferred to a data bus according to the level applied to the read / write switching terminal. The serial data transmission / reception apparatus according to claim 1, further comprising a random access memory that is exchanged between the serial data transmission / reception devices.