JPH0736565B2 - Serial data receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data receiving apparatus, and provides a receiving apparatus which has an extremely simple structure and is compatible with advanced communication, and is particularly suitable for a microprocessor. It realizes such a device.

2. Description of the Related Art Conventionally, a serial data communication device that has been frequently used in a one-chip microprocessor or the like is composed of a shift register, a shift counter, and a buffer register, and a typical example thereof is Japanese Patent Publication No. 60-58482. (Hereinafter abbreviated as Document 1).

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, since the device as described in the above-mentioned document 1 is mainly composed of the random logic circuit, the number of wirings between the respective circuit blocks is large and the circuit structure becomes complicated. However, if a large amount of data is to be communicated at one time, most of the processing must rely on software, and the circuit configuration must be changed each time for higher-level communication or high-speed data transfer. there were.

Means for Solving the Problems In order to solve the above-mentioned problems, the serial data receiving apparatus of the present invention has a counter for counting a reception clock corresponding to the number of data bits of one frame, and Memory means for transmitting parallel data to the data bus having a bit width and a block select terminal when the block select terminal is activated, and transferring the data at the bit position decoded by the output of the counter from the serial input terminal Is equipped with.

Operation According to the present invention, with the above-described configuration, it is possible to realize a serial data receiving device with an extremely simple configuration.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a case in which a serial data receiving apparatus according to an embodiment of the present invention is applied to a microprocessor. A 3-bit down counter to which a receive clock is supplied via a serial clock terminal 10. 100
And the parallel data is the microprocessor data bus 200
The random access memory 300 supplied from the serial input terminal 20 constitutes the main part of the data of the bit position which is sent to the serial input terminal 20 and is decoded by the output of the counter 100 and supplied via the counter bus 150. Also, the output of each bit of the counter 100 is supplied to the D terminal of the D flip-flop 400, and the output signal of the D flip-flop 400 is an interrupt request signal which is transmitted to the microprocessor via the AND gate 410 and the interrupt output terminal 30. Is generated. That is, the D flip-flop 400 and the AND gate 410 form an interrupt signal generation circuit that generates an interrupt request signal when the counting operation for one frame of the counter is completed. Further, the reset terminal 40 and the clear terminal 50 are connected to the non-latch type output port of the microprocessor to supply a reset signal by software, and the interrupt disable terminal 60 is connected to the latch type output port of the microprocessor to interrupt by software. Used for control. The block select terminal 70 connected to the random access memory 300 is connected to the random access memory 300.
A select signal for activating the parallel output section of is activated.

The operation of the receiver configured as described above will be described based on the timing charts of the main parts shown in the configuration diagram of FIG. 1 and FIG.

First, FIG. 2A shows the waveform of the clock signal supplied to the serial clock terminal 10, and FIGS. 2B, C and D show the output signal waveform of each bit of the counter 100. Yes, FIG. 2, E, F, G, H, I, J, K, L all show output signal waveforms of the bit position switching decoder configured inside the random access memory 300.
FIG. 2M shows how the serial data sent to the serial input terminal 20 changes.

In order to receive serial data by the device shown in FIG. 1, if the D flip-flop 400 with the counter 100 is reset in advance, the serial clock terminal 10
When the clock signal for reception is supplied to, the count value of the counter 100 changes to [111], [110] ... [001], [000] each time its leading edge arrives. As shown in FIGS. 2E to 2L, the bit position of the random access memory 300 that takes in data from the serial input terminal 20 is also switched. Counter 100
When the count value of becomes [000], the D flip-flop 4
The level of the D terminal of 00 shifts to "1", the output level of the D flip-flop 400 shifts to "1" at the trailing edge of the clock signal supplied to the serial clock terminal 10, and the interrupt output terminal 30 is interrupted. A request signal is sent. As a result, the microprocessor may start an interrupt processing routine and read parallel data from the random access memory 300 via the data bus 200 by this interrupt processing routine.

In this way, the serial data receiving apparatus shown in FIG. 1 can receive serial data in the same manner as the conventional apparatus, but as can be seen from the configuration of FIG. In contrast, a shift register and a shift counter are both required, whereas the serial data receiving device of the present invention requires a shift register.
Along with that, the circuit configuration is simplified and the proportion occupied by the random logic circuit is reduced.
Layout is easy when configuring LSI, and it is also suitable for LSI inspection in the production process. Furthermore, since the received data is directly read from the serial input terminal 20 without passing through the shift register, a large amount of data can be processed at higher speed. That is, by increasing the address of the random access memory 300 to form a multi-stage buffer structure and selecting the address by the upper bits of the counter 100 having the increased number of bits, more information can be handled at once. This enables advanced communication.

3 is a circuit connection diagram showing a specific configuration example of the random access memory 300. The unit memory cell is composed of an inverter 301 and a 3-state inverter 302, and the AND gate 303 is a counter 100 of FIG. It constitutes a part of a decoder which decodes the count value of the bit into the corresponding bit position. For example, the serial clock terminal of FIG.
When the level (SCK) of 10 is '0', the output level of the inverter 350 becomes '1', and if the output level of the AND gate 303 is also '1', the 3-state inverter 304 becomes active. Data of serial input terminal 20 (SDA)
Is written in the memory cell. Further, when reading parallel data, the 3-state inverter 305 becomes active.

As is apparent from the above description, the serial data receiving apparatus of the present invention has the counter 100 that counts the reception clock corresponding to the number of data bits of one frame, and the bit width that is equal to or more than the number of data bits. Data bus 200
When the block select terminal 70 is activated, parallel data is sent to the data bus, and the data at the bit position decoded by the output of the counter is transferred from the serial input terminal (in the embodiment, a memory means). The random access memory 300 is used, but it may be a latch type memory). It is possible to realize a serial data receiving device with an extremely simple configuration, By applying the above, it is possible to obtain a communication device capable of performing high-level processing relatively easily, and a great effect is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart of main parts of FIG. 1, and FIG. 3 is a circuit connection diagram showing a configuration example of a random access memory. Is. 20 …… Serial input terminal, 100 …… Counter, 200 …… Data bus, 300 …… Random access memory.

Claims (2)

[Claims] 1. A counter that counts a reception clock corresponding to the number of data bits in one frame, a data bus having a bit width equal to or greater than the number of data bits, and a data bus when the block select terminal is activated. A serial data receiving device comprising memory means for transmitting parallel data and transferring data at a bit position decoded by the output of the counter from a serial input terminal. 2. A counter for counting a reception clock corresponding to the number of data bits of one frame, a data bus having a bit width equal to or greater than the number of data bits, and a data bus for the data bus when a block select terminal is activated. The parallel data is sent out, the memory means to which the data at the bit position decoded by the output of the counter is transferred from the serial input terminal, and the interrupt request signal is generated when the counting operation for one frame of the counter is completed. A serial data receiving device including an interrupt signal generating circuit.