JPH0693165B2 - Matrix type display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a matrix type display device using a switch / capacitor array, and more particularly to a device for color display.

[Prior Art] Recently, as a small-sized and high-density display device for a pocket TV or the like, a liquid crystal display device or a low-speed electron beam excitation phosphor is being developed. In these display devices, as a means for controlling the brightness of each pixel,
Switch / capacitor arrays made using semiconductor integrated circuit technology are used.

FIG. 1 is an equivalent circuit diagram for explaining a configuration example of a switch / capacitor array, and (1) is a MOS as a switch.
FET, (2) is MOS type capacitor as capacitor, (3)
Is a display electrode that defines a pixel and is electrically connected to the source or drain of the MOS FET and one end of the capacitor. The gates of the MOS-type FETs are commonly connected row by row to provide address lines Y ₁ , Y ₂ ... Y _n , and the drains or sources are commonly connected column by column and are data lines X ₁ , X ₂ ... X _m. Is provided. The MOS type FET (1), the capacitor (2), the address and the data line are formed on a semiconductor substrate, for example, and a display electrode (3) is further formed thereon with an interlayer insulating film interposed therebetween.

FIG. 2 is a block diagram for explaining a liquid crystal display device as an example of a display device using the switch / capacitor array of FIG. 1, in which (3) is a display electrode and (4) is a switch / capacitor array. For example, a silicon substrate, (5) an interlayer insulating film, (6) a reinforcing substrate, (7) a counter electrode made of a transparent conductive film, (8) a transparent insulating substrate, (9) a spacer and a sealing portion. , (10) are liquid crystal substances.

The liquid crystal display device shown in FIG. 2 operates as follows.
That is, in FIG. 1, address lines Y ₁ , Y ₂ ... Y _n
Are sequentially scanned and driven by the scanning signal from the scanning drive circuit, and the FET (1) is brought into a conductive state sequentially for a period of T _F / n for each line. Here, T _F is a frame scanning period. When data, for example, m parallel image signal voltage is supplied to the data lines X ₁ , X _2, ... X _m in synchronization with the above scanning, the signal voltage is sequentially written into the capacitor (2) line by line, and the frame scanning period (T _F ) held over. The held signal voltage is guided to the display electrode (3), and the liquid crystal layer sandwiched between the counter electrode (7) and the counter electrode (7) is excited in accordance with the signal voltage to display an image.

[Problems of Prior Art] When color display is performed using this type of device, in the case of using liquid crystal, a method of combining three primary color filters corresponding to each pixel, a method of coloring the display electrode surface into three primary colors, and the like It is conceivable that a slow electron-excited phosphor is associated with each pixel. However, in color display, one pixel must be composed of three primary color pixels, so three times as many pixels as in monochrome display are required. Therefore, for example, the number of data lines of the switch / capacitor array is tripled, and the connection with the driving circuit becomes very troublesome.

[Object of the Invention] It is an object of the present invention to provide a matrix type display device which solves the above-mentioned problem in connection with a drive circuit.

SUMMARY OF THE INVENTION According to the present invention, 3n 2-input gate / buffer circuits equal to the number of address lines (3n) of a switch / capacitor array are provided integrally with the array, and the outputs of the circuits and the address lines are respectively provided. One of the inputs of the 3n circuits is commonly connected by three adjacent circuits to form a first group of n terminals, and the other input is commonly connected every two circuits. A second terminal group, the first and second terminals
The n-phase and 3-phase pulses are supplied to the respective terminal groups, and color sequential m line simultaneous signals are supplied to the data lines (m lines) of the array. As a result, the number of data lines can be made the same as in black and white display, and the number of connecting lines between data lines and drive circuit is 1/3
Can be reduced to In this case, the number of address lines is tripled, but since the gate / buffer circuit is integrally provided, the number of lines connected to the drive circuit is 3 as compared with the case of monochrome display.
The number of books (the above-mentioned second terminal group) is only increased.

[Embodiment of the Invention] FIG. 3 is an equivalent circuit diagram for explaining a configuration of a switch / capacitor array in a device of an embodiment. (1
1), (12), (13) are, for example, MOS type FETs as switching elements for the three primary color pixels, (21), (22), (23)
Is, for example, MO as a signal storage element for each of the three primary color pixels
S-type capacitors, (31), (32), (33) each 3
These are display electrodes that define primary color pixels, and these constitute one pixel in color display. Y ₁₁ , Y ₁₂ , Y ₁₃ , Y ₂₁ , Y
₂₂ , Y ₂₃ ... Y _n1 , Y _n2 , Y _n3 are address lines,
X ₁ , X ₂ ... X _m are data lines. (14) is a 3n 2-input gate / buffer circuit provided integrally with the array, for example, a 2-input AND gate / buffer, the outputs of which are connected to the address lines, respectively. One input of this circuit (14) is commonly connected by three adjacent circuits, and n first terminal groups Y ₁ , Y ₂ ... Y _n are provided, and the other input is every two. Of three second terminal groups U, V, which are commonly connected to each circuit
W is provided.

Figure 4 is a waveform diagram for explaining the operation of the switch / capacitor array of Figure _{3, y 1, y 2, ...} y n the first Figure 3
N-phase pulse, u, v, w supplied to the terminal groups Y ₁ , Y ₂ ... Y _n of
Is a three-phase pulse supplied to the second terminal group U, V, W. When such a pulse is input to 3n 2-input AND / buffer (14), the output of FIG.
y ₁₁ , y ₁₂ , y ₁₃ , y ₂₁ …… y 3n-phase pulses as shown in y ₃ can be obtained. These pulses are on address line Y ₁₁ ,
It is supplied to Y ₁₂ , Y ₁₃ , Y ₂₁ ... Y _n3 , respectively, and the address lines are scanned and driven. Therefore, the FETs (11), (12), and (13), which are respectively m in number along the address line, are brought into a conductive state for each period sequentially for T _F / 3n. Here, T _F is a frame scanning period.

When, for example, color-sequential m-line simultaneous signals as shown in FIG. 4 Xi are supplied to the data lines X ₁ , X _2, ... X _m in synchronization with the above scanning, the color signal voltages are respectively m along the address lines. The capacitors (21), (22), and (23) are sequentially written and held for the frame scanning period T _F.
At the timing of FIG. 4, the red (R) signal is written to the capacitor (21), the green (G) signal is written to the capacitor (22), and the blue (B) signal is written to the capacitor (23).
Retained. These held three-primary-color signal voltages are guided to the display electrodes (31), (32), and (33) of the three-primary-color pixels, respectively, and the optical characteristics of the liquid crystal or the light emission of the phosphor are changed according to the three-primary-color signal voltages. It is possible to control and display characters, figures, images in color.

The switch / capacitor array shown in FIG. 3 can be formed on a semiconductor substrate such as a silicon substrate using a normal IC technique, or can be formed on a transparent insulating substrate such as a glass plate using a thin film IC technique. it can.

As described above, according to the present invention, in a matrix type display device using a switch / capacitor array which is driven and controlled by a plurality of address lines and data lines, on a substrate on which the array is formed. By integrally providing the same number of gate / buffer circuits as the number of address lines, and supplying the scanning pulse to the address lines through this circuit and supplying the color line sequential signals to the data lines simultaneously, Even if the number of pixels in color display is three times as large as that in black and white display, the number of connecting lines with the drive circuit can be substantially the same as in black and white display without increasing the number of data lines.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram for explaining a configuration example of a switch / capacitor array, and FIG. 2 is a configuration diagram for explaining a liquid crystal display device as an example of a matrix type display device using the switch / capacitor array. FIG. 3 is an equivalent circuit diagram for explaining the configuration of the switch / capacitor array in the device of one embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of FIG. (11), (12), (13) ... FET, (21), (22), (2
3)… Capacitor, (31), (32), (33)… Display electrode, (14)… 2-input AN
D gate / buffer, Y ₁ , Y ₂ ... Y _n ... first terminal group, U, V, W ... second terminal group, Y ₁₁ , Y ₁₂ , Y ₁₃ , Y ₂₁ , Y ₂₂ , Y ₂₃ ... Y _n1 , Y _n2 , Y _n3 ... address lines, X ₁ , X ₂ ... X _m ... data lines.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/66 B 9068-5C

Claims (1)

[Claims] 1. A matrix type display device using a switch / capacitor array driven by a plurality of 3n address lines and m data lines, respectively.
3n 2-input gate / buffer circuits are provided integrally with the array to connect the outputs of the circuits and the address lines, respectively, and one input of the 3n circuits is commonly connected to three adjacent circuits. To make a group of n first terminals, and the other input is commonly connected to every second circuit and three second terminals.
Terminal groups, and n-phase and 3-phase pulses are supplied to the first and second terminal groups, respectively, and color-sequential m-line simultaneous signals are supplied to the data lines. Matrix type display device.