JPH0693566B2 - Microwave synthesis circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microwave synthesizing circuit device for power synthesizing an input signal between a plurality of microwave lines. Hereinafter, the microwave line is a line for transmitting a signal having a frequency of approximately 1 GHz or higher, and refers to a coplanar line, a coplanar line such as a slot line, and a microstrip line.

[Prior Art] FIG. 7 (A) shows a composite circuit between coplanar lines (hereinafter referred to as a first circuit).
The conventional example of. ) Is a plan view and FIG. 7 (B) is a vertical cross-sectional view taken along the line AA ′ in FIG. 7 (A). 7 (A) and (B), T-shaped strip conductors 3, 5, 8 are integrally formed on the semiconductor substrate 1, and ground conductors 2a, 2b and 6 are respectively formed in the strip conductors. 3,5,8
Are formed on the semiconductor substrate 1 on both sides of the semiconductor substrate 1 with a predetermined distance from the strip conductors 3, 5, and 8. Further, in the synthesizing portion of the synthesizing circuit, between the ground conductors 2a and 2b, between the ground conductors 2a and 6,
In addition, the ground conductors 2b and 6 are connected to each other via connecting bridge conductors 10a, 10b and 10c. The connecting bridge conductors 10a, 10b, 10c are formed on the semiconductor substrate 1 and the strip conductors 3, 5, 8 with the insulating layer 11 interposed therebetween. Here, the strip conductor 3 and the ground conductors 2a and 2b, the strip conductor 5 and the ground conductors 2a and 6, and the strip conductor 8 and the ground conductors 2b and 6 constitute known coplanar lines 4, 7 and 9, respectively. In the synthesizing circuit configured as described above, for example, the signals input to the coplanar lines 7 and 9 are power-combined into one signal by the synthesizing circuit, and then the combined signals are combined.
Is output to.

FIG. 8 is a plan view of a Wilkinson type combining circuit between slot lines (hereinafter referred to as a second conventional example). 8th
In the figure, the conductors 60a and 60b are separated from each other by a predetermined distance on the left side of the semiconductor substrate 1 and a predetermined distance from the conductor 64 in the central portion of the semiconductor substrate 1, and further on the right side of the semiconductor substrate 1 in the drawing. Are formed at a predetermined distance from the conductor 60c. The plane shape of the conductor 64 is a pentagon of a substantially home base shape, the left end portion 64b of the conductor 64 in the figure is connected to the conductor 60c via the resistor 65, and the vertex 64a of the conductor 64 to the center of the resistor 65. The distance to the part is λg / 4. Where λg
Is the guide wavelength. In addition, the conductors 60a, 60b, the conductors 60a, 60c, and the conductors 60b, 60c are used to form the slot lines 61, 62, 63, respectively.
Are configured. In the combining circuit configured as described above, for example, the signals input to the slot lines 62 and 63 are power-combined into one signal at the apex 64a of the conductor 64 and output to the slot line 61.

[Problems to be Solved by the Invention] Since the above-described first conventional combination circuit is a reciprocal circuit, the input / output lines are not electrically separated from each other, and the circuit connected to the output coplanar line 4 is not provided. If there is a reflection from, the reflected wave will appear on the input coplanar lines 7 and 9 as it is. When this reflected wave is not desirable, there is a problem that it is necessary to further provide an isolator to remove this reflected wave. Further, in this circuit, if the characteristic impedance of the output coplanar line 4 is Z, the characteristic impedances of the input coplanar lines 7 and 9 matching this are
There is also a problem in that a matching circuit is further required to connect the coplanar line having the characteristic impedance Z to the input side, for example, and the overall combining circuit becomes large.

Further, in the above-mentioned second conventional combination circuit, by appropriately selecting the resistance value of the resistor 65, all the characteristic impedances of the input / output slot lines 61 to 63 can be set to the same, Impedance matching can be performed between the input and output slot lines. However,
This combined circuit is also a reciprocal circuit like the circuit of the first conventional example, and the input lines 62 and 63 are separated from each other, but the input / output lines are not separated from each other.
If there is a reflection from the circuit connected to and 63, the reflected wave will appear on the output slot line 61 as it is. When this reflected wave is not desirable, there is a problem that it is necessary to further provide an isolator to remove this reflected wave. Also, in this second conventional example, λg / 4
However, there is a problem in that it is difficult to reduce the size of the line because it requires the length of the line.

The object of the present invention is to solve the above problems and to synthesize an input signal with good electrical isolation between the input and output microwave lines with a simple circuit without using an isolator, and
An object of the present invention is to provide a compact microwave synthesis circuit in which impedance matching between input and output microwave lines is achieved.

[Means for Solving Problems] The present invention relates to a first field-effect transistor having a grounded gate in which a plurality of source electrodes are connected to a plurality of input microwave lines, respectively, and the first field-effect transistor. And a drain-grounded second field-effect transistor whose source electrode is connected to the output microwave line and whose drain electrode is connected to the gate electrode.

[Operation] With the configuration described above, a first grounded field effect transistor having a plurality of source electrodes,
A second field-effect transistor whose drain is grounded is cascaded. Therefore, the microwave signals input to the plurality of input microwave lines are input to the first field effect transistor, power is combined into one microwave signal, and processing such as amplification and impedance conversion is performed. Then, the combined microwave signal is output to the second field effect transistor. The microwave signal input to the second field effect transistor is subjected to processing such as amplification and impedance conversion, and then output to the output microwave line.

Here, the first field effect transistor and the second field effect transistor
In the field effect transistor of (1), since the plurality of source electrodes and the drain electrodes, the plurality of gate electrodes, and the gate electrodes and the source electrodes are electrically isolated, respectively, And the output microwave line, and between the plurality of input microwave lines are electrically separated. In addition, the first and second
Since the field effect transistor has the impedance conversion function as described above, impedance matching can be achieved between the plurality of input microwave lines and the output microwave lines.

[Embodiment] Basic Circuit FIG. 1 is a circuit diagram of a basic circuit of a microwave synthesizing circuit using a field effect transistor (hereinafter referred to as FET) according to an embodiment of the present invention.

In FIG. ₁ , the first having the characteristic impedance Zo 1
Input microwave line 23 is connected to the first source electrode of the gate-grounded FET 21, and the second input microwave line 24 having a characteristic impedance Zo ₂ is connected to the second source electrode of the FET 21. The first and second drain electrodes of the FET 21 are connected together and to the gate electrode of a drain-grounded FET 22 having a transconductance gm ₃ . FET22
The source electrode of is connected to the output microwave line 25 having a characteristic impedance Zo ₃ .

Here, it has two source electrodes and two gate electrodes.
The FET 21 is composed of a first FET section Q ₁ having a first gate electrode and a first source electrode, and a second FET section Q ₂ having a second gate electrode and a second source electrode. And the second F
The ET sections Q ₁ and Q ₂ have mutual conductances gm ₁ and gm ₂ , respectively. The first and second FET parts Q ₁ and Q ₂ may be formed on the same operation layer or may be formed on different operation layers.

Considering these FET21 and FET22 as ideal FETs that can be described only by mutual conductance, S of the circuit of FIG.
The parameters are as follows: The input microwave lines 23 and 24 are used as the first and second terminals, respectively, and the output microwave line 25 is used as the third terminal, and S parameter subscripts are given.

S ₁₃ = S ₂₃ = 0 (4) Here, S ₁₁ and S ₂₂ are the input end reflection coefficients of the input microwave lines 23 and 24, respectively, and S ₃₃ is the output microwave line 25.
Is the reflection coefficient at the output end on the side.

Furthermore, if the gate widths of the gate-grounded FET 21 and the drain-grounded FET 22 are set so that gm ₁ Zo ₁ = gm ₂ Zo ₂ = gm ₃ Zo ₃ = 1, the above S-parameters are as follows. .

S ₁₁ = S ₂₂ = S ₃₃ = 0 (5) In this way, the gate-grounded FET 21 and the drain-grounded FET 22 set to gm ₁ Zo ₁ = gm ₂ Zo ₂ = gm ₃ Zo ₃ = 1 are cascaded. By connecting, there are the following effects.

(1) Since the input end reflection coefficients S ₁₁ and S ₂₂ and the output end reflection coefficient S ₃₃ are zero, impedance matching between the input and output lines can be achieved.

(2) Since the reverse transfer coefficients S ₁₃ and S ₂₃ are zero, the input / output lines can be electrically separated.

Therefore, this synthesis circuit uses two input microwave lines 2
The input signals can be combined in a state where the impedances between the output lines 3 and 24 and the output microwave line 25 are matched and the input and output lines are electrically separated. Also, FE
Since the first source electrode and the second source electrode of T21 are electrically separated, the first and second input microwave lines 23, 24 connected to each electrode are electrically separated. be able to. Furthermore, the spacing between the input / output lines 23, 24 and 25 is
Unlike the second conventional example, the length of 1/4 wavelength is not required, and the FET
By miniaturizing the circuit constituted by 21,22, the microwave synthesizing circuit can be miniaturized as compared with the second conventional example.

FIG. 2 is a circuit diagram of a microwave synthesis circuit provided with bias terminals Tb ₁ and Tb ₂ for FETs 21 and 22. The circuit of FIG. 2 differs from the basic circuit of FIG. 1 in that (1) the coupling capacitor Cc is connected between the first and second drain electrodes of the FET 21 and the gate electrode of the FET 22, (2) the first FET21 and the second drain electrode is connected to ground via a series circuit resistor Rb and a DC blocking capacitor Cb ₁ bias setting, the (3) FET 22 gain adjusting resistor R is the gate electrode of the (4) The drain electrode of FET22 is a DC blocking capacitor Cb ₂
Bias terminal T is connected between the resistor Rb and capacitor Cb _{1 and} between the drain electrode of FET 22 and capacitor Cb ₂ respectively.
b ₁ and Tb ₂ are provided.

In the combining circuit configured as above, the bias terminal
By applying a DC bias voltage to Tb ₁ and Tb ₂ ,
Bias settings of 21 and 22 can be made. Further, by changing the resistance value of the resistor R, the gain of the signal output from the input lines 23, 24 to the output line 25 can be adjusted.

First Embodiment FIG. 3 (A) is a plan view of a microwave monolithic integrated circuit of a composite circuit between the input coplanar lines 7 and 9 and the output coplanar line 4 according to the first embodiment of the present invention. 3 (B) is a vertical sectional view taken along the line BB 'of FIG. 3 (A), and FIG. 3 (C) is a vertical sectional view taken along the line CC' of FIG. 3 (A). FIG. 3D is a vertical sectional view taken along the line DD ′ of FIG.
In FIGS. 3A to 3D, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

In FIGS. 3A to 3D, a Schottky gate type field effect transistor (hereinafter referred to as MESF) is formed at a substantially central position on the right side of the rectangular semi-insulating GaAs semiconductor substrate 1 in the figure.
It is called ET. ) 22 is formed on the upper surface of the semiconductor substrate 1, and impurity ions are implanted from the upper surface of the semiconductor substrate 1 to form the operating layer 17. The gate electrode 31 of the MESFET 22 is integrally formed with the conductor 33 at a substantially central position of the operating layer 17. Here, the planar shape of the gate electrode 31 is a rectangular shape having two sides of a long gate width w ₃ and a gate length g _{3 which} are parallel to the horizontal direction of the semiconductor substrate 1 in the figure. Further, the source electrode 32 and the drain electrode 30 are separated from the gate electrode 31 by a predetermined distance with the gate electrode 31 interposed therebetween, and the conductor 41 and the conductor of the output coplanar line 4 are respectively provided on the operating layer 17. It is formed integrally with 3. Here, the source electrode 32 and the drain electrode
Each planar shape of 30 is rectangular, and the sides of the electrodes 32, 30 in the longitudinal direction are parallel to the sides of the gate electrode 31 in the gate width w ₃ direction.

The gate electrode 31, the source electrode 32 and the drain electrode 30 which are formed on the operating layer 17 in the semiconductor substrate 1 by the known method as described above constitute the MESFET 22.

Further, after the impurity ions are implanted from the upper surface of the semiconductor substrate 1 at the position on the left side of the MESFET 23 in the figure to form the operating layer 13,
The two gate electrodes 15a and 15b are separated from the substantially central position of the operating layer 13 where the drain electrode 16 is formed by a predetermined distance, and are respectively grounded conductors 6 and 2a and grounded conductors 2 and 2b on the operating layer 13. Is formed integrally with. Here, the planar shapes of the gate electrodes 15a and 15b are the longitudinal gate width w ₁ and
It has a rectangular shape having sides of w ₂ and sides of gate lengths g ₁ and g ₂ , and each side of the gate widths w ₁ and w ₂ of the gate electrodes 15a and 15b is MES.
The gate width of the gate electrode 31 of the FET 22 is parallel to each side in the w ₁ and w ₂ directions. Further, the drain electrode 16 is integrally formed with the conductor 34 on the operating layer 13 with the gate electrodes 15a and 15b interposed therebetween and separated by a predetermined distance. The drain electrode 16 has a rectangular planar shape,
The side in the longitudinal direction of 16 is the gate width w of the gate electrodes 15a and 15b.
It is parallel to the ₁ and w ₂ sides. Further, the two source electrodes 14a, 14b are spaced apart from the gate electrodes 15a, 15b by a predetermined distance on the outside of the gate electrodes 15a, 15b, which are opposite to the side where the drain electrode 16 is formed. Action layer 1
The conductors 5 and 8 are integrally formed on the conductor 3. The source electrodes 14a, 14b have a rectangular planar shape, and the sides in the longitudinal direction of the source electrodes 14a, 14b are the gate electrodes 15a, 1b.
It is parallel to the side of the long gate width w ₁ and w _{2 of} 5b.

The MESFET 21 is constituted by the gate electrodes 15a and 15b, the drain electrode 16 and the source electrodes 14a and 14b which are formed on the operation layer 13 in the semiconductor substrate 1 by the known method as described above.

Conductors 5 and 8 are integrally formed with the source electrodes 14a and 14b, respectively, on the semiconductor substrate 1 above and below the source electrodes 14a and 14b of the MESFET 21 in the figure. Each planar shape of the conductors 5 and 8 is a substantially rectangular shape having widths in the gate width w ₁ and w ₂ directions and long sides in the gate lengths g ₁ and g ₂ directions, and the gate width w _{1 of the} conductors 5 and 8 is ,
Each side of w ₂ direction are respectively connected to the one side of the source electrode 14a, the gate width of 14b w _1, w ₂ directions.

On the semiconductor substrate 1 on the left side of each of the MESFET 21 and the conductors 5 and 8, a rectangular ground conductor 6 is separated from the conductors 5 and 8 by a predetermined distance l ₁ and l ₂ , respectively, and integrally with the gate electrodes 15a and 15b. It is formed.

The right side of the drain electrode 16 of the MESFET21 in the figure
A rectangular conductor 34 having the same width as the drain electrode 16 is formed on the semiconductor substrate 1 on the left side of FIG.
The rectangular conductor 90 is integrally formed with the drain electrode 16 and the conductor 34 while being integrally formed with the conductor 90. Here, one side of the drain electrode 16 in the gate length g ₁ , g ₂ direction is the conductor 3
It is connected to the side of the gate length g ₁ and g ₂ direction of 4. Therefore, the drain electrode 16 is connected to the conductor 90 via the conductor 34.

Semiconductor substrate 1 on the upper surface of the conductor 90 and on the right side of the conductor 90 in the figure
The conductor 33 is integrally formed on the gate electrode 31 via the insulating layer 42. Here, the planar shape of the conductor 33 is a substantially rectangular shape, and an end portion of the conductor 33 near the gate electrode 31 side extends to the gate electrode 31 and is connected to a side of the gate electrode 31 in the gate length g ₃ direction. . By the conductor 90, the insulating layer 42 and the conductor 33, a known metal-insulator-metal capacitor (hereinafter referred to as MIM
It is called a capacitor. ) 35, the MIM capacitor 35 is a coupling capacitor between the MESFETs 21 and 22.

The ground conductor 2a is separated from the conductor 5 by a distance l ₁ on the left side of the conductor 5 in the drawing on the upper side of the conductors 34, 90 and the MESFET 22 in each drawing, and the conductors 34, 90 and the source are also separated. Electrode 30
And a predetermined distance, and a distance l ₃ from the conductor 32,
It is formed integrally with the gate electrode 15a. Here, the end portion of the ground conductor 2a near the gate electrode 15a is connected to one side of the gate electrode 15a in the gate length g ₁ direction.

On the left side of the conductor 8 in the figure, and on the upper and lower sides of the conductors 34, 90 and 3 in the figure, the ground conductor 2b is spaced apart from the conductor 8 by a distance l _2.
Is separated from the conductors 34 and 90 by a predetermined distance and further separated from the conductor 3 by a distance l ₃ , and is integrally formed with the gate electrode 15b. Here, the gate electrode 15b of the ground conductor 2b
The end portion near the side is connected to one side of the gate electrode 15b in the gate length g ₂ direction. The conductor 5 and the ground conductors 6 and 2a, and the conductor 8 and the ground conductors 6 and 2b constitute input coplanar lines 7 and 9, respectively.

A bridge conductor 10a for connecting between the ground conductors 2a and 2b is provided on the conductor 34 between the portions of the ground conductors 2a and 2b near the MESFET21 side and close to each other and the semiconductor substrate 1 via an insulating layer.
It is formed.

A rectangular conductor 38 is integrally formed with the conductor 38a on the end portion of the ground conductor 2b near the conductor 90 with an insulating layer 46 interposed therebetween.
A part 38c of the upper end of the figure 8 is connected to the conductor 38a.
Here, the grounding conductor 2b, the insulating layer 46, and the conductor 38 form a DC blocking MIM capacitor 39 as described above. The bias terminal 40 is connected to the conductor 38 through the lead wire 40a.
Are connected.

The upper and lower ends 38c of the conductor 38a from the upper and lower end portions 90c of the conductor 90 in the drawing
Impurity ions are previously implanted into the semiconductor substrate 1 up to ac, whereby the resistor 36 is formed. Therefore, the conductor
90 is connected to the conductor 38 via the resistor 36 and the conductor 38a.

Also, from the right end 33c of the conductor 33 in the figure to the conductor 3 of the ground conductor 2a.
Impurity ions are previously implanted into the semiconductor substrate 1 up to the end portion 2ac in the vicinity of the third side, whereby the gain adjusting resistor 37 is formed. Therefore, the conductor 33 is grounded via the resistor 37.
Connected to 2a.

A conductor 41 is integrally formed with the drain electrode 30 on the ground conductor 2a on the upper side of the MESFET 22 in the figure with an insulating layer 80 interposed therebetween. Conductor 41
The plane shape is rectangular and the side of the conductor 41 in the gate width w ₃ direction is connected to the side of the drain electrode 30 in the gate width w ₃ direction. Here, the ground conductor 2a, the insulating layer 80, and the conductor 41 constitute the DC blocking MIM capacitor 43 in the same manner as described above, and the bias terminal 4 is connected to the conductor 41 via the lead wire 44a.
4 is connected.

The conductor 3 of the output coplanar line 4 is the drain electrode of the MESFET 22.
The drain electrode 32 is integrally formed on the upper and lower sides and the lower right side of the figure 32, and the conductor 3 has a dogleg shape with a predetermined width. Here, one side of the conductor 3 in the width direction is connected to the side of the drain electrode 32 in the gate width w ₃ direction.

A bridge conductor 10b for connecting between the ground conductors 2a and 2b is formed on the conductor 3 and the semiconductor substrate 1 at the end portion of the ground conductors 2a and 2b near the MESFET 22 via an insulating layer. The conductor 3 and the ground conductors 2a and 2b form an output coplanar line 4.

In addition, hereinafter, with the connecting bridge conductor 10a as a boundary, the MES
The left side of the semiconductor substrate 1 on which the FET 21 is formed in the figure is called the input side of the substrate 1, and the right side of the semiconductor substrate 1 on which the MESFET 22 is formed is called the output side of the substrate 1.

With the above configuration, the drain electrode 16 of the MESFET 21 is connected to the ground conductor 2b via the conductors 34 and 90, the resistor 36, the conductor 38a and the MIM capacitor 39 and grounded at high frequency, and the drain of the MESFET 22 is also provided. Electrode 16 is MIM capacitor 4
It is connected to the ground conductor 2a via 3 and is grounded at high frequency. This synthesis circuit corresponds to the circuit in Fig. 2, and the signals input to the input coplanar lines 7 and 9 are MESFET2 with the gate grounded.
1, MESF with drain grounded via MIM capacitor 35 for coupling
After being input to the ET22 and power-combined into one signal, the combined signal is output to the output coplanar line 4.

Here, the high frequency equivalent circuit of this circuit is as shown in FIG. 1, and the mutual conductances gm ₁ and gm of MESFET 21 and MESFET 22 are shown.
₂ , gm ₃ so that gm ₁ Zo ₁ = gm ₂ Zo ₂ = gm ₃ Zo ₃ = 1
By setting the gate widths w ₁ , w ₂ and w ₃ of the ESFETs 21 and 22, impedance matching can be achieved between the input and output lines. Further, the amplification degree of the synthesis circuit can be changed by changing the resistance value of the resistor 37. Source electrode of MESFET21
Since there is an electrical isolation action between 14a, 14b and the drain electrode 16 and between the gate electrode 31 and the source electrode 32 of the MESFET 22,
Input and output lines are electrically separated, and output coplanar line 4
Even if there is a reflection from the circuit connected to, the reflected wave does not appear on the input coplanar lines 7 and 9 as it is. Further, the input lines 7 and 9 are also separated by the electrical separation action of the MESFET 21. Therefore, it is not necessary to take measures such as an isolator for reflected waves, and a combined circuit of monolithic integrated circuits with good separation between input and output can be obtained. In this embodiment, the MESFET 21 and the MESFET 22 are arranged close to each other and are connected in a lumped constant manner, but it is also possible to connect them via a known microwave line. This also applies to the following examples.

Second Embodiment FIG. 4 is an input coplanar line according to the second embodiment of the present invention.
FIG. 4 is a plan view of a microwave monolithic integrated circuit of a combined circuit between 7, 9 and the output slot line 51, and FIG.
The same parts as those in the above drawings are designated by the same reference numerals.

This synthetic circuit is different from the first embodiment of FIG. 3A in that on the output side of the substrate 1, (1) the output coplanar line 4 replaces the output slot line 51 having the conductor 50 and the ground conductor 2a. (2) The ground conductor 2a is formed only on the right side of the conductor 8 in the figure, the upper and lower sides of the conductors 34 and 90 in the figure, and the left side of the conductor 50 in the figure.

In FIG. 4, the input side of the substrate 1 is formed in the same manner as in the first embodiment of FIG. 3 (A).

The MESFET 22 is formed at a substantially central position on the output side of the substrate 1 as in the first embodiment of FIG. 3 (A). Ground conductor 2a
Is formed in the same manner as in the first embodiment except that the conductor 50 is separated from the conductor 50 by an interval l ₄ , and the ground conductor 2b is formed so that the side near the conductor 50 side is cut in the gate length direction. Except for this, it is formed similarly to the first embodiment. further,
MIM capacitors 39,43, bias terminals 40,44, conductors 34,90,3
The 8a and the resistors 36 and 37 are formed in the same manner as in the first embodiment.

On the upper and lower sides and the lower right side of the MESFET 22 in the figure, the conductor 50 is separated from the ground conductor 2a by a distance l ₄ and the source electrode 32 is provided.
Is formed integrally with. The planar shape of the conductor 50 is the gate width w ₃
Parallel and a substantially trapezoidal shape having two sides parallel to each other, part of the gate width w ₃ side in the direction of the conductor 50 is connected to the gate width w ₃ direction of the source electrode 32. Further, the distance between the conductor 50 and the ground conductor 2b becomes wider as the distance from the MESFET 22 increases. Here, the conductor 50 and the ground conductor 2a constitute an output coplanar line 51.

With the above-described configuration, the drain electrode 16 of the MESFET 21 has the conductors 34 and 90, the resistor 36, the conductor 38a, and
The MESFET 22 is connected to the ground conductor 2b via the MIM capacitor 39 and grounded at a high frequency, and the drain electrode 30 of the MESFET 22 is connected to the ground conductor 2a via the MIM capacitor 43 and grounded at a high frequency. This combining circuit corresponds to the circuit of FIG. 2, and the signals input to the input coplanar lines 7 and 9 are input to the drain grounded MESFET 22 via the gate grounded MESFET 21 and the coupling MIM capacitor 35, respectively. After being power-combined with the signal, the combined signal is output to the output slot line 51. The high frequency equivalent circuit of this combined circuit is as shown in FIG. 1 as in the case of the first embodiment of FIG. 3 (A), and has the same operation and effect as the first embodiment.

Third Embodiment FIG. 5 shows an input slot line according to a third embodiment of the present invention.
FIG. 6 is a plan view of a microwave monolithic integrated circuit of a synthesis circuit between 53, 55 and the output coplanar line 4, and in FIG. 5, the same parts as those in the above drawings are denoted by the same reference numerals.

This combining circuit differs from the first embodiment of FIG. 3A in that the input coplanar lines 7 and 9 are replaced by the input slot lines 53 and 55 on the input side of the substrate 1. Hereinafter, the difference will be described in detail.

In FIG. 5, the output side of the substrate 1 is the first side of FIG. 3 (A).
It is formed in the same manner as in the above embodiment. Further, on the input side of the substrate 1, the MESFET 21 is formed similarly to the first embodiment.

The conductors 52 and 53 are respectively separated from the ground conductors 2a and 2b by the distances l ₅ and l ₆ on the upper and lower semiconductor substrates 1 of the MESFET 21 in the figure and the first and second source electrodes 14a and 14b, respectively. It is integrally formed. Each plane shape of the conductors 52, 53 is substantially rectangular, and each side of the conductors 52, 53 in the gate width w ₁ , w ₂ direction is each side of the source electrodes 14a, 14b in the gate width w ₁ , w ₂ direction. Connected with.
Further, in order to electrically isolate the input lines 53, 54 with a good degree of isolation, the distance between the sides of the conductors 52 and 53 facing each other is ME.
It gets wider as you move away from SFET21. Where the conductor 52
The ground conductor 2a, the conductor 54, and the ground conductor 2b constitute input coplanar lines 53 and 55, respectively.

This combined circuit corresponds to the circuit in FIG. 2, and the signals input to the input slot lines 53 and 55 are the gate grounded MESFET2.
1, MESF with drain grounded via MIM capacitor 35 for coupling
After being input to the ET22 and power-combined into one signal, the combined signal is output to the output coplanar line 4. Also,
The high frequency equivalent circuit of this combined circuit is as shown in FIG. 1 as in the case of the first embodiment of FIG. 3 (A), and has the same operation and effect as the first embodiment.

Fourth Embodiment FIG. 6 shows an input slot line according to a fourth embodiment of the present invention.
FIG. 7 is a plan view of a microwave monolithic integrated circuit of a combined circuit between 53, 55 and the output slot line 51, and in FIG. 6, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

In this synthesis circuit, the input side of the substrate 1 is formed in the same manner as in the third embodiment of FIG. 5, while the output side of the substrate 1 is formed in the same manner as in the second embodiment of FIG.

The synthesis circuit configured as described above corresponds to the circuit of FIG. 2, and each signal input to the input slot lines 53, 55 passes through the gate-grounded MESFET 21, the coupling MIM capacitor 35, and the drain-grounded MESFET 22. Input to the output slot line 51, and after the power is combined into one signal, the combined signal is output to the output slot line 51. The high frequency equivalent circuit of this combined circuit is as shown in FIG. 1 as in the first embodiment of FIG. 3 (A), and has the same operation and effect as those of the first embodiment.

Other Embodiments In the above embodiments, the MESFET is used as an active element for performing amplification and impedance matching, but the present invention is not limited to this, and another type of FET may be used. Further, although the slot line and the coplanar line are used as the input / output lines, the present invention is not limited to this, and other microwave lines such as a microstrip line may be used. Furthermore, I explained the case where the microwave line format on the synthetic input side is the same,
Not limited to this, the microwave line format on the combined input side may be different.

Although the number of the gate electrodes and the number of the source electrodes of the drain-grounded MESFET 21 are two in each of the above embodiments, the number is not limited to this and may be three or more. Furthermore, since the connecting portion between the MESFET 21 and the MESFET 22 has high impedance, a plurality of MESFETs 21 may be connected to this connecting portion to form a combining circuit that combines a large number of input signals.

As described above in detail, according to the present invention, the first field-effect transistor having a plurality of source electrodes, which is grounded in the gate, and the second field-effect transistor, which is grounded in the drain, are connected in series. It is possible to configure a microwave combining circuit device in which the microwave signals input to the plurality of input microwave lines are power-combined into one signal and the combined signal is output to the output microwave line.

Here, the first field effect transistor and the second field effect transistor
In the field effect transistor of (1), since the plurality of source electrodes and the drain electrodes, the plurality of source electrodes, and the gate electrodes and the source electrodes are electrically isolated from each other, The output microwave lines are electrically isolated from each other and the plurality of input microwave lines are electrically isolated from each other. Further, since the first field effect transistor and the second field effect transistor have an impedance conversion function, between the plurality of input microwave lines and the output microwave line,
Impedance matching can be achieved. Further, since the microwave synthesizing circuit device is composed of only two field effect transistors and does not require the length of 1/4 wavelength unlike the second conventional example, it is compared with the second conventional example. Can be miniaturized.

Therefore, it is possible to realize the microwave synthesizing circuit device in which the input and output and the plurality of outputs are electrically separated from each other, impedance matching between the input and output is achieved, and moreover, the size is smaller than that of the conventional example.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a basic circuit of a microwave synthesizing circuit using an FET according to an embodiment of the present invention, and FIG. 2 is a circuit of a microwave synthesizing circuit in which a bias terminal for FET is provided in the circuit of FIG. FIG. 3, FIG. 3 (A), FIG. 4, FIG. 5, and FIG. 6 are plan views of a microwave monolithic integrated circuit of a synthesis circuit of the first to fourth embodiments of the present invention, respectively. 3B is a vertical cross-sectional view taken along the line BB ′ of FIG. 3A, FIG. 3C is a vertical cross-sectional view taken along the line CC ′ of FIG. 3A, and FIG. Is a vertical cross-sectional view taken along the line D-D 'of FIG. 3 (A), FIG. 7 (A) is a plan view of a synthetic circuit of the first conventional example, and FIG. 7 (B) is FIG. 7 (A). FIG. 8 is a vertical cross-sectional view taken along the line AA ′ in FIG. 8 and FIG. 8 is a plan view of a Wilkinson-type synthesis circuit of a second conventional example. 1 ... Semiconductor substrate, 4,7,9 ... Coplanar line, 21,22 ... Schottky gate type field effect transistor (M
ESFET), 14a, 14b, 32 ... Source electrode, 15a, 15b, 31 ... Gate electrode, 16, 30 ... Drain electrode, 51, 53, 55 ... Slot line.

Front page continuation (72) Inventor Masayoshi Aikawa 5 Seiraya, Seika-cho, Soraku-gun, Kyoto Pref. 5 Mihiratani, ATR Optical Optical Communication Laboratory, Inc. (56) Reference JP-A-57-186347 (JP, A)

Claims (1)

[Claims] 1. A grounded first field effect transistor having a plurality of source electrodes connected to a plurality of input microwave lines, and a gate electrode connected to a drain electrode of the first field effect transistor. And a source-electrode second drain-grounded field-effect transistor connected to the output microwave line.