JPH069356B2 - Time division multiplex transmission device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a multi-pole signal transmission device used in a time division multiplex load control system.

[Background Art] FIG. 3 shows an example of use of this type of transmission apparatus. A polling signal including a start pulse, a terminal address, control data, etc. from a master A to a plurality of terminals T _{1 to} T _3. Is transmitted and the monitoring data is returned from the terminal device in the current mode within a fixed return period. The time division multiplex transmission apparatus according to the present invention is provided in the base unit A,
As shown in the figure (b) as the transmission signal, using a bipolar signal that oscillates in both positive and negative polarities has the advantage of improving various transmission characteristics, but on the other hand, a protection circuit against a short-circuit accident between signal lines There is a problem that it becomes complicated and the transmission output loss increases due to a switching element inserted in the output circuit for short-circuit protection.

[Object of the Invention] The present invention has been made in view of the above problems, and an object of the present invention is to control an output transistor itself without inserting a switching element for short circuit protection into an output circuit. Accordingly, it is an object of the present invention to provide a circuit configuration of a transmission device capable of short-circuit protection.

DISCLOSURE OF THE INVENTION According to the present invention, however, two totem pole circuits each including an NPN transistor and a PNP transistor are connected in parallel to form a bridge circuit, and each of a normal rotation type and an inverting type operational amplifier which receives a logic signal as input. By supplying a bipolar signal to the two circuit lines connected to the output terminals of both totem pole circuits by controlling the transistor pair of each totem pole circuit by the output, the bridge circuit is supplied. Means for detecting the power supply current, and by holding the outputs of both operational amplifiers at the H level when the power supply current exceeds a reference value, both NPN transistors are turned on, both PNP transistors are turned off, and an output loop To shut off both NPN transistors by holding the output of both operational amplifiers at the L level. , A means for turning on both PNP transistors to cut off the output loop,
The two operational amplifiers, which always output signals in opposite phases, are forcibly held at the same level in the event of an abnormality so that the loop of the output circuit formed by the bridge is cut off.

FIG. 1 shows an embodiment of the device of the present invention. In the figure, the two totem pole circuits Ta and Tb forming the bridge circuit are each an NPN transistor Q.
na, Qnb and PNP transistors Qpa, Qpb are connected in cascade, and the gates of the transistor pairs Qna, Qpa and Qnb, Qpb of each totem pole circuit Ta, Tb are connected in common to each other, and a non-inverting operational amplifier is provided. It is controlled by each output of OPa and the inverting operational amplifier OPb. An output signal from the logic section 1 is applied to the signal input terminals of both operational amplifiers OPa and OPb by the photocoupler PH and its load resistors R ₁ and R ₂ , and zener diodes ZD and The reference voltage formed by the resistors R ₃ and R ₄ is supplied. Short circuit detection circuit 2
The feedback circuit 3 will be described later.

In the above configuration, when the photocoupler PH is turned on by the logic signal, the input terminal voltages Va and Vb of both operational amplifiers OPa and OPb become lower than the reference voltage Vref as shown on the left side of FIG. Type operational amplifier O
The output of Pa becomes L level and the output of the inverting operational amplifier OPb becomes H level. Therefore, a current flows in the loop of DC power supply E → transistor Qnb → signal line L ₂ → signal line L ₁ → transistor Qpa → current detection resistor Rs → DC power supply E.

Next, when the logic signal is inverted, the inputs of both operational amplifiers become higher than the reference voltage, as shown on the right side of FIG. 2 (b), so that the outputs are inverted, and the DC power supply E → transistor Qna → line L ₁ → A current flows in the loop of the line L ₂ → transistor Qpb → power supply detection resistor Rs → DC power supply E. In this way, the bipolar signal swinging to both the positive and negative polarities is transmitted to the signal lines L ₁ and L ₂ .

The short-circuit detection circuit 2 compares the voltage across the current detection circuit Rs with the reference voltage formed by the Zener diode ZD and the resistors R ₅ and R ₆ by the comparator CP, and thereby the two signal lines L ₁ and L ₁ . The short circuit between the _two is detected, and the feedback circuit 3 receives the output of the short circuit detection circuit 2 and switches the input terminal voltage of the operational amplifiers OPa and OPb to the low level or the ground level, thereby making the outputs of both operational amplifiers the same. It is something to hold at the level. Fig. 1
In the embodiment of (a), when the signal lines are short-circuited, the current flowing through the current detection circuit Rs via the pair of transistors in the on-operation increases, which causes a large voltage drop in the current detection resistor Rs. Therefore, this voltage is input to the inverting input terminal, and this input voltage and the reference voltage (the Zener voltage of the Zener diode ZD are input to the non-inverting input terminal of the resistors R ₅ and R ₆
The output of the comparator CP, which is being compared with the voltage obtained by dividing the voltage in step (1), is inverted, and the RS flip-flop FF is set by the output, and the state is held. As a result, the transistor Qd is turned on, the collector potential is set to zero, the input terminal voltages Va, Vb, Vref are lowered via the diodes D ₁ and D ₂ , respectively, and the state shown in FIG. As a result, the potentials at the output terminals of both operational amplifiers OPa and OPb are fixed at the H level. As a result, the transistors Qna and Qnb of the bridge circuit are turned on, the transistors Qpa and Qpb are turned off, and the output loop is cut off. Resistors R ₂ and R ₄ are inserted so that each input voltage at this time has a relationship of Va>Vref> Vb as shown in FIG. 7C, and each resistance value is set to R ₁ / R ₂ >. It is set as R ₃ / R ₄ .

Actually, the short circuit between the signal lines L ₁ and L ₂ is often caused by a slight contact, and the cause is usually easily removed, but it is troublesome to manually reset the flip-flop FF each time. There is a problem. Fig. 2
The embodiment of (a) is an improvement in that point. A time constant circuit TM composed of a resistor Rt and a capacitor Ct is inserted at the signal input terminal of the comparator CP, and the output terminal voltage of the comparator CP is directly fed to the diodes D ₁ , D. It is intended to give feedback via ₂ . The figure (b) shows the operation, and when a short circuit accident occurs at time t ₁ , the voltage across the current detection resistor Rs increases due to the short circuit current, and the charging of the capacitor Ct is started by the increased voltage. , When this capacitor voltage Vc reaches the reference voltage (set value H) set by the Zener diode ZD and the resistors R ₅ and R ₆ ,
The output of the comparator CP is inverted to "L", the therefore the inverting input terminal of the operational amplifier OPb through the diode D ₂ becomes the "L", and block the bridge circuit to turn off the transmission output. At the same time, the cathode of the Zener diode ZD becomes “L” via the diode D ₁ , so that the comparator CP
The reference voltage of is also reduced to near zero (set value L), and then the charge of the capacitor Ct is discharged through the resistors Rt and Rs. When the capacitor voltage Vc reaches the set value L, the output terminal voltage of the comparator CP is restored. To do. In this way, the output loop is restored and the transmission of the transmission signal is restarted. However, if the short-circuit state continues, the charging of the capacitor Ct starts again, and the transmission output is repeatedly turned on and off until the cause of the short circuit is removed. During this period, since the duty ratio of the transmission output is small and the idle period is long, the output transistor Q
There is no danger of na, Qnb, Qpa, and Qpb generating heat, and a heat sink or the like is unnecessary. According to this structure, after eliminating the cause of the short circuit, the function can be automatically restored without manually operating the restoration switch.

[Advantages of the Invention] As described above, the present invention includes means for detecting a power supply current supplied to an output circuit including a transistor bridge,
By holding the outputs of both operational amplifiers at the H level when the power supply current exceeds the reference value, both NPN transistors are turned on, both PNP transistors are turned off, and the output loop is cut off. By holding the L level, both NPN transistors are turned off and both PNP transistors are turned on to cut off the output loop. Therefore, it is necessary to insert a separate switching element into the output circuit for short circuit protection. Moreover, since the output transistor itself can interrupt the circuit, there is no transmission loss due to the protection circuit, and there is an advantage that short circuit protection of the multi-pole signal transmission device can be provided with an extremely simple circuit configuration.

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram showing an embodiment of the present invention, FIGS. 1 (b) and 1 (c) are operation explanatory diagrams of the same, and FIG. 2 (a) is a circuit diagram showing another embodiment. FIG. 3B is an operation explanatory diagram of the above, FIG. 3A is a system configuration diagram of the embodiment, and FIG. 3B is a signal waveform diagram of the same. 1 is a logic unit, 2 is a short circuit detection circuit, 3 is a feedback circuit, Ta and Tb are totem pole circuits, and Qna and Qnb are N.
PN transistor, Qpa, Qpb are PNP transistors,
CP is a comparator, FF is an RS flip-flop, T
M is a time constant circuit, Rs is a current detection resistor, Rt is a charging resistor, Ct is a capacitor, D ₁ and D ₂ are diodes, ZD is a zener diode, R _{1 to} R ₇ are resistors, Q is a transistor,
E is a DC power supply, and L ₁ and L ₂ are signal lines.

Front Page Continuation (72) Inventor Mitsunobu Kuroda 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) Reference JP-A-54-64938 (JP, A) )

Claims (1)

[Claims] 1. A totem pole circuit comprising NPN transistors and two totem pole circuits each composed of a PNP transistor connected in parallel to form a bridge circuit. By controlling the transistor pair of, the multi-pole signal is transmitted to the two signal lines connected to the output terminals of both totem pole circuits, and the power supply current supplied to the bridge circuit is detected. And means for turning off both NPN transistors and turning off both PNP transistors to cut off the output loop by holding the outputs of the both operational amplifiers at the H level when the power supply current exceeds the reference value. Both NPN transistors are turned off and the PNP transistor Division multiplexing transmission apparatus when characterized by comprising comprises a means for interrupting the on and so the output loop.