JPH0695026B2 - Encoder open phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICABILITY The present invention outputs 90 ° phase-shifted incremental signals of A phase and B phase (hereinafter referred to as A phase and B phase) and Z phase of 1 pulse per rotation. The present invention relates to a processing circuit of an encoder output signal of a device using an encoder.

2. Description of the Related Art The configuration of a conventional encoder open phase detection circuit will be described below.

FIG. 4 is a block diagram of a conventional encoder open-phase detection circuit. 1 is a bias circuit that applies a bias to a signal that has received an input signal and changes the level, and outputs the signal. 2 is a circuit that receives the output of the bias circuit. , A level detection circuit for detecting the bias level, and 3 is a level conversion circuit for receiving the output of the bias circuit 1 and removing the bias component.

The operation of the encoder open phase detecting circuit configured as described above will be described below.

First, the A phase, B phase, and Z phase encoder signals are 0 or 5v.
Is input to the bias circuit 1, and the bias circuit 1 applies a bias to the signal, converts the signal level into 5v and 10v, outputs it as an encoder output, and transmits it to the processing circuit side. Next, it is input to the level conversion circuit 3 on the processing circuit side,
Converted to the original 0.5v level. At the same time, the level detection circuit 2 receives the output of the bias circuit 1 and detects whether the signal level is always 5v or higher, and the encoder signal is 5v.
When it changes to ~ 10v level, it is judged as normal, and conversely, when the encoder signal is open phase or disconnected and the signal level becomes 5v or less, it is judged as open phase and a signal of open phase is output.

Problems to be Solved by the Invention However, in the conventional configuration as described above, when the signal line is broken, the level becomes 5v or less, so that the phase loss can be detected, but the signal line is short-circuited with the power supply line and the phase loss occurs. In such a case, the voltage did not become 5v or less, the open phase could not be detected, and in terms of noise resistance, the differential transmission method could not be used because the signal level was changed, and there was a problem that it was weak to noise.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an encoder open phase detection circuit capable of detecting open phase in all states of disconnection and short circuit.

In order to achieve this object, the encoder phase loss detection circuit of the present invention has a detection circuit for detecting edges of A phase and B phase and output data of the edge detection circuit at the timing of Z phase. It is composed of a memory element for reading in.

Operation With this configuration, the Z phase is used as the reference signal, the edges of the A and B phases are detected between the pulses of the Z phase during rotation, and the open phase is detected. The A phase and B phase edges are generated by the Z phase pulse. The detection circuit is reset, an edge is detected until the next Z-phase pulse, the data is read by the storage element at the timing of the Z-phase pulse, and the open phase is detected. At the same time, the edge detection circuit is reset and the same operation is repeated again, and by detecting the edges of the A and B phases, the edge is detected if it is normal, and if there is no phase, there is no edge. Can be detected.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an encoder open phase detection circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 100 is an edge detection circuit that detects edges of the A phase and B phase, and 200 is a storage element that reads the output data of the edge detection circuit 100 at the timing of two phases. FIG. 2 shows a connection diagram of the encoder open phase detection circuit, in which three D flip-flops are used and the incremental A phase and B phase are input to the clock input 14 of the flip-flop 11 and the clock input 15 of the flip-flop 12, respectively. And input data 16 and 17 to H
Set it to the level. The outputs 18 and 19 of the flip-flops 11 and 12 are input to the AND circuit 25, and the outputs are connected to the data input 22 of the flip-flop 13. The Z-phase is input to the resets 20 and 21 of the flip-flops 11 and 12 and the clock input 23 of the flip-flop 13, and an encoder open phase detection signal is obtained from the output 24 of the flip-flop 13.

The operation of the encoder open phase detecting circuit configured as described above will be described below with reference to the time chart of FIG. FIG. 3A is a time chart when the phase is not lost. First, each flip-flop is initialized, and the outputs 18 and 19 of the flip-flops 11 and 12 are L level.
Then, the output 24 of the flip-flop 13 is set to H. Output 1 when encoder signal is input and edge is detected
8,19 becomes H. After that, the flip-flop 13 reads the output of the AND circuit 25 at the edge of the Z-phase pulse, but since the outputs of the flip-flops 11 and 12 are H,
The output 24 remains H, and at the same time, the flip-flops 11 and 12 are reset by the Z-phase pulse, and the same operation is repeated again.

Next, the operation when the phase is lost will be described with reference to the time chart of 3-b. Phase A of the encoder signal was normal at first, but
It is assumed that the phase is lost and fixed to L. The encoder rotates, the flip-flops 11 and 12 are reset in the Z phase, and after reset, the A phase and the B phase are input to the clock inputs 14 and 15, but the A phase is open and fixed to L and the edge is fixed. Since there is no data, the data fixed at H of the data input cannot be read, and the output 18 remains L. Further, since the B phase is normal, the output 19 of the flip-flop 12 becomes H. Next, at the edge of the Z-phase pulse, the flip-flop 13 reads the output of the AND circuit 25. Since the output 18 is L and the output 19 is H, the output of the AND circuit 25 is L and the data input 22 to L , The output of the flip-flop 13 becomes L, and the open phase can be detected.

As described above, in this embodiment, the flip-flop is used, and Z
The phase loss can be detected by detecting the edges of the A phase and B phase with the phase pulse.

In this embodiment, three flip-flops are used, the two flip-flops detect the edges of the A-phase and the B-phase, the logical product of the outputs is taken, and the third flip-flop outputs the data Z.
Although it was latched at the phase timing, any signal may be output as long as it outputs a reference signal of 1 pulse or more per rotation even if it is not the Z phase. For example, the magnetic pole position detection signal of the AC servo motor of the rectangular wave drive Can also be used.

Further, although the D flip-flop is used as the memory element in this embodiment, any type of memory element capable of detecting an edge can be used.

As described above, the present invention uses the Z phase as a clock, detects the edge of the incremental signal of the encoder, is reset by the Z phase pulse once per rotation, and is the first rising edge of the A phase or B phase. An encoder phase loss can be detected by providing an edge detection circuit that detects an edge and holds the state until the next Z-phase pulse is input, and a storage element that reads the output data of the detection circuit at the Z-phase timing. Further, since the edge is detected, even if the signal line of the encoder is fixed to H or L due to disconnection or short circuit, the open phase can be detected in the same manner.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoder open phase detection circuit in an embodiment of the present invention, FIG. 2 is a connection diagram of the encoder open phase detection circuit, and FIG. 3 is a case where the encoder signal in FIG. 2 is normal. 4 is a configuration diagram of a conventional example. 11 ... First flip-flop, 12 ... Second flip-flop, 13 ... Third flip-flop, 25 ... AND circuit, 100 ... Edge detection circuit, 200 ... Storage element.

Claims (1)

[Claims] 1. An edge of a 90 ° phase-shifted incremental signal of A phase and B phase is detected and reset by a Z phase pulse once per rotation, and the first rising edge of A phase or B phase. And an edge detection circuit that holds the state until the next Z-phase pulse is input, and a storage element that reads the output data of the edge detection circuit at the Z-phase timing and detects a missing phase. Phase loss detection circuit.