JPH0695627B2 - Low frequency digital filter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a low frequency band digital filter that processes data input in time series based on a predetermined algorithm and outputs the processed data as time series data.

(B) Conventional Technology In general, primitive information sources existing around us, such as voices and images, are often analog signals. A system that processes this analog signal by a digital method is a digital signal processing device (digital signal processing system: DSP system).

In recent years, digital circuits are rapidly becoming LSIs, and DSP systems can be easily realized on a single chip. Furthermore, high-accuracy processing is possible compared to analog signal processing, and arbitrary characteristics are stabilized by setting parameters. Since it has the characteristics that it can be uniformly obtained and adjustment can be made, DSP
The system came into practical use rapidly. Also, DS
The application range of the P system is broadly used for voice signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, underwater acoustic signal processing, and the like.

Also in the audio field, a DS (digital compact disc) player or a DAT (digital audio tape) player, which processes audio signals digitally as digital processing of audio signals progresses.
P system has been put to practical use.

A conventional DSP system has an architecture shown in FIG. 7 so that a digital filter can be easily formed.

In FIG. 7, the data bus (1) has an input / output circuit (I / O) (2), a data RAM (2) a multiplier (3), an arithmetic circuit (ALU) (4), and an accumulator (ACC). ) (5) etc. are connected, the output of the data RAM (2) and the output of the data ROM (6) are connected to the multiplier (3), and the multiplication result output of the multiplier (3) is one of the ALU (4). Applied to the input of. Each of these circuits is controlled by a microcode signal output from a decoder (8) that decodes the instructions sequentially read from the program ROM (7) in response to the instructions.

By the way, in the case of implementing a graphic equalizer in audio signal processing, it can be obtained by cascading a plurality of second-order direct type IIR filters shown in FIG. The IIR type filter of FIG. 8 has Y _i = C ₁ X _i + C ₂ X _i-1 + C ₃ X _i-2 + C ₄ X _i-1 + C ₅ X _i-2 (1)
Equation (C ₁ , C ₂ , C ₃ , C ₄ , and C ₅ are constants that determine the filter characteristics) is used to calculate the sum of products, and Z ^-1 shown in (29) is the unit time (in this case, sampling (30) is a multiplication element having constants C _{1 to} C ₅ , and (31) is an addition element.

When this digital filter is realized by a DSP system, the calculation order of the nodes in the filter is determined, a program is created, and the program is stored in the program ROM (7) and calculated in the data ROM (6). Stores the constant of the expression. Then, by executing the program, the product-sum operation is performed, and the operation result is sequentially stored in the data RAM (2).

(C) Problems to be solved by the invention The graphic equalizer function can be realized by connecting digital filters having different center frequencies in cascade, and at each stage, the product-sum operation of the equation (1) is performed. There is.

However, in the case of a low-frequency band digital filter with a center frequency of about 200 Hz, the effective digits below the decimal point of the constant that performs the product-sum operation become long, and the limited number of bits, such as 16
When the sum-of-products calculation is performed with bits, there are drawbacks such as deterioration of calculation accuracy, deterioration of filter characteristics, and distortion of audio signals in the low frequency range.

Further, in order to improve the calculation accuracy in the low frequency band, it is necessary to increase the number of bits of the constant and the number of bits of the multiplier. Therefore, the memory and the multiplier for storing the constant become large,
There is an inconvenience that becomes an obstacle when integrated into an integrated circuit.

(D) Means for Solving the Problems The present invention was created in view of the above points,
Each of the filter constants of the low frequency band digital filter is α + δ · β (α is an integer closest to the constant, β is an integer α
And the filter constant difference is the numerical value common to each filter constant δ <<
In a low frequency band digital filter that obtains a filter output by using each coefficient α, β, δ, the digital data input every predetermined time unit is A plurality of first delaying means for delaying;
A first multiplication of the input digital data and each delay output of the first delay means by the corresponding coefficient β.
Second multiplying means for delaying the digital data of the filter output by the time unit, and second multiplying means for multiplying each delay output of the second multiplying means by the corresponding coefficient β. Means, first adding means for adding each output of the first multiplying means and each output of the second multiplying output, and third adding means for multiplying the addition result of the first adding means by the coefficient δ. Multiplying means, subtracting means for subtracting digital data of a filter output from the input digital data, a plurality of third delaying means for delaying the output of the subtracting means by the time unit, and the third delaying means. Fourth multiplication means for multiplying the coefficient α corresponding to a predetermined output of the means, the input digital data, the multiplication result of the third multiplication means, the multiplication result of the fourth multiplication means, and the The data output from the third delay circuit Adding Tal data, characterized by being configured a low frequency band digital filter by a second adding means for the filter outputs the addition result.

(E) Action According to the above-mentioned means, the constants C ₁ , C ₂ , C _{3 of} equation (1) for realizing the digital filter are α + β · δ [α is a constant in the low frequency band. Near integer, β is divided into the form of difference between integer α and constant and each constant is divided by common constant δ (δ << 1)], and sum of products of each constant β with respect to input data After performing the calculation, the constant δ can be multiplied, and the result of the product-sum calculation of each constant α and the input data can be added to or subtracted from the multiplication result.

As a result, since the decimal point of each constant is expressed as a product of the significant digit β and a very small common constant δ of 1 or less, such as β · δ, β is a limited small number of bits, for example, 16 bits. The product-sum operation with the data can be performed accurately. Then, by multiplying the result of the product-sum calculation of β by β, the calculation result of the part below the decimal point is obtained. On the other hand, by multiplying and summing the integer part α and data and adding both, the overall calculation result can be obtained, and the calculation in the low frequency band can be performed with a 16-bit data length with sufficient accuracy. obtain.

(F) Embodiment FIG. 1 is a circuit diagram of a low frequency band digital filter showing an embodiment of the present invention. In the figure, Z indicated by (29)
^-1 is a delay element of unit time (here, sampling period), which can be configured by a latch circuit or a memory operated by a sampling signal. (30) is a constant multiplication element, and (31) is an addition element, which is composed of a multiplication circuit and an addition circuit.

In the case of the conventional digital filter shown in FIG. 8, when the center frequency is in the low frequency band of about 200 Hz, the constants C _{1 to} C ₅
The number of significant digits of can not be represented by 16 bits.
Therefore, in the present invention, each constant is converted into the form α + β · δ. That is, α is the nearest integer constant,
β is a quotient obtained by dividing the difference between the integer α and the original constant C by a number δ smaller than 1. If the center frequency is 200Hz, the constants C _{1 to} C ₅
Is C ₁ = 1 + a · δ C ₂ = −2 + b · δ C ₃ = 1 + c · δ C ₄ = 2 + d · δ C ₅ = −1 + e · δ. Here, δ is 1/2 ⁿ (n is an integer). Substituting these into the equation (1), Y _i = X _i −2X _i-1 + X _i-2 + 2Y _i-1 −Y _i-2 + δ (aX _i + bX _i-1 + cX _i-2 + dY _i-1 + eY _{i -2} ) = X _i- 2 (X _i-1 -Y _i-1 ) + X _i-2 -Y _i-2 + δ (aX _i + bX _i-1 + cX _i-2 + dY _i-1 + e
Y _i-2 ).

FIG. 1 shows a circuit that realizes the product-sum calculation. That is, aX
_i + bX _i-1 + cX _i-2 + dY _i-1 + eY _i-2
And the input data X _i and the data X _i-2 −Y _i-2 two samplings before are added to the multiplication result, and from the result, the data X _i−1 −Y _i one sampling before is added. _The output data Y _i is calculated by subtracting _-1 multiplied by 2. Therefore, 16
Since the sum-of-products operation is performed using the constants a, b, c, d, and e, in which the significant digits are sufficiently represented by bits, the operation precision below the decimal point is improved.

FIG. 2 shows a circuit that realizes the graphic equalizer. That is, the filters shown in FIG. 1 and FIG. 8 are connected in cascade. In the first stage, the input data is X _i , the constants are A, B, C, D, E, and the output is Y _i . Yes, in the second stage, the input data is Y _i , the constants are a, b, c, d, e, δ, 2, and the output data is Z _i .

The digital filter shown in FIG. 1 and FIG.
It is also possible to realize with program software using.

FIG. 3 is a block diagram of an audio DSP which is convenient for realizing a digital filter, and includes a pair of digital processing circuits (9) (10) and the digital processing circuits (9) (1).
Data input / output circuit (12) connected to the data bus (BUS1) (BUS2) (11) of (0), an interface circuit (13) similarly connected to the data bus (11), and these digital processing circuits (12). 9) (10), data input / output circuit (12),
And a control circuit (14) for controlling the operation of the interface circuit (13).

The data bus (11) has a 24-bit structure of 8 bits × 3. The data input / output circuit (12) serially inputs 16-bit left-channel and right-channel sampling data (for example, in the case of a CD player, the sampling frequency is 44.1 kHz) to the input terminal IN serially. , Left channel data is BUS1 of data bus (11)
The data of the right channel is sent to BUS2 of the data bus (11), and the processed left channel data sent to the data bus BUS1 and the processed right channel data sent to the data bus BUS2 are sent. It receives and alternately outputs serially from the output terminal OUT. The interface circuit (13) sends and receives data between the DSP system and a microcomputer (not shown), and sends constants of the digital filter applied from the microcomputer to the data bus (11). , Receives the system status data and the like sent to the data bus (11) and sends them to the microcomputer. The data processing circuit (9) is for left channel data processing, and the data processing circuit (10) is for right channel data processing. That is, the data processing circuits (9) (10) are connected to the data bus (11) and the data RAM (1
5), constant RAM (16), constant ROM (17), address pointers (18) (19) (20), multiplier (MUL) (21), ALU (2
2), accumulator (ACC) (23), and temporary registers (TMP1, TMP2, ...) (24). data
The RAM (15) is a first RAM having a capacity of 24 bits × 128 for storing the data before processing and the data after arithmetic processing sent from the data input / output circuit (12), and the data bus (11) And the input of the multiplier (21). Constant RAM
(16) is a 16-bit memory for storing constants such as digital filter coefficients sent from the interface circuit (13) ×
A second RAM having a capacity of 256, which is connected to the data bus (11) and the other input of the multiplier (21). The address pointer (18) consists of 8 bits and is a data RAM (15)
Addressing is performed, which is controlled by microcodes INC1 and DEC1 output from the control circuit (14) and has a function of incrementing (+1) and decrementing (-1) the held address data, It has a register that can set an arbitrary value by a program and a circuit that compares the set value with the address data. When the result of incrementing the address data exceeds the set value, it becomes "0", and the decrement result becomes "0". When it is less than ", it has a function of setting value, that is, a function of circulating between" 0 "and the setting value. This circular addressing function is used to simplify the product-sum operation of digital filters. In addition, the address pointer (19) is a constant RAM (1
6) is a 10-bit pointer that specifies the address of
Controlled by the microcode INC2 output from the control circuit (14), the function to increment the address data,
It has the function of being cleared to "0" by the microcode CLEAR2 output from the control circuit (14). Furthermore,
The address pointer (20) is an 8-bit pointer that specifies the address of the constant ROM (17), and the control circuit (14)
It has the function of decrementing the address data by the microcode DEC3 output from.

The multiplier (21) performs multiplication of 24 bits × 16 bits, the A input is 24 bits and the B input is 16 bits, and the multiplication result is determined after one cycle. Furthermore,
The input selection circuit MPXA is used for the A and B inputs of the multiplier (21).
And MPXB are provided, and the input selection circuit MPXA is a control circuit (1
Data bus (1 by microcode A-BUS from 4)
Select 1) and use microcode A-DRAM to data RAM
(15) is selected and applied to the A input, and the input selection circuit MPXB
Selects the data bus (11) with the microcode B-BUS and the constant RAM (16) with the microcode B-CRAM.
And select the constant ROM (1
Select 7) and apply to the B input. The multiplication result is output in 32 bits.

The ALU (22) is a 32-bit arithmetic circuit, and the 32-bit multiplication result input to one side and the 32-bit arithmetic result input to the other side.
The data of ACC (23) is added by microcode Add and the result is transferred to ACC (23). ACC (23)
Of the 32 bits, the upper 24 bits are connected to the data bus (11) and the lower 8 bits are connected to the lower 8 bits of the temporary register (24) by the auxiliary bus (25). The temporary register (24) is composed of 32-bit registers TMP1, TMP2 ... TMP8, and holds up to eight 32-bit data. The upper 24 bits of each are connected to the data bus (11). . Temporary register (24) with data bus (11) and auxiliary bus (25)
32-bit data is transferred between ACC and ACC (23).

The control circuit (14) is a program RO that stores the program.
M (26), a program counter (PC) (27) that specifies the address of the program ROM (26), and an instruction decoder (I-DEC) (2) that decodes the read instruction.
8) and Program ROM (26) is 32 bits x 51
It has a capacity of 2 and stores a program for realizing a digital filter and other necessary programs. The instruction decoder (28) decodes an instruction and outputs a microcode, and controls the address pointers (18) (19) (20) INC1, INC2, DEC1, C.
AB for controlling LEAR2, DEC3 and input selection circuits MPXA, MPXB
US, A-DRAM, B-BUS, B-CRAM, B-CROM, or ALU (2
2) Output ADD, THR, etc. that control Since this microcode is applied to a common circuit of each part of the data processing circuits (9) and (10), the same control is simultaneously performed on the data processing circuits (9) and (10) by executing one instruction. .

In the DSP system shown in FIG. 3, an example of the instructions necessary to configure the digital filter is shown in FIG.
In FIG. 4, the MUL instruction is a multiply instruction, and the multiplier (2
The object to be input to the input A and the input B of 1) is selected and multiplication is performed. The AP instruction increments, decrements or clears the address pointers (18) (19) (20). The ALU command is a control command for ALU (22), and ALUADD stores the two input data.
Add with ALU (22), hold the addition result in ACC (23),
ALUSUB subtracts the data of one input from the data of the other input, and the subtraction result is held in ACC (23).
This is an instruction to hold the multiplication result from the multiplier (21) in the ACC (23) as it is. RAM1D, TMP1D, TMP2D, TMP3D are store instructions, and the data on the data bus (11) is data RAM
(15), it is stored in the temporary register (24). AC
LS, TMP1S, TMP2S, TMP3S are transfer instructions, and ACC (23),
Data of temporary register (24) is transferred to data bus (1
1) and an instruction to send to the auxiliary bus (25).

Next, a method for realizing the graphic equalizer as shown in the second by using the DSP system shown in FIG. 3 will be described.

FIG. 5 is a diagram showing a program for realizing the digital filter of FIG. 2, and FIG. 6 shows data stored in the data RAM (15), the constant RAM (16), and the temporary register (24). FIG. Since the multiplication of constants is performed in the order of C, B, A, E, D, c, b, a, e, d by the program of FIG. 5, the constant RAM (16) addresses "0" to "9" Up to, constants are stored in the same order. On the other hand, data RAM (1
In 5), the data of x _i , y _i , and z _i are written every 3 addresses, but the sampling cycle, that is, one address is shifted for each calculation process for one input data x _{i + 1} .
By writing x _{i + 1} , y _{i + 1} , and z _{i + 1} , the delay element (2
We are creating delay data according to 9). Therefore, in the case of the digital filter shown in FIG. 2, the address pointer (18) is circular addressing of "0" to "7", and the address pointer (19) is "0" to "9". It is set in advance by a program so that the cyclic address is designated.

Here, when the step "0" of the program of FIG. 5 is executed for the input data x _i , the data RAM (1
When the content of 5) is as shown in FIG. 6 (a), and when the address pointers (18) and (19) are both addresses "0", when step "0" is executed, the multiplier (21) The inputs A and B are stored at the address "0" of the data RAM (15). The data x _i-2 (input data two samples before) and the coefficient C stored at the address “0” of the constant RAM (16) are applied, but the multiplication result is determined and output in the next step. It Also, at the end of step "0",
Address pointer (18) (19) by AP1INC and AP2INC
Are incremented together, and the content becomes "1".

When the step "1" is executed, the data RAM (15) and the constant RAM (16) are selected as the input of the multiplier (21) as in the step "0", and stored in the address "1" respectively. The data x _i-1 and the constant B are applied to the multiplier (21). In addition, the result of multiplication at the previous step "0" is the instruction AL.
The UTHR stores the first multiplication result C · x _{i−2 in} ACC (23) by passing it through ALU (22). At the end of step "1", the address pointer (1
8) (19) is incremented and the content becomes address "2".

Next, when step "2" is executed, the command MULA-BUS,
The B-CRAM selects the data bus (11) for the input A and the constant RAM (16) for the input B of the multiplier (21). On the other hand, the instruction TMP1S sends the contents of the temporary register TMP1 to the data bus (11), and the instruction RAM1D
The data sent to the data bus (11) is stored in the address "2" of the data RAM (15) designated by the address pointer (18). At this time, the temporary register TMP1 has a data input circuit (1
Input data x _i applied from the outside is stored in advance in 2). Therefore, the input data x _i is multiplied by the constant A read from the constant RAM (16) by the multiplier (21) and is stored in the address “2” of the data RAM (15). On the other hand, by the command ALUADD, the multiplication result B · x of C · x _i−2 stored in ACC (23) and step “1”
_i-1 is added, and as a result, B · x _i-1 + C · x _i-2 is ACC
Stored in (23). At the end of step "2", the address pointers (18) and (19) are incremented, and the content becomes the address "3".

When step "3" is executed, the input A of the multiplier (21) is input.
The data y _i-2 and the constant E stored in the address “3” of the data RAM (15) and the constant RAM (16) are applied to B and B, and the multiplication result A of the step “2” is given by the instruction ALUADD.
・ Contents of x _i and ACC (23) B ・ x _i-1 + C ・ x _i-2 is ALU (22)
The result of addition is A · x _i + B · x _i-1 + C · x
_i-2 is stored in ACC (23). At the end of step "3", the address pointers (18) and (19) are incremented to become the address "4".

When step "4" is executed, the input A of the multiplier (21)
The data y _i-1 stored at the address “4” of the constant RAM (16) of the data RAM (15) and the constant D are applied to B and B, and the multiplication result E of step “3” is given by the instruction ALUADD.
・ The contents of y _i-2 and ACC (23) A ・ x _i-1 + B ・ x _i-1 + C ・ x
_i-2 is added in ALU (22), and the addition result is A · x _i + B
-X _i-1 + C * x _i-2 + E * y _i-2 is stored in ACC (23). At the end of step “4”, the address pointer (18) is decremented to the address “3” by the instructions AP1DEC and AP2INC, and the address pointer (19) is incremented to the address “5”.

When step “5” is executed, the input A of the multiplier (21) is input.
In and B, the data y _i-2 stored at the address “3” of the data RAM (15) and the address “5” of the constant RAM (16).
The constant c stored in is applied. That is, the multiplier (2
In step 1), the multiplication of the second stage of the digital filter shown in FIG. 2 is performed from step "5". Meanwhile, the instruction ALUADD
Results in multiplication result of step “4” D · y _i-1 and ACC (2
3) Content A ・ x _i + B ・ x _i-1 + C ・ x _i-2 + E ・ y _i-2 is ALU
It is added in (22), and the addition result is A · x _i + B · x _i-1 +
C · x _i-2 + D · y _i-1 + E · y _i-2 are stored in ACC (23). At this time, the content of ACC (23) becomes the output y _i of the first-stage digital filter. At the end of step "5", the address pointer (18) is incremented to the address "4", and the address pointer (19) is incremented to the address "6".

When step "6" is executed, the input A of the multiplier (21) is input.
In and B, the data y _i-1 stored in the address “4” of the data RAM (15) and the address “6” of the constant RAM (16) are stored.
The constant b stored in is applied. Further, the instruction ACC sends the data y _i stored in the ACC (23) to the data bus (11), and the instruction TMP1D sends it to the data bus (1
1) Data y _i sent to 1) is temporary register TMP1
Will be stored in. On the other hand, the instruction ALUTHR causes the multiplication result c · y _i-2 of step “5” to pass directly through ALU (22) to A.
Stored in CC (23). At the end of step "6", the address pointers (18) and (19) are incremented to the addresses "5" and "7".

When step "7" is executed, the commands MULA-BUS, B-CRA
By M, the data sent to the data bus (11) and the constant a stored at the address "7" of the constant RAM (16) are applied to the inputs A and B of the multiplier (21). The data y _i stored in the temporary register TMP1 by the instructions TMP1S and RAM1D is sent to the data bus (11) and applied to the input A of the multiplier (21) and designated by the address pointer (18). The data is stored in the address "5" of the data RAM (15). On the other hand, by the instruction ALUADD, the multiplication result b · y _i-1 of step “6” and c · y _{i-2 of} ACC (23).
Are added in ALU (22), and the result is b · y _i-1 + c
・ Y _i-2 is stored in ACC (23). At the end of step "7", the address pointers (18) and (19) are incremented to address "6" and address "8".

When step “8” is executed, the input A of the multiplier (21) is input.
In and B, the data z _i-2 stored in the address “6” of the data RAM (15) and the address “8” of the constant RAM (16) are stored.
Stored in the the constant e is applied, whereas the multiplication result a · y _i and ACC (23) b · Data is stored in y the ALU (22) in at step "7" _i-1 + c · y _{i- 2} is added, and as a result, a · y _i + b · y _i-1 + c · y _i-2 is stored in ACC (23). At the end of step "8", the address pointer (1
8) (19) is incremented to become address "7" and address "9".

When step "9" is executed, the input A of the multiplier (21) is input.
In and B, the data z _i-1 stored at the address “7” of the data RAM (15) and the address “9” of the constant RAM (16) are stored.
Is applied to the constant d, while in ALU (22), the multiplication result of step "8" e · z _i-2 and ACC (23)
The data _a.yi + b.yi _-1 + c.yi _-2 stored in is added and the addition result _a.yi + b.yi _-1 + c.yi _-2 + e.z
_i-2 is stored in ACC (22). When the address pointers (18) and (19) are incremented at the end of step "9", both the address pointers (18) and (19) become the address "0".

When step “10” is executed, multiplication is not performed, and the multiplication result d · z _{i−1 of} step “9” and the data a · y _i + b · y _i-1 + c · y stored in ACC (23) are obtained. _i-2 + e · z _i-2 is ALU
It is added in (22), and the addition result is a ・ y _i + b ・ y
_i-1 + c · y _i-2 + d · z _i-1 + e · z _i-2 is stored in ACC (23).

When step "11" is executed, the data stored in ACC (23) is shifted to the right by n bits. The shifted result is δ (a · y _i + b · y _i-1 + c · y _i-2 + d · z _i-1
+ E · z _i-2 . That is, since δ is set to 1/2 ⁿ , shifting to the right by n bits is equivalent to multiplication by 1/2 ⁿ . When step "12" is executed, the instruction TMP3
By S, the data y _i-2 −z _i-2 held in the temporary register TMP3 is sent to the data bus (11) and the ALU
In (22), it is added to the data of ACC (23), and the addition result is y _i-2 −z _i −2 + δ (a · y _i + b · y _i-1 + c · y)
_i-2 + d · z _i-1 + d · z _i-2 ) is held in ACC (23).

When step "13" is executed, the instruction TMP2S sends the data y _i-1 -z _i-2 of the temporary register TMP2 to the data bus (11) and obtains the delay data for the processing of the next sampling data. Therefore, the instruction y TMP3D writes the data y _i-1 −z _i−1 to the temporary register TMP3. On the other hand, by the command ALUSUB, ACC in ALU (22)
The data y _i-1 −z _i-1 sent to the data bus (11) is subtracted from the data held in (23), and the result is ACC (2
Held in 3).

When step "14" is executed, the data y _i-1 -z _i-1 is sent to the data bus (11) as in step "13".
From the data held in ACC (23) at ALU (22)
y _i-1 −z _i-1 is subtracted, and the result is written in ACC (23). The data of ACC (23) at this time is -2 (y _i-1 -z
_i-1 ) + (y _i-2 −z _i-2 ) + δ (a ・ y _i + b ・ y _i-1 + c ・ y
_i-2 + d · z _i-1 + e · z _i-2 ).

When step "15" is executed, the instruction TMP1S causes the data x _i of the temporary register TMP1 to be transferred to the data bus (11).
To the ACC (23) and the addition result is written to the ACC (23). The data in ACC (23) at this time is y _i-2 (y _i-1 −z _i-1 ) + (y
_i-2 −z _i-2 ) + δ (a ・ y _i + b ・ y _i-1 + c ・ y _i-2 + d ・ z
_i−1 + e · z _i−2 ), that is, the output data z _i of the digital filter.

When step "16" is executed, the instruction ACCS causes ACC (2
The data z _i stored in 3) is sent to the data bus (11) and is stored in the address “0” of the data RAM (15) designated by the address pointer (18) by the instruction RAM1D.

When step “17” is executed, the instruction TMP1S transfers the data y _i of the temporary register TMP1 to the data bus (11).
Dispatched by instruction ALUSUB, from the data y _i ACC (2
The data z _i stored in 3) is subtracted by ALU (22) and y _i
−z _i is stored in ACC (23).

When step "18" is executed, the instruction ACCS causes ACC
The data y _i −z _i stored in (23) is stored in the data bus (11).
And the instruction TMP2D stores the data y _i −z _i of the data bus (11) in the temporary register TMP2,
Next, it becomes delay data for processing the sampling data. At the end of step "18", the instruction AP1INC increments the address pointer (18) to the address "1". Therefore, when the processing of the next sampling data x _{i + 1} is started, the data RAM (15) addressed by the address pointer (18) is accessed from the address “1”, which is one address after the previous start address. It shifts earlier.

By executing the programs of the above steps “0” to “18” at each sampling cycle, the input data x _i ,
Filtering is applied to x _{i + 1} , x _{i + 2} ...
The contents of RAM (15) are shown in Fig. 7 (a) (b) (c) (d) ...
.., and filter outputs z _i , z _{i + 1} , z _{i + 2} ,.

In this way, the digital filter shown in FIG.
The product-sum operation of the low-frequency band digital filter shown in the figure can be continuously performed, and since the effective number below the decimal point of the constant is multiplied by being represented by 16 bits, the multiplication precision is improved.

(G) Effect of the Invention As described above, according to the present invention, in the low frequency band digital filter, since the multiplication accuracy can be increased without increasing the number of multiplication bits, the filter characteristic in the low frequency band is good. Can be secured. Further, it can be continuously performed with other low frequency band filtering. In particular, when a graphic equalizer is realized by a DSP system, the number of program steps can be shortened, there is room for other processing, and this also contributes to improvement in the throughput of the entire DSP system.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment, and FIG. 3 is a convenient view for realizing the digital filter shown in FIGS. 1 and 2. 4 is a block diagram of a DSP, FIG. 4 is a diagram showing an example of instructions used in the DSP device of FIG. 3, FIG. 5 is a diagram showing a program for realizing the graphic equalizer of FIG. 2, and FIG. RA
FIG. 7 is a block diagram of a general DSP device, FIG. 8 is a circuit diagram of a conventional digital filter, and FIG. 7 is a data allocation diagram of M, a constant RAM, and a temporary register. (9) (10) …… Digital processing circuit, (12) …… Data input / output circuit, (13) …… Interface circuit, (14)
...... Control circuit, (11) …… Data bus, (15) …… Data RAM, (16) …… Constant RAM, (17) …… Constant ROM, (1
8) (19) (20) …… Address pointer, (21) …… Multiplier, (22) …… ALU, (23) …… Accumulator (A
CC), (24) …… temporary register, (25) …… auxiliary bus, (26) …… program ROM, (27) program counter, (28) …… instruction decoder,
(29) …… Delay element, (30) …… Multiplier element, (31) ……
Addition element.

Claims (1)

[Claims] 1. A plurality of filter constants of a low frequency band digital filter are respectively α + δβ (α is an integer closest to the constant, β is an integer α and the difference between the filter constants is a numerical value δ << 1 common to each filter constant. Divided by the value), and in the low-frequency band digital filter that obtains the filter output using each coefficient α, β, δ, delay the digital data input every predetermined time unit in the time unit. A plurality of first delay means, and a first multiplication means for multiplying the input digital data and each delay output of the first delay means by the corresponding coefficient β.
Means, a plurality of second delay means for delaying the digital data of the filter output by the time unit, and a second multiplication for multiplying each delay output of the second multiplying means by the corresponding coefficient β. Means, first adding means for adding each output of the first multiplying means and each output of the second multiplying output, and third means for multiplying the addition result of the first adding means by the coefficient δ. Multiplying means, subtracting means for subtracting digital data of a filter output from the input digital data, and a plurality of third delaying means for delaying the output of the subtracting means by the time unit.
Delay means, fourth multiplying means for multiplying the coefficient α corresponding to the predetermined output of the third delay means, the input digital data, the multiplication result of the third multiplying means, and the fourth A low-frequency band digital filter comprising: a second addition unit that adds the multiplication result of the multiplication unit and the digital data output from the third delay circuit and outputs the addition result as a filter output.