JPH07101835B2 - Digital signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital signal processing device that processes data input in time series based on a predetermined algorithm and outputs the processed data as time series data.

(B) Conventional Technology In general, primitive information sources existing around us, such as voices and images, are often analog signals. A system that processes this analog signal by a digital method is a digital signal processing device (digital signal processing system: DSP system).

In recent years, digital circuits are rapidly becoming LSIs, and DSP systems can be easily realized on a single chip. Furthermore, high-accuracy processing is possible compared to analog signal processing, and arbitrary characteristics are stabilized by setting parameters. Since it has the characteristics that it can be uniformly obtained and adjustment can be made, DSP
The system came into practical use rapidly. Also, DS
The application range of the P system is broadly used for voice signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, underwater acoustic signal processing, and the like.

Also in the audio field, a DS (digital compact disc) player or a DAT (digital audio tape) player, which processes audio signals digitally as digital processing of audio signals progresses.
P system has been put to practical use.

A conventional DSP system has an architecture shown in FIG. 6 so that a digital filter can be easily formed.

In FIG. 6, an input / output circuit (I /
O) (1), data RAM (2), multiplier (3), arithmetic circuit (ALU) (4), accumulator (ACC) (5), etc. are connected, and output of data RAM (2) and data ROM ( The output of 6) is connected to the multiplier (3), and the multiplication result output of the multiplier (3) is applied to one input of the ALU (4). Each of these circuits is controlled by a microcode signal output according to the instruction from a decoder (8) that decodes the instructions sequentially read from the program ROM (7).

In the realization of a digital filter, the multiply-accumulate operation of the form Y = A · x ₁ + B · x _i-1 + C · x _i-2 ... appears repeatedly. When this digital filter is realized by a DSP system, the calculation order of the nodes in the filter is determined, a program is created, and the program is stored in the program ROM (7) and calculated in the data ROM (6). Stores the constant of the expression. Then, by executing the program, the product-sum operation is performed, and the operation result is sequentially stored in the data RAM (2).

(C) Problems to be solved by the invention When the DSP system shown in FIG. 6 is used in the audio field, it is necessary for audio such as graphic equalizer function, bass treble, loudness, low boost function and surround effect function. However, since there are left and right two-channel signals in the audio signal, the left and right channel signals must be subjected to the above-described functions. In order to change the characteristics of the left and right channels independently, different constants must be written in the data ROM.

Therefore, in a CD player or DAT player, the signal sampling cycle has a high frequency such as 44.1 KHz or 48 KHz. Therefore, all the processing for realizing the above-mentioned function is performed on the left and right channels during the sampling cycle. You have to finish each one. Therefore, depending on the processing speed of the DSP system, it may not be possible to realize any of the functions described above. That is, there is a drawback that the throughput of the DSP system deteriorates.

(D) Means for Solving the Problems The present invention was created in view of the above points,
A first RAM that stores a plurality of input digital data and operation result data, a second RAM that stores a plurality of constants for realizing a digital filter, and a first RAM that specifies an address of the first RAM. Data pointer and the second
Second data pointer designating the RAM address of
A multiplier for multiplying the data read from the first RAM and the second RAM, and a calculation for calculating the multiplication result of the multiplier and the operation result held in the accumulator and holding the operation result in the accumulator A pair of digital processing circuits having at least a circuit (ALU) are provided, and the pair of digital processing circuits are simultaneously controlled by a control circuit which decodes a preprogrammed instruction and outputs a control signal, thereby producing a left and a right. It is intended to provide a digital signal processing device in which the signals of the channels are independently processed at the same time and the slewing is improved.

(E) Operation According to the above-mentioned means, for example, when the program that realizes the digital filter is executed, the data read from the first RAM and the constant read from the second RAM are multiplied. The multiplication result and the data held in the accumulator are added or subtracted, and the processing result is held again in the accumulator. This operation is simultaneously performed in each of the pair of digital processing circuits, and as a result, the sum of products operation is simultaneously performed on the two input data, that is, the left channel data and the right channel data, and the filter operation is performed. Since it is performed, a throughput twice as high as that of the conventional one can be obtained. Further, when different filter characteristics are obtained for the left and right channels, different filter characteristics can be stored in the second RAM of each digital processing circuit and then the same multiply-add operation can be performed.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. A pair of digital processing circuits (9) and (10) and a data bus (BUS1) of the digital processing circuits (9) and (10). ) (BUS2) (11)
Data input / output circuit (12) connected to the data bus and interface circuit (13) similarly connected to the data bus (11)
And a digital processing circuit (9) (10), a data input / output circuit (12), and a control circuit (14) for controlling the operation of an interface circuit (13). .

The data bus (11) has a 24-bit structure of 8 bits × 3. The data input / output circuit (12) serially inputs 16-bit left-channel and right-channel sampling data (for example, in the case of a CD player, the sampling frequency is 44.1 kHz) to the input terminal IN serially. , Left channel data is BUS1 of data bus (11)
The data of the right channel is sent to BUS2 of the data bus (11), and the processed left channel data sent to the data bus BUS1 and the processed right channel data sent to the data bus BUS2 are sent. It receives and alternately outputs serially from the output terminal OUT. The interface circuit (13) sends and receives data between the DSP system and a microcomputer (not shown), and sends constants of the digital filter applied from the microcomputer to the data bus (11). , Receives the system status data and the like sent to the data bus (11) and sends them to the microcomputer.

The data processing circuit (9) is for left channel data processing, and the data processing circuit (10) is for right channel data processing. That is, the data processing circuits (9) (10) are connected to the data bus (11) and the data RAM.
(15), constant RAM (16), constant ROM (17), address pointers (18) (19) (20), multiplier (MUL) (21), ALU
(22), an accumulator (ACC) (23), and temporary registers (TMP1, TMP2, ...) (24). The data RAM (15) stores the data before processing and the data after arithmetic processing sent from the data input / output circuit (12) 24
It is a first RAM having a capacity of 128 bits and is connected to the input of the data bus (11) and the multiplier (21). Constant RAM
(16) is a 16-bit memory for storing constants such as digital filter coefficients sent from the interface circuit (13) ×
A second RAM having a capacity of 256, which is connected to the data bus (11) and the other input of the multiplier (21). The address pointer (18) consists of 8 bits and is a data RAM (15)
Addressing is performed, which is controlled by microcodes INC1 and DEC1 output from the control circuit (14) and has a function of incrementing (+1) and decrementing (-1) the held address data, It has a register that can set an arbitrary value by a program and a circuit that compares the set value with the address data. When the result of incrementing the address data exceeds the set value, it becomes "0" and the decrement result becomes "0". It has a function of becoming a set value when it becomes less than ", that is, a function of circulating between" 0 "and the set value. This circular addressing function is used to simplify the product-sum operation of digital filters. (Details will be described later.) In addition, the address pointer (1
9) is a 10-bit pointer that specifies the address of the constant RAM (16), and is controlled by the microcode INC2 output from the control circuit (14) to increment the address data and the control circuit (14). It has the function of being cleared to "0" by the microcode CLEAR2 output from. Furthermore, the address pointer (20) is a constant ROM
An 8-bit pointer for designating the address of (17), which is the microcode DEC3 output from the control circuit (14).
Has a function of decrementing address data.

The multiplier (21) performs multiplication of 24 bits × 16 bits, the A input is 24 bits and the B input is 16 bits, and the multiplication result is determined after one cycle. Furthermore,
The input selection circuit MPXA is used for the A and B inputs of the multiplier (21).
And MPXB are provided, and the input selection circuit MPXA is a control circuit (1
Data bus (1 by microcode A-BUS from 4)
Select 1) and use microcode A-DRAM to data RAM
(15) is selected and applied to the A input, and the input selection circuit MPXB
Selects the data bus (11) with the microcode B-BUS and the constant RAM (16) with the microcode B-CRAM.
And select the constant ROM (1
Select 7) and apply to the B input. The multiplication result is output in 32 bits.

The ALU (22) is a 32-bit arithmetic circuit, and the 32-bit multiplication result input to one side and the 32-bit arithmetic result input to the other side.
The data of ACC (23) is added by the microcode ADD and the result is transferred to ACC (23). ACC (23)
Of the 32 bits, the upper 24 bits are connected to the data bus (11) and the lower 8 bits are connected to the lower 8 bits of the temporary register (24) by the auxiliary bus (25). The temporary register (24) is composed of 32-bit registers TMP1, TMP2 ... TMP8, holds up to eight 32-bit data, and the upper 24 bits of each are connected to the data bus (11). The data bus (11) and the auxiliary bus (25) enable the temporary register (24) and
32-bit data is transferred between ACC (23).

The control circuit (14) is a program RO that stores the program.
M (26), program counter (PC) (27) that specifies the address of program ROM (26), and instruction decoder (I-DEC) (2) that decodes the read instruction.
8) and Program ROM (26) is 32 bits x 51
It has a capacity of 2 and stores a program for realizing a digital filter and other necessary programs. The instruction decoder (28) decodes an instruction and outputs a microcode, and controls the address pointers (18) (19) (20) INC1, INC2, DEC1, C.
It controls LEAR2, DEC3 and input selection circuits MPXA, MPXB. A
-BUS, A-DRAM, B-BUS, B-CRAM, B-CROM, or ALU
Outputs ADD, THR, etc. that control (22). Since this microcode is applied to a common circuit of each part of the data processing circuits (9) and (10), the same control is simultaneously performed on the data processing circuits (9) and (10) by executing one instruction. .

In the DSP system shown in FIG. 1, an example of the instructions necessary to configure the digital filter is shown in FIG.
In FIG. 2, the MUL instruction is a multiply instruction, and the multiplier (2
The object to be input to the input A and the input B of 1) is selected and multiplication is performed. The AP instruction increments, decrements or clears the address pointers (18) (19) (20). The ALU command is a control command for ALU (22), and ALUADD stores the two input data.
Add with ALU (22), hold the addition result in ACC (23),
ALUTHR uses the multiplication result from the multiplier (21) as it is to ACC
This is an instruction to be held by (23). RAM1D, TMP1D, TMP2D are store instructions, and data on the data bus (11)
It is stored in the RAM (15) and the temporary register (24). ACCS, TMP1S, TMP2S are transfer instructions, and ACC (2
3) is an instruction to send the data in the temporary register (24) to the data bus (11) and the auxiliary bus (25).

By the way, in the case of realizing a graphic equalizer in audio signal processing, y _i = x ₁ A + x _i-1 B + x _i-2 C + y _i-1 D + y _i-2 E (A, B, C, D, E is It is obtained by cascade-connecting a plurality of band digital filters realized by the sum of products operation represented by

FIG. 3 shows a two-band graphic equalizer realized by connecting two stages of band digital filters of a second-order direct IIR filter in cascade. In FIG. 3, (29) Z ^-1 is a delay element of unit time (sampling period in this case), (30) is a multiplication element of constants A to J, and (31) is an addition element. x _i is the input data input to the filter and z _i is the filter output. In the case of an audio system, such filtering must be performed on the left channel signal and the right channel signal, but in the DSP system shown in FIG. 1, a program that realizes the digital filter of FIG. Since the digital processing circuits (9) and (10) both perform the same operation by executing once, the filtering processing for the left channel signal and the right channel signal is performed at the same time.

Therefore, in the DSP system shown in FIG.
The operation for realizing the digital filter shown in FIGS. 4 and 5 is performed.
It will be described with reference to the drawings.

FIG. 4 is a diagram showing a program for realizing the digital filter of FIG. 3, and FIG. 5 is an allocation diagram of data stored in the data RAM (15) and the constant RAM (16).
By the program of Fig. 4, the multiplication of constants is performed by C, B, A, E, D,
In order to carry out in the order of H, G, F, J, I, constants are stored in the same order at addresses "0" to "9" of the constant RAM (16). On the other hand, the data RAM (15) contains 3 x _i , y _i , z _i data.
Although written at every address, x _{i + 1} , y _{i + 1} , z _{i + 1} are written by shifting one address for each sampling period, that is, for each filter processing period for one input data x _{i + 1} . The delay data is created by the delay element (29). Therefore, in the case of the digital filter shown in FIG. 3, the address pointer (18) has a value of "0" ...
The cyclic address designation of "7" and the address pointer (19) are set by the program so as to be the cyclic address designation of "0" to "9".

Here, when the step "0" of the program of FIG. 4 is executed for the input data x _i , the data RAM (1
When the contents of 5) are as shown in (a) of FIG. 5 and both address pointers (18) and (19) are address "0",
When the step "0" is executed, the input A of the multiplier (21) is input.
In and B, the data x _i-2 (input data two samples before) stored in the address “0” of the data RAM (15) and the coefficient stored in the address “0” of the constant RAM (16). Although C is applied, the multiplication result is determined and output in the next step. Also, at the end of step "0",
Address pointer (18) (19) by AP1INC and AP2INC
Are incremented together, and the content becomes "1".

When the step "1" is executed, the data RAM (15) and the constant RAM (16) are selected as the input of the multiplier (21) as in the step "0", and stored in the address "1" respectively. The data x _i-1 and the constant B are applied to the multiplier (21). In addition, the result of multiplication at the previous step "0" is the instruction AL.
The UTHR stores the first multiplication result C · x _{i−2 in} ACC (23) by passing it through ALU (22). At the end of step "1", the address pointer (1
8) (19) is incremented and the content becomes address "2".

Next, when step "2" is executed, the command MULA-BUS,
The B-CRAM selects the data bus (11) for the input A and the constant RAM (16) for the input B of the multiplier (21). On the other hand, the instruction TMP1S sends the contents of the temporary register TMP1 to the data bus (11), and the instruction RAM1D
The data sent to the data bus (11) is stored in the address "2" of the data RAM (15) designated by the address pointer (18). At this time, the temporary register TMP1 has a data input circuit (1
Input data x _i applied from the outside is stored in advance in 2). Therefore, the input data x _i is multiplied by the constant A read from the constant RAM (16) by the multiplier (21) and is stored in the address “2” of the data RAM (15). On the other hand, by the command ALUADD, the multiplication result B · x of C · x _i−2 stored in ACC (23) and step “1”
_i-1 is added, and as a result, B · x _i-1 + C · x _i-2 is ACC
Stored in (23). At the end of step "2", the address pointers (18) and (19) are incremented, and the content becomes the address "3".

When step "3" is executed, the input A of the multiplier (21) is input.
The data y _i-2 and the constant E stored in the address “3” of the data RAM (15) and the constant RAM (16) are applied to B and B, and the multiplication result A of the step “2” is given by the instruction ALUADD.
・ Contents of x _i and ACC (23) B ・ x _i-1 + C ・ x _i-2 is ALU (22)
The result of addition is A · x _i + B · x _i-1 + C · x
_i-2 is stored in ACC (23). At the end of step "3", the address pointers (18) and (19) are incremented to become the address "4".

When step "4" is executed, the input A of the multiplier (21)
The data y _i-1 stored at the address “4” of the data RAM (15) and the constant RAM (16) and the constant D are applied to B and B, and the multiplication result E of step “3” is given by the instruction ALUADD.
・ The contents of y _i-2 and ACC (23) A ・ x _i + B ・ x _i-1 + C ・ x _i-2
Are added in the ALU (22) and the addition result is A · x _i + B · x
_i-1 + C · x _i-2 + E · y _i-2 is stored in ACC (23).
At the end of step "4", the commands AP1DEC and AP2INC
The address pointer (18) is decremented to the address "3", and the address pointer (19) is incremented to the address "5".

When executed in step "5", input A of the multiplier (21)
In and B, the data y _i-2 stored in the address "3" of the data RAM (15) and the address "5" of the constant RAM (16) are stored.
The constant H stored in is applied. That is, the multiplier (2
In step 1), the second-stage multiplication of the digital filter shown in FIG. 3 is performed from step "5". Meanwhile, the instruction ALUADD
Results in multiplication result of step “4” D · y _i-1 and ACC (2
3) Content A ・ x _i + B ・ x _i-1 + C ・ x _i-2 + E ・ y _i-2 is ALU
It is added in (22), and the addition result is A · x _i + B · x _i-1 +
C · x _i-2 + D · y _i-1 + E · y _i-2 are stored in ACC (23). The content of ACC (23) at this time becomes the output y _i of the first-stage digital filter. At the end of step "5", the address pointer (18) is incremented to the address "4", and the address pointer (19) is incremented to the address "6".

When step "6" is executed, the input A of the multiplier (21) is input.
In and B, the data y _i-1 stored in the address “4” of the data RAM (15) and the address “6” of the constant RAM (16) are stored.
The constant G stored in is applied. Further, the instruction ACCS sends the data y _i stored in the ACC (23) to the data bus (11), and the instruction TMP2D sends the data bus (1
1) Data y _i sent to temporary register TMP2
Will be stored in. On the other hand, according to the instruction ALUTHR, the multiplication result H · y _i−2 in step “5” passes through ALU (22) and A
Stored in CC (23). At the end of step "6", the address pointers (18) and (19) are incremented to the addresses "5" and "7".

When step "7" is executed, the commands MULA-BUS, B-CRA
By M, the data sent to the data bus (11) and the constant F stored at the address "7" of the constant RAM (16) are applied to the inputs A and B of the multiplier (21). The data y _i stored in the temporary register TMP2 by the instruction TMP2S and RAM1D is sent to the data bus (11) and applied to the input A of the multiplier (21) and designated by the address pointer (18). The address "5" of the stored data RAM (15) is stored. On the other hand, by the instruction ALUADD, the multiplication result G · y _{i-1 in} step “6” and H · y _{i-2 in} ACC (23)
Are added in ALU (22), and as a result G · y _i-1 + H
・ Y _i-2 is stored in ACC (23). At the end of step "7", the address pointers (18) and (19) are incremented to address "6" and address "8".

When step “8” is executed, the input A of the multiplier (21) is input.
In and B, the data z _i-2 stored in the address “6” of the data RAM (15) and the address “8” of the constant RAM (16) are stored.
Stored in the constant J is applied, whereas ALU (22) the multiplication result of step "7" In F · y _i and ACC (23) to stored data _{G · y i-1 + H} · y i- ₂ is added, and as a result, F · y _i + G · y _i-1 + H · y _i-2 is stored in ACC (23). At the end of step "8", the address pointer (1
8) (19) is incremented to become address "7" and address "9".

When step "9" is executed, the input A of the multiplier (21) is input.
In and B, the data z _i-1 stored at the address “7” of the data RAM (15) and the address “9” of the constant RAM (16) are stored.
The constant I stored in is applied to the ALU (22) while the multiplication result J · z _i-2 and ACC (23) in step “8” are applied.
The data F · y _i + G · y _i-1 + H · y _i-2 stored in is added, and the addition result F · y _i + G · y _i-1 + H · y _i-2 + J · z
_i-2 is stored in ACC (22). When the address pointers (18) and (19) are incremented at the end of step "9", the address pointers (18) and (19) both become the address "0".

When step “10” is executed, multiplication is not performed, and the multiplication result I · z _{i−1 of} step “9” and the data F · y _i + G · y _i-1 + H · stored in ACC (23) are obtained. y _i-2 + J ・ z _i-2 is AL
It is added in U (22), and the addition result is F ・ y _i + G ・ y
_i-1 + H · y _i-2 + I · z _i-1 + J · z _i-2 is stored in ACC (23). The data of ACC (23) at this time becomes the output z _i of the second-stage digital filter.

Finally, when step "11" is executed, the instruction ACCS
Data z _i stored in ACC (23) is data bus (11)
The data z _i sent to the data bus (11) is stored in the address “0” of the data RAM (15) designated by the address pointer (18) by the instruction RAM1D.
At the end of step "11", the address pointer (18) is incremented to become the address "1". Therefore, when the program is executed again from step "0", the data RA addressed by the address pointer (18)
M (15) is to be accessed from address "1", which is one address ahead of the previous start address.

By executing the program of the above steps "0" to "11", the filtering process is performed on the input data x _i , the contents of the data RAM (15) are changed as shown in FIG. z _i is obtained. In addition, the delay data for the data x _{i + 1} can be obtained by advancing the start address by one address for the next filtering process of the sampling data x _{i + 1} . Therefore, steps "0"-
By repeatedly executing the program of "11" for the sampling data, the data RAM (15) is changed as shown in FIG. 5 (c) and (d), and the filter outputs z _{i + 1} and z _{i + 2} ……
Is obtained. Further, since the above-described operation is simultaneously performed in the digital processing circuits (9) and (10), the filter output data of the left channel and the right channel can be obtained at the same time. Furthermore, by changing the constants stored in the constant RAM (16) of the digital processing circuits (9) and (10) before executing the program of FIG. 4, the filter characteristics of the left channel and the right channel are changed. That is, the levels of the graphic equalizer can be left and right independent. In this case, the constant writing to the constant RAM (16) is performed by transferring the constant applied from the microcomputer to the interface circuit (13) to the constant RAM (16).

(G) Effect of the Invention As described above, according to the present invention, by executing a program for realizing a digital filter, one set of digital processing circuits operates at the same time, and one set of digital filters can be realized. The digital signal processing of the right and left channel audio signals can be performed with about half the conventional program length, which has the advantage of increasing the functions that can be realized during the sampling period. Therefore, an easy-to-use DSP device with improved throughput can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing instructions necessary for realizing a digital filter in the block diagram shown in FIG. 1, and FIG. 3 is connected in two stages. FIG. 4 is a diagram showing a second-order direct type IIR digital filter, FIG. 4 is a diagram showing a program for realizing the digital filter of FIG. 3 in the embodiment of FIG. 1, and FIG. 5 is a data RAM and a constant RAM. FIG. 6 is a block diagram showing a conventional example. (9) (10) ... Digital processing circuit, (12) ... Data input / output circuit, (13) ... Interface circuit, (14) ... Control circuit, (11) ... Data bus, (15) ... Data RAM, (1
6) ... Constant RAM, (17) ... Constant ROM, (18) (19) (20)
… Address pointer, (21)… Multiplier, (22)… ALU,
(23) ... Accumulator (ACC), (24) ... Temporary register, (25) ... Auxiliary bus, (26) ... Program
ROM, (27) ... Program counter, (28) ... Instruction decoder, (29) ... Delay element, (30) ... Multiplication element, (31) ... Addition element.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G10K 15/12 H03H 17/02 K 8842-5J H04S 1/00 K (72) Inventor Masaki Kawaguchi Osaka 2-18 Keihanhondori, Moriguchi, Sanyo Electric Co., Ltd. (56) Reference JP 62-284510 (JP, A) JP 63-113756 (JP, A) JP 63-266576 (JP , A) JP 60-5339 (JP, A) JP 63-292716 (JP, A) JP 63-221708 (JP, A) JP 63-264000 (JP, A) JP 63-264799 (JP, A) JP-A-63-254513 (JP, A) JP-A-2-236693 (JP, A)

Claims (1)

[Claims] 1. A first RAM for storing a plurality of input digital data and operation result data corresponding to a stereo audio signal having two left and right channels, and a second RAM for storing a plurality of constants for realizing a digital filter. RAM
A first data pointer for designating an address of the first RAM, and a second data pointer for designating an address of the second RAM.
A data pointer, and a multiplier (MUL) for multiplying the data read from the first RAM and the second RAM,
A digital signal processing circuit, which has at least an arithmetic circuit (ALU) for operating the multiplication result of the multiplier and the operation result held in the accumulator and holding the operation result in the accumulator, includes a left channel and a right channel of the audio signal. A pair is provided corresponding to each channel, and an interface is provided between the pair of digital signal processing circuits and the microcomputer, and the pair of second digital signals in the pair of digital signal processing circuits is provided from the microcomputer. An interface circuit for sending a plurality of constants respectively corresponding to the characteristics of the left channel and the right channel of the audio signal to the RAM is provided, and the pair of digital signal processing circuits is provided with one command from a preprogrammed program memory. It is the same in the control circuit that decodes and outputs the control signal. And controls the at the pair of digital signal processing circuit, a digital signal processing apparatus characterized by different signal processing in accordance with the characteristics of the left and right channels of the audio signal can be executed simultaneously.