JPH0697554B2 - Serial access memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (first in first out) type serial access memory used as a storage element of a digital TV or a digital VTR.

Conventional technology In recent years, digital technology has been adopted for higher image quality and higher functionality in TV systems and VTR systems. Therefore, a line memory for storing digital video signals for several scanning lines or a field memory for storing one field,
A frame memory for storing one frame is required, and the demand for a FIFO type serial access memory among the above various memories has increased.

The conventional FIFO type serial access memory will be described below. FIG. 3 is a diagram showing the structure of a conventional FIFO type serial access memory. The first input latch 1 and the second input latch 2 are latches for n words of input data, respectively, and the first output latch 4 and the second output latch 5 are latches for n words of output data, respectively. The input switch 7 has a function of transferring input data to the first input latch 1 word by word, and the output switch 8 has a function of transferring data of the first output latch 4 word by word. The write circuit 9 has a function of writing the data of the second input latch 2 to the memory block 10, and the read circuit 11 is a memory block.
It has a function of reading from 10 to the second output latch 5. Also,
Write address pointer 12, Read address pointer 13
Selects the word line of the memory cell of the memory block 10 to be written or read. The input switch 7 sequentially transfers the input data word by word to the first input latch 1 every cycle time T. First input latch 1
Data is transferred from the first input latch 1 to the second input latch 2 at the time when all the data for n words have been written into. The data transferred to the second input latch 2 is written in the memory cell selected by the write address pointer 12 by the write circuit 9 during the cycle time of nT.
It operates as follows on the output side. During the nT cycle time, the read circuit 11 causes the read address pointer 13
The data of the memory cell selected in step n is read by the second output latch 5 for n words. The data of the first output latch 4 is sequentially set to 1 by the output switch 8 every cycle time T.
Words are transferred and output word by word, and when the transfer of all n words is completed, the next n words of data are transferred from the second output latch 5 to the first output latch 4.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above configuration, in order to reset the read address and read from the leading address, n cycles are required to read the data of the leading n words from the memory cell to the second output latch 5. You have to put a reset in advance.

Also, in order to secure sufficient time for writing to the memory cell, the reset interval from the reset on the write side is
It must be an integer multiple of nT, which greatly limits the reset timing. In the data transfer from the first input latch 1 to the second input latch 2 and the data transfer from the second output latch 5 to the first output latch 4, a large instantaneous current is applied in order to transfer n words of data quickly. It also has the drawback of occurring.

The present invention solves the above-mentioned conventional problems. When a reset input is input, the FIFO address can be immediately returned to the start address for reading / writing, and the position of the reset input can be stably operated with low power consumption. It is intended to provide a form of serial access memory.

Means for Solving the Problems In order to achieve this object, the serial access memory of the present invention uses a first input latch for latching the first address n words of the input data and input data of the subsequent addresses. The second and third input latches that are alternately latched, the input switch that selects one of the first, second and third input latches according to the address to transfer the input data, and the start address of the output data A first output latch for latching n words, second and third output latches for alternately latching output data of subsequent addresses, and first, second, and third outputs corresponding to addresses An output switch that selects one of the latches and transfers the data, and the data of the first input latch is transferred to the first output latch, and the data of the second and third input latches are transferred to the memory block alternately. Writing And viewing the circuit has a configuration that includes a readout circuit for reading out the second, third output latch alternately first n words after the address of the read data from the memory block.

Operation With this configuration, in writing, n words immediately after resetting are transferred to the first input latch by the input switch by the input switch, and during this time, the second or third input is being written into the memory cell until just before resetting. The data transfer from the latch is completed, and the data of the second or third input latch that has been transferring the input data is written in the memory block, and after n words from the reset, the input switches have the second and third input switches. The input latches are alternately selected n words at a time to transfer the input data, and the data of the input latches not selected by the input switch are written to the memory cells by the write circuit, thereby immediately returning to the start address immediately after reset. It becomes possible to write by writing, and writing to the subsequent addresses is also input It is possible without the data transfer from the latch to the input latch.

In reading, for n words immediately after resetting, the n-word data stored in the first output latch is read by the output switch, and the read data at the address following the first n words is read during the second or third output latch. Read out by the read circuit, then alternately read the data from the memory block to the second or third output latches, and select the output latches which have not been read out alternately by the output switch to transfer the data to the outside. As a result, immediately after resetting, it is possible to return to the head address and perform reading, and subsequent reading is also possible without performing data transfer between output latches.

Further, since the data transfer from the first input latch to the first output latch is performed through the data line of the memory block, a special data bus for this data transfer is not required, and the serial access memory It has become possible to reduce the chip area.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a serial access memory according to an embodiment of the present invention. Both input data and output data are 4-bit parallel output, and the first input latch 1, the second input latch 2, the third input latch 3, the first output latch 4, the second output latch 5, and the third output latch 6 are each It is a 4-bit x 8-word latch. The input switch 7 and the output switch 8 are high-speed switches that sufficiently follow the data rates of input data and output data. The memory cell is a 3-transistor dynamic memory cell for realizing asynchronous read and write operations, and has a write word line, a read word line, a write data bus, and a read data bus independently. Memory cells of 4 × 8 bits are arranged in the vertical direction of the memory block 10, and each word line runs in this direction. The word line is formed of a polysilicon layer and has a high resistance, so that the delay is large. Each address pointer 12, 13 selects each word line in turn every eight cycles and is returned to the first word line by an external reset input. A data bus runs in the lateral direction of the memory block 10.

The operation of the serial access memory of this embodiment having the above configuration will be described below. 2 shows the input latch selection signal of the input switch 7 (FIG. 2a), the write selection signal of the write circuit 9 (FIG. 2b), the output latch selection signal of the output switch 8 (FIG. 2c), and the read circuit. 11
The respective timings of the read selection signal (FIG. 2d) are shown. In writing, the 8-word input data immediately after reset is transferred to the first input latch 1 by the input switch 7, the next 8-word input data is transferred to the second input latch 2, and the next 8-word input data is transferred. Transfers the input data to the third input latch 3 and then transfers the input data to the second input latch 3 and the third input latch 3 alternately every 8 words. The data written to the first input latch 1 is 9-
The data is transferred to the first output latch 4 by the write circuit 9 through the write bus in 13 to 16 of 16 cycles.
The data of the second input latch 2 and the third input latch 3 is 4 in the latter half of the cycle which is not selected by the input switch 7.
In the cycle, the write circuit 9 writes data to the memory cells sharing the write word line selected by the write address pointer 12. Immediately after reset,
Data is transferred from the input latch to the memory cell at the time of resetting for 1 to 4 cycles, and the data of the input latch selected by the input switch 7 immediately before the reset is written to the memory cell for 5 to 8 cycles. Do it during the cycle.

For reading, data of eight cycles immediately after reset is selected by the output switch 8 by the first output latch 4 and read, and during this time, a memory cell having data of the next nine to sixteen cycles is selected by the read address pointer 13 and read. The second output latch 5 is read by the circuit 11. In 9 to 16 cycles, the output switch 8 is the second
Selects and reads the data in the output latch 5, while reading the output data of the next 17 to 24 cycles during this period.
The data is read from the memory cell to the third output latch 6 by 11. Thereafter, the second output latch 5 and the third output latch 6 alternately perform data transfer from the memory cell and data output to the outside.

As described above, according to the present embodiment, by independently providing the latches for the leading 8 words for input and output, it is possible to return to the leading address immediately after receiving the reset, and to perform the input / output. It became possible to remove the timing constraint. Furthermore, by providing two latches each having 8 words for input and output and alternately performing input or output with the outside and input or output with the memory cell, a high-speed serial access memory with low current consumption can be realized. .

In this embodiment, the memory cell is composed of a dynamic memory cell of three transistors and the asynchronous operation of writing and reading is realized. However, by providing a competition adjusting means for writing and reading to and from the memory cell, one transistor It goes without saying that it can also be realized by a dynamic memory cell. Further, although the latch of 8 words is used in this embodiment, it can be configured by a latch of another word number.

EFFECTS OF THE INVENTION The present invention provides data latches for the first n words of input and output, and two n-word input latches and two output latches separately from the data latches. Data can be input / output, and the serial access memory can be realized with a restriction on the timing of resetting. Further, by using two input latches and two output latches to control the input switch and the write circuit, and the output switch and the read circuit, alternate input or output with the outside and input or output with the memory cell are performed. As a result, a low power consumption serial access memory can be realized. Further, by performing data transfer between the input latch and the output latch for the first n words through the data bus of the memory cell, a special data bus for this data transfer is not required, and the chip area of the serial access memory is suppressed to a low level. It has become possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial access memory according to an embodiment of the present invention, FIG. 2 is a timing diagram thereof, and FIG. 3 is a block diagram of a conventional serial access memory. 1 ... 1st input latch, 2 ... 2nd input latch, 3 ...
Third input latch, 4 ... First output latch, 5 ... Second output latch, 6 ... Third output latch, 7 ... Input switch, 8 ... Output switch, 9 ... Writing circuit, 10 ...
Memory block, 11 ... Read circuit, 12 ... Write address pointer, 13 ... Read address pointer.

Claims (2)

[Claims] 1. A first input latch having a memory block which is connected to a word line and a data line orthogonal to the word line and which is two-dimensionally arranged, and latches a leading address n words of input data. The second and third input latches that alternately latch the input data of the subsequent addresses n words at a time, and the one of the first, second, and third input latches corresponding to the write address are selected and input. An input switch for transferring data, a first output latch for latching n words of the start address of output data, and second and third output latches for alternately latching output data of subsequent addresses n words at a time , An output switch for outputting data by selecting any one of the first, second, and third output latches corresponding to an address, and the data of the first input latch for the first switch.
Write latch for transferring the data of the second and third input latches to the memory block alternately, and read data of addresses from the first n words onward from the memory block alternately. A serial access memory having a read circuit for reading data from the second and third output latches. 2. The serial access memory according to claim 1, wherein the data transfer from the first input latch to the first output latch is performed through the data line of the memory block.