JPH0697708B2 - Semiconductor light emitting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor light emitting device, the present invention provides a high resistance buried layer with a groove formed to reach a substrate from a surface to form a mesa including a striped light emitting region. With a semiconductor layer of the same conductivity type as the high resistance buried layer formed over the entire surface in contact with the surface of the high resistance buried layer and the surface of the mesa, and the depth reaching from the surface of the semiconductor layer to its base. A stripe-shaped impurity region having a width not exceeding both outer ends of the high-resistance buried layer and having a conductivity type opposite to that of the semiconductor layer and the high-resistance buried layer is formed, and is formed on the stripe-shaped impurity region. By forming the electrode to be in contact with the high resistance buried layer, even if the electrode is widely formed, as long as it exists on the impurity region, the high resistance buried layer is not contacted. Therefore, it is possible to reduce the threshold current and improve the cut-off frequency without causing any leak current, so that stable laser oscillation can be performed, and the surface is flat and the electrode width is wide. It is easy to manufacture and has good heat dissipation when attached to a heat sink.

[Industrial application field]

The present invention relates to an improvement in a buried semiconductor light emitting device having a so-called double channel (double groove) in which a stripe-shaped current limiting layer is formed on both sides of a light emitting region.

[Conventional technology]

FIG. 6 shows a cutaway front view of a main part of a conventional embedded semiconductor light emitting device.

In the figure, 1 is an n ⁺ type InP substrate, 2 is an n type InGaAsP active layer, 2A is a striped light emitting region which is a part of the n type InGaAsP active layer 2, 3 is a p type InP clad layer, and 4 is n. ^- -type InP high-resistance burying layer, 5 a p-side electrode made of Ti / Pt / Au, is 6 Au
-The n-side electrodes made of Ge are shown.

In order to perform the laser operation of this conventional example, a forward bias voltage is applied to the heterojunction diode formed by the stripe-shaped light emitting region 2A which is a part of the n-type InGaAsP active layer 2 and the p-type InP clad layer 3, In particular, stripe light emitting area
This is done by injecting current into 2A.

In the semiconductor light emitting device having such a structure, in order to improve the laser characteristics, it is necessary to suppress the current that does not pass through the stripe light emitting region 2A, that is, the leakage current as much as possible.

In this case, the leakage current is suppressed mainly by p-type In.
This is done by utilizing the fact that the forward rising voltage of the pn junction diode composed of the P clad layer 3 and the n ⁻ type InP high resistance buried layer 4 is higher than that of the hetero junction diode.

In this conventional example, when a non-defective product is obtained, light confinement and current confinement are excellently performed and excellent properties are exhibited, but it is very difficult to manufacture a non-defective product with good reproducibility.

FIG. 7 is a cutaway front view of a main part for explaining the drawbacks of the conventional example described with reference to FIG. 6, and the same symbols as those used in FIG. 6 represent the same parts or have the same meanings. I shall.

In this conventional example, the width of the p-side electrode 5 is wider than that shown in FIG. 6, so that the n ⁻ -type InP high resistance buried layer 4 is formed.
I am also in contact with.

With such a configuration, as indicated by the arrow,
A large amount of leakage current i _L that does not pass through the pn junction diode as well as the hetero junction diode flows, and laser oscillation becomes impossible.

Therefore, in the semiconductor light emitting device of the type as shown in FIG. 6, the p-type InP clad layer 3 in the portion forming the mesa by the groove filled with the n ⁻ -type InP high-resistance buried layer 4 is formed. It is necessary to form the p-side electrode 5 only immediately above.

[Problems to be solved by the invention]

Generally, in a semiconductor light emitting device, in order to stably oscillate a laser, the width of the stripe-shaped light emitting region 2A is 1.5
[Μm] or less is necessary, and applying the conventional technique as described with reference to FIG. 6 to the semiconductor light emitting device having such a narrow light emitting region 2A is not necessary in the research stage, but is in mass production. In the stage, it is difficult as it is almost impossible, and if the width of the electrode is narrow, good heat dissipation cannot be achieved even if the semiconductor light emitting device is mounted on the heat sink, and the groove is filled up again. It is actually difficult to form a high resistance buried layer and planarize the surface as it is.

According to the present invention, a semiconductor light emitting device can be easily manufactured and its heat dissipation can be improved. Therefore, even if the width of the electrode is widened, an increase in leakage current is not caused and the surface is flattened. Make it easy.

[Means for solving problems]

In the semiconductor light emitting device according to the present invention, the active layer (for example, n-type
In order to make the semiconductor layers laminated including the InGaAsP active layer 8) into stripe-shaped mesas, a substrate (for example, n ⁺ type) is formed from the surface.
Two grooves (for example, groove 10) formed until reaching the InP substrate 7) and a high-resistance buried layer (for example, n ⁻ -type InP high-resistance buried layer 10A) that fills the two grooves and has a substantially flat surface. )
A semiconductor layer (for example, an n-type InP layer 11) which is formed over the entire surface in contact with the surface of the high resistance buried layer and the surface of the mesa and has the same conductivity type as the high resistance buried layer, and from the surface of the semiconductor layer It has a depth reaching the underlying layer (for example, p-type InP clad layer 9) and a width that does not exceed both outer ends of the two high-resistance buried layers, and has a conductivity type opposite to that of the semiconductor layer and the high-resistance buried layer. a stripe-shaped impurity region having (e.g. p ⁺ -type impurity region 12), the provided comprising constituting the stripe electrodes that contact is formed on the stripe-shaped impurity regions on (e.g. p-side electrode 13) take the ing.

[Action]

By adopting the above means, even if the electrode is located on the high resistance buried layer in plan view, an impurity region having a conductivity type opposite to that of the high resistance buried layer exists between the electrode and the high resistance layer. Therefore, it is much easier for the current to flow to the mesa portion than to flow into the substrate through the route of the impurity region-high resistance buried layer, so that a large leakage current as in the conventional semiconductor light emitting device is generated. As a result, the threshold current can be reduced, the cut-off frequency can be improved, stable laser oscillation can be performed, and the electrode can be widely formed, which facilitates the manufacturing. Becomes
The heat dissipation is also good, and the surface is flattened because the semiconductor layer is present on top of the high resistance buried layer.

〔Example〕

1 to 5 are sectional front views of a main part of a semiconductor light emitting device in a process key point for explaining an embodiment of the present invention,
Hereinafter, description will be given with reference to these drawings.

See Fig. 1 (1) For example, liquid phase epitaxial growth (liquid phase)
epitaxy: LPE) is applied to form an n-type I on the n ⁺ -type InP substrate 7.
The nGaAsP active layer 8 and the n-type InP clad layer 9 are grown in this order.

Here, an example of main data of each part is as follows.

(A) About n-type InP substrate 7 Thickness: 500 [μm] Size: 20 × 20 [mm ² ] Surface index: (100) Impurity: Sn Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ] (b) n ^- type InGaAsP active layer 8 thickness: 0.5 [μm] (c) n-type InP clad layer 9 thickness: up to 3 [μm] Impurity: Sn Impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] second See FIG. (2) For example, a sputtering method is applied to form an insulating film made of SiO ₂ to a thickness of, for example, about 3000 [Å].

(3) By applying a normal photolithography technique, the insulating film is etched to provide an opening necessary for forming a groove for burying a high resistance burying layer. In this case, HF: NH ₄ F = 1: 10 may be used as the etching solution.

(4) By applying a normal photolithography technique, etching is performed from the n-type InP clad layer 9 on the surface to the n ⁺ -type Inp substrate 7 by using the insulating film having the opening as a mask to form the groove 10.

The following is an example of data used to form the groove 10.

Etching solution: Br ₂ : HBr: H ₂ O = 1: 17: 34 Width of central stripe part: 1.5 [μm] Width of groove 10: ~ 9 [μm] Depth of groove 10: ~ 5 [μm] ( 5) For example, the VPE method is applied to form the n ⁻ -type InP high resistance burying layer 10A filling the groove 10.

The resistivity of the n ⁻ type InP high resistance buried layer 10A is about 10 ⁴ (Ω · cm) as in the case of the conventional technique, and the growth is such that the groove 10 is completely filled and the surface is Stop when it becomes flat.

(6) The insulating film made of SiO ₂ used as the mask is removed.

See Fig. 3 (7) LPE method or VPE method is applied, and the thickness is about 1 [μm].
The n-type InP layer 11 having a certain degree is formed.

See FIG. 4 (8) By applying the sputtering method again, an insulating film made of, for example, SiO _{2 is} formed to a thickness of about 3000 [Å].

(9) The conventional photolithography technique is applied to pattern the insulating film, and the width of the n ^- type InP is two.
Striped openings are formed to the extent that they do not exceed both outer ends of the high resistance buried layer 10A. The width of the stripe-shaped opening is usually about 3 [μm].

(10) The ion implantation method is applied, and Be is dosed at 1 × 10 5 with the insulating film having the stripe-shaped opening as a mask.
Implanting about ¹⁵ [cm ⁻² ] to form a P ⁺ -type impurity region 12 having a depth reaching the n-type InP clad layer 9 from the surface, for example, about 1 μm.

This ion implantation is sufficient even if a part of the n ⁻ type high resistance buried layer 10A appearing on the surface is inverted to p ⁻ type.

See FIG. 5 (11) The p-side electrode 13 and the n-side electrode 14 are formed by applying a normal technique such as a vapor deposition method, a photolithography technique, or an alloying method. Of course, it is necessary that the width of the p-side electrode 13 does not exceed both outer ends of the P ⁺ -type impurity region 12.

In this case, the p-side electrode 13 is Ti / Pt / Au, and the n-side electrode 14 is Au.
It can be configured using each Ge.

After that, the process is completed through a normal process such as cleavage of the end face of the resonator.

The semiconductor light emitting device completed as described above has a resonator length: 300 [μm] average threshold current I _th : 16 [mA] cut-off frequency: 2.1 [GHz] I _d / I _th = 1.05 3 [dB] A down value was obtained.

The reason why such excellent characteristics are obtained is that the pn junction diode formed by the p ⁺ type impurity region 12 and the n ⁻ type InP high resistance buried layer 10A, the p ⁺ type impurity region 12 and the n type InP layer 11 are formed. This is due to the current blocking effect of the generated pn junction diode.

For comparison, a semiconductor light emitting device of the type shown in FIG. 6 was simultaneously made with the same dimensions, and the average threshold current I _th : 18 [mA] cut-off frequency: 1.3 [GHz] I _d / I _th = 1.05 Met.

In the above embodiment, the semiconductor light-emitting device is intended for those conventional construction, for example, can be carried out like that of a distributed feedback type having a diffraction grating is of course, also, p ⁺ -type impurity In addition to the ion implantation method, a usual diffusion method can be applied to form the region 12.

〔The invention's effect〕

In the semiconductor light emitting device according to the present invention, a groove formed so as to reach the substrate from the surface is filled with a high resistance buried layer to form a mesa including a stripe-shaped light emitting region, and the high resistance buried layer is formed. A semiconductor layer of the same conductivity type as the high resistance buried layer formed over the entire surface in contact with the surface and the surface of the mesa, and a depth from the surface of the semiconductor layer to the base and both outer ends of the high resistance buried layer. A stripe-shaped impurity region having a conductivity type opposite to that of the semiconductor layer and the high-resistance buried layer and having a width not exceeding the width, and an electrode formed on the stripe-shaped impurity region and in contact with the impurity region is formed. I am collecting.

By adopting such a configuration, even if a striped electrode is formed widely, as long as it exists on the striped impurity region, there is no contact with the high resistance buried layer, As a result, a large leakage current is not generated, therefore, the threshold current can be reduced and the cut-off frequency can be improved, stable laser oscillation can be performed, and the surface is flat and the width of the electrode is small. Its wide size makes it easy to manufacture and has good heat dissipation when attached to a heat sink.

[Brief description of drawings]

1 to 5 are front views of a semiconductor light emitting device in a principal part of a manufacturing process according to an embodiment of the present invention, and FIG. 6 is a front view of a main part in a conventional example. , 7th
The figures respectively show cut-away front views for explaining the drawbacks of the conventional example. In the figure, 7 is an n ⁺ type InP substrate, 8 is an n type InGaAsP active layer, 8A is a striped light emitting region which is a part of the n type InGaAsP active layer 8, 9 is a p type InP clad layer, and 10 is Groove, 10A
N ⁻ type InP high resistance buried layer, 11 is n type InP layer, 12 is p ⁺ type impurity region, 13 is p side electrode, and 14 is n side electrode.

Claims (1)

[Claims] 1. Two grooves formed to reach a substrate from a surface to form semiconductor layers laminated including an active layer into a stripe mesa, and the two grooves are filled with the surface. A flat high resistance buried layer, a semiconductor layer formed on the entire surface in contact with the surface of the high resistance buried layer and the surface of the mesa, and having the same conductivity type as the high resistance buried layer; Stripe-shaped impurity regions having a depth reaching the base and a width not exceeding both outer ends of the two high-resistance burying layers and having a conductivity type opposite to those of the semiconductor layer and the high-resistance burying layers; A semiconductor light emitting device, comprising: a striped electrode formed on and in contact with a striped impurity region.