JPH0697780B2 - Encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an encoding device for encoding image data.

[Prior Art] In recent years, a facsimile machine using a public telephone line network as a transmission line has become widespread.
Many of them comply with CCITT (International Telegraph and Telephone Advisory Committee) recommendations, and the one with the highest transmission efficiency is the recommendation.
It is a Group 3 (G3) facsimile machine specified in T.4.

This G3 facsimile machine is an MH which is a one-dimensional encoding system.
(Modified Huffman) method or 2D encoding method
By using the MR (Modified READ) encoding method, the image signal is encoded and compressed to shorten the transmission time. Generally, the two-dimensional coding system has a higher coding compression efficiency than the one-dimensional coding system, and thus the fax machine capable of selecting the two-dimensional coding system has a higher transmission efficiency.

Such an encoding process is composed of, for example, a general-purpose microcomputer system or a system using a microprogram sequencer so that the amount of data to be processed is very large and the processing speed can correspond to the transmission speed of the facsimile machine. It is made by a dedicated encoding device.

By the way, in the above-mentioned two-dimensional encoding method according to CCITT recommendation T.4, in order to limit a portion disturbed by a transmission error, one line is one-dimensionally encoded and then a maximum of K-1 consecutive lines are transmitted. Is determined to be two-dimensionally encoded, and the data of the one-dimensionally encoded line is used as a reference line of the two-dimensionally encoded line. The value of the K parameter is set to 2 for standard resolution and 4 for high resolution.

In this way, the one-dimensional encoding process is performed even when the image is compressed by the two-dimensional encoding method. Also,
Even in the two-dimensional encoding process, depending on the state of the image signal, the image is encoded in the horizontal mode using the MH code.

For this reason, the encoding apparatus separately includes a processing unit (processing routine) for realizing the one-dimensional encoding method and a processing unit (processing routine) for realizing the two-dimensional encoding method. There has been a problem that the size of the processing program is increased and the processing speed is not so fast.

[Object] The present invention has been made in order to solve the above-mentioned problems of the conventional technique, and an object of the present invention is to provide an encoding device capable of increasing the processing speed.

[Structure] In order to achieve this object, the present invention performs a coding procedure process and generates a two-dimensional code, a micro program sequencer, a code discriminating means for performing run length counting and code mode detection, and a run length. To a run-length code generating means for generating a run-length code corresponding to, a mode signal output from the code discriminating means when a code mode is detected is input as a microprogram address, and processing corresponding thereto is performed. The processing speed is improved by branching to the routine and generating the corresponding code.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an encoding device 1 according to an embodiment of the present invention. It should be noted that this embodiment is applied to a facsimile apparatus or the like provided with a control device constituted by a microcomputer system having a 16-bit width data bus, and therefore, the image data to be processed and the coded data after the processing are both 16 It has been formatted into bits.

In the figure, an encoding device 1 includes an input / output unit 100 for inputting / outputting data to / from a data bus, a data generating unit for discriminating a run length and a code mode (described later) of input image data and generating an MH code. 200, and performs MP processing and other control processing and MP
It is composed of a microprogram sequencer 300 that generates a code.

The input / output unit 100 includes a latch circuit 101 for inputting the image data DI shaped into 16 bits, an image data interface circuit 102 for controlling the input timing of the image data DI, and a serial for shaping the encoded data DC to be output into 16 bits. /
It is composed of a parallel converter 103 and an encoded data interface circuit 104.

The data generator 200 counts the run length of the image data DI input from the latch circuit 101, and when the two-dimensional coding mode is set, determines the coding mode based on the correlation with the reference line. Run length counting two-dimensional mode detection circuit 201 and run length data DRL output from run length counting two-dimensional mode detection circuit 201
MH coded ROM (read only memory) 202 for generating MH coded data DMH corresponding to, a gate circuit for selecting either MH coded data DMH or MR coded data DMR output from the microprogram sequencer 300. 20
3, 204 and a parallel / serial converter 205 for temporarily storing variable-length code data output via the gate circuits 203, 204 and then transferring the code data to the serial / parallel converter 103.

The run-length counting two-dimensional mode detection circuit 201 starts its operation when the signal RLGO is output from the microprogram sequencer 300. When the signal RL / MODE output from the micro program sequencer 300 is in the signal RL state of the logic level H, the signal R is sent to the micro program sequencer 300 every time the run length is determined.
Signal MODE with logic level L when RLDY is responded and signal RL / MODE is
In the state, the signal RLRDY is responded each time the code mode is determined, and at the same time, the mode data DM representing the code mode is output to the microprogram sequencer 300. Further, when the processing of the image data DI for one line is completed, the signal LE is output to the micro program sequencer 300.

The microprogram sequencer 300 executes 1 word 21
A microprogram ROM 301 that stores 1024 words of microprograms of bits, a 21-bit pipeline register 302 that stores the execution instruction output from the microprogram ROM 301, and a 10-bit pipe that stores the address of the instruction to be executed in the next microcycle. Line register 303,
An incrementer 304 for generating an address of an instruction to be executed in the second micro cycle from that point, a 10-bit micro program counter register 305 that stores the output of the incrementer 304, and a transition to a subroutine by a condition call, etc. A stack 306 for storing a return address to the main routine after the subroutine is finished, a stack pointer 307 indicating the top of the stack 306, mode data DM output from the run-length counting two-dimensional mode detection circuit 201, and a pipe. Line register 302
The branch address output from the stack, the output of the stack 306, and the output of the microprogram counter register 305 are added to the input ends A, B, C, and D, respectively, and a multiplexer 308 that outputs one of them from the output end Y. , The multiplexer 308 corresponding to the 2-bit sequencer command SC output from the pipeline register 302, the 1-bit test data TD output from the multiplexer 309, and the upper 3-bit data CS of the branch address.
Instruction decoder that outputs a 2-bit selection signal SL for setting the selection of the stack and a 2-bit active signal AT for controlling the stack 306 and the stack pointer 307
It consists of 310.

In this way, the micro program sequencer 300
It has a level pipeline structure. Further, the multiplexer 309 is added with 6 bits of the output of the pipeline register 302 as a selection signal, selects one of 64 input terminals and outputs it as test data to the instruction decoder 310. The signals input to the multiplexer 309 include, for example, the signals LE and RLRDY output from the run-length counting two-dimensional mode detection circuit 201.

By the way, in the microprogram sequencer 300, the 21-bit microprogram is divided into four modes according to the upper 2 bits, and the relationship between the states of the upper 2 bits and each mode is shown in Table 1 below.

The sequencer command SC added to the instruction decoder 310 is the data of bit 18 and bit 17, which is common to each mode. Here, the sequencer command SC and the instruction decoder 310
Table 2 shows the relationship of the outputs of the above.

Mode 0 is a mode in which a conditional jump is performed depending on the state of the data output from the multiplexer 309.
16 to 0 are assigned as shown in Table 3.

Here, the upper 3 bits of the branch address A _{9 to} A ₀ , that is, the data CS is the run length counting two-dimensional mode detection circuit.
201 detects run length or code mode and signal R
All bits are set to 1 when LRDY is output, that is, when the mode data DM is selected when the condition is satisfied by the conditional jump instruction. The most significant bit of the test address sets whether the condition is true (T) or false (F) is determined. For example, when the multiplexer 309 performs an exclusive OR with the output. Which is the other signal, and the result of the exclusive OR is output from the output terminal of the multiplexer 309.

Mode 1 is a mode in which constant data such as code data is set in the output, and bits 16 to 0 are assigned as shown in Table 4.

Here, the address corresponds to the output destination of the constant data, and is used as an enable signal in, for example, a latch circuit (not shown) that latches the signal RLGO. The constant data also includes the signal RL / MODE. Also, in mode 1, the pipeline register 302 outputs MR to the gate 204.
Code data DMR is output and serial / parallel converter 2
Latch to 05. Note that bit 4 is not used in this mode 1.

Mode 2 is for performing, for example, data transfer between registers and set / reset of a flag flip-flop (hereinafter referred to as F / F), and bits 16 to 0 are assigned as shown in Table 5 below.

Here, T / M is a signal for selecting whether to generate a terminating code or a makeup code in the MH encoding ROM 202. Of the F / F control signals, A, B, C, D indicate the F / F address, and R, S indicate the reset signal and the set signal. In addition, the pixel described later
When inverting the color of a ₀ inverts gives a set signal and a reset signal to the F / F that holds the color of the pixel a ₀ at the same time. S.ADR. And D.ADR. Are the source (Source) and the receiver (Dest) of the data in the register that transfers the data, respectively.
ination) address. In this mode 2, bit 16 and bit 15 are not used.

Mode 3 is a mode in which the serial / parallel converter 103 and the parallel / serial converter 205 are shifted, and a counter for storing the shift numbers of these serial / parallel converter 103 and parallel / serial converter 205 is enabled. Yes, bits 16-0 are assigned as in Table 6 below.

Here, the signals SEL of bits 16 and 15 are the gate circuits 203 and 204.
Is a signal for enabling any of the above to select the data to be set in the parallel / serial converter 205. In addition, other control signals include counter enable signals, serial / parallel converter 103, and parallel / parallel converters.
The shift signal of serial converter 205 is included.

Each of these modes is appropriately selected and the microprogram is appropriately executed.

Next, the encoding process by this encoding device will be described. In the following description, processing at a higher level rather than the microprogram level will be described.

Here, some terms relating to the encoding process used in the following description will be described. Note that these terms are CCITT
As defined in Recommendation T.4.

(I) Change Pixel The change pixel a ₀ is a reference or starting point change pixel on the coding line, and at the beginning of the coding line, the change pixel a ₀ is on the virtual white change pixel immediately before the first pixel of the line. The position of the changing pixel a ₀ , which is placed during the coding of the coding line, is defined by the immediately preceding coding mode.

The change pixel a ₁ is the first change pixel to the right of the change pixel a ₀ on the coding line.

The change pixel a ₂ is the first change pixel on the coding line to the right of the change pixel a ₁ .

Change pixel b ₀ is the first changing pixel with opposite color and the change pixel a ₀ from the right change pixel a ₀ on the reference line.

The change pixel b ₁ is the first change pixel to the right of the change pixel b ₀ on the reference line.

(Ii) Code (encoding) mode The pass mode is defined by the presence of the change pixel b ₂ on the left side of the change pixel a ₁ . When encoding this mode,
In preparation for the next encoding, the changing pixel a ₀ is set on the pixel on the encoding line immediately below the changing pixel b ₂ .

In the vertical mode, the position of the changing pixel a ₁ is encoded by the relative position from the changing pixel b ₁ . Relative distance a ₁ b ₁ is represented by 7 different values V 0, V _R 1, V _R 2, V _R 3, V _L 1, V
Takes either _L 2 or V _L 3. The subscripts _R and _L respectively indicate whether the changed pixel a ₁ is on the right side or the left side of the changed pixel b ₁ , and the subscripts 0 to 3 indicate the value of the distance a ₁ b ₁ . After vertical mode encoding, the position of the changing pixel a ₀ is moved onto the changing pixel a ₁ .

In horizontal mode, both run lengths a ₀ a ₁ and a ₁ a ₂ are encoded using the code H + M (a ₀ a ₁ ) + M (a ₁ a ₂ ). The codes M (a ₀ a ₁ ) and M (a ₁ a ₂ ) are codes indicating the length and color (white or black) of the run lengths a ₀ a ₁ and a ₁ a ₂ , respectively, and the corresponding MH codes. Consists of. After encoding this mode, the position of the changing pixel a ₀ is moved onto the changing pixel a ₂ .

Each code in each of these code modes takes the values shown in Table 7 below.

The mode of such a two-dimensional code is detected by the run-length counting two-dimensional mode detection circuit 201. The run-length counting two-dimensional mode detection circuit 201 outputs the mode data DM of values as shown in Table 8 when detecting each mode.

Incidentally, H in the column of mode data represents a hexadecimal number, and the lower 10 digits thereof are output as mode data DM.

On the other hand, addresses 0010H and 0011 of the microprogram ROM 301
H, 0012H, 0013H, 0014H, 0015H, 0016H, 0017H, 0018H, 0019H
(However, only the lower 10 digits are valid), there is a jump instruction for shifting to the process of generating the code of the corresponding mode. Therefore, when the mode data DM is input as address data, immediately after that, Since it branches to the corresponding processing, high-speed processing becomes possible.

FIG. 2 shows the outline of the main routine of the one-line encoding process in this embodiment.

In this 1-line encoding processing, 1-line image data DI
The line start edge processing 101 is carried out before the actual encoding of.

In the line start end processing 101, first, a line synchronization code EOL representing a line delimiter is set in a parallel / serial converter 205 so that the upper bits are packed, and the number of bits of the line synchronization code EOL is set in the parallel / serial converter 205.
Then, the serial / parallel converter 103 is shifted, and the line synchronization code EOL is set in the serial / parallel converter 103 from the lower bit.

Next, the TAG bit (1 bit) for identifying whether the line is a one-dimensional encoding line or a two-dimensional encoding line is packed in the serial / parallel converter 103 from the lower bits by the same processing as the line synchronization code EOL. .

Then, if the encoding method set at that time is the one-dimensional encoding method, the signal RL / MODE is set to the signal RL state of the logic level H, and if the two-dimensional encoding method, the signal RL / MOD is set.
Set E to signal MODE state at logic level L. Immediately after outputting the signal RL / MODE, the signal RLGO is output to operate the run-length counting two-dimensional mode detection circuit 201.

Next, the state of the line end flag FEL to be set when the encoding process for one line is completed is determined (determination 10).
2). Since the line end flag FEL is not turned on immediately after the line start end processing 101 is ended, the result of this judgment 102 is NO.
become.

When the result of judgment 102 is NO, run length count 2
The output of the signal RLRDY indicating that one of the modes is detected from the dimension mode detection circuit 201 is monitored (decision 103), and when the signal RLRDY is output, 1 is output at that time.
It is determined whether or not the signal LE indicating that the encoding processing of the image data DI for the line is completed is output from the run length counting two-dimensional mode detection circuit 201 (determination 1
04).

When the result of determination 104 is YES, processing 105 is executed to turn on the line end flag FEL. When the result of determination 104 is NO because the encoding process for one line is not completed, the instruction decoder 310 selects the input terminal A of the multiplexer 308 and the mode data DM is input as a microprogram address. (Process 106).

As a result, the branch instruction stored in the address of the microprogram ROM 301 is executed in accordance with each code mode, the processing branches to the corresponding encoding processing routine, and the corresponding code is generated (processing 107). .

By executing the main routine once, one code data is formed and output, and by repeatedly executing the code data, image data for one line is sequentially encoded. Then, since the signal LE is responded when the encoding process is completed, the result of the determination 104 is YES, and the line end flag FEL is turned on in process 105. Therefore, at the next execution, the result of the judgment 102 becomes YES, and the line end processing 108
Is executed.

In this line terminating process 108, it is checked whether or not the coded data of the finished line is equal to or more than the minimum compensation bit number of one line set at that time, and if it is less than that, the fill bit is supplemented.

In this way, the encoding process for one line is performed,
This is repeated for the total number of lines, and the encoding process of the image (image information) for one page is executed.

By the way, the branch instruction in the processing 107 of the above-mentioned main routine is set to the microprogram address corresponding to the value of the mode data DM as shown in Table 9, for example.

Here, the numerical value in the address field is a hexadecimal number, and each operand of the branch instruction is a label name attached to the head address of the branch destination routine.

That is, the main body of the horizontal mode encoding processing routine is placed from the label TXHORZ, and the main body of the vertical mode encoding processing routine is placed from the label TXV (x) to the label TXH.
The main body of the pass mode encoding processing routine is placed from PASS, and the main body of the one-dimensional mode encoding processing routine is placed from the label TX1D. In addition, TXV (x)
X of 1 represents one or two characters following TXV.

These encoding processing routines are shown in FIG. A corresponding label name is attached to the beginning of each routine, and each routine will be referred to by that label name below.

FIG. 9A shows a horizontal mode encoding processing routine TXHORZ.
Is shown. In this routine TXHORZ, the horizontal mode code H is first set in the parallel / serial converter 205, then the data of the parallel / serial converter 205 is shifted out to the serial / parallel converter 103, and further M
Subroutine TXMH for generating H code (see (b) in the figure;
(Described later) is called, and the run length a ₀ a ₁ counted by the run length counting two-dimensional mode detection circuit 201 at that time is called.
Is encoded into a corresponding MH code and set in the serial / parallel converter 103.

Next, the color of the changed pixel a ₀ is inverted, the signals RL and RLGO are output to detect the run length a ₁ a ₂ , the run length counting two-dimensional mode detection circuit 201 is activated, and the signal RLRDY is output. Wait for a response.

When the signal RLRDY is responded, the subroutine TXMH is called again to set the MH code corresponding to the run length a ₁ a ₂ in the serial / parallel converter 103.

Then, after inverting the color of the changed pixel a ₀ and outputting the signals MODE and RLGO to detect the next code, the process returns to the main routine of FIG. 2 by jumping to the point A.

As a result, the code H + M (a ₀ a ₁ ) + M (a ₁ a ₂ ) is formed and output.

In the subroutine TXMH, first, the corresponding MH code is read from the MH coding ROM 202 with the contents of the run length counter of the run length counting two-dimensional mode detector 201, and the read MH code is set in the parallel / serial converter 205. Then, the data of the parallel / serial converter 205 is shifted out to the serial / parallel converter 103. As a result, the MH code is set in the serial / parallel converter 103.

FIG. 11C shows the encoding processing routine TXV (x) for the vertical mode V (x). The encoding processing routine TXV (x) is an encoding processing routine TXVL3, TXVL2, TXV.
Represents L1, TXV0, TXVR1, TXVR2, TXVR3 on behalf.

In this encoding processing routine TXV (X), first, the vertical mode code V (x) is set in the parallel / serial converter 205, and its contents are serial / parallel converter 103.
Shift out to. Then, after inverting the color of the changed pixel a ₀ , the signals MODE and RLGO are output to activate the run-length counting two-dimensional mode detection circuit 201. The vertical mode code V (x) is a code corresponding to each vertical mode.

FIG. 11D shows the encoding processing routine TXPA of the pass mode P.
Shows SS. In this encoding processing routine TXPASS,
First, pass mode code P is converted into parallel / serial converter
Set to 205 and shift out the contents to the serial / parallel converter 103. Then, the signal RLGO is output to activate the run-length counting two-dimensional mode detection circuit 201.

FIG. 3E shows a one-dimensional mode encoding processing routine TX1D.
Is shown. In the encoding processing routine TX1D, first, the subroutine TXMH is called, and the MH code corresponding to the run detected by the run length counting two-dimensional mode detection circuit 201 at that time is set in the serial / parallel converter 103, and the change pixel is set. After inverting the color of a ₀ , the signals RL and RLGO are output to activate the run-length counting two-dimensional mode detection circuit 201.

In each of the above processing routines, when data is shifted out from the parallel / serial converter 205 to the serial / parallel converter 103, the shift operation is temporarily performed while the serial / parallel converter 103 is full. The 16-bit data that is interrupted and stored in the serial / parallel converter 103 at that time is output to the outside (for example, a bus line) by the code data interface circuit 104. Then, when the serial / parallel converter 103 is in the empty state, the shift is restarted. The full state of the serial / parallel converter 103 is detected by a counter (not shown) that counts up in synchronization with this.

When the 16-bit data stored in the latch circuit 101 is completely encoded by the run-length counting two-dimensional mode detection circuit 201, the operation of the run-length counting two-dimensional mode detection circuit 201 is temporarily suspended and the image data interface The circuit 102 requests the next 16-bit data from the external device. When the data is stored in the latch circuit 101, the run length counting two-dimensional mode detection circuit 20
Operation 1 is restarted.

In this way, one piece of code data is generated.

Each step in the above-mentioned routine is realized by a plurality of combinations of microprograms.

By the way, in the above-described embodiment, the present invention is implemented as a means for encoding image data, but the present invention may also be implemented as a decoding means for restoring encoded image data to original image data. It is possible. In that case, it is possible to realize an encoding / decoding device in which both the encoding process and the decoding process are fast.

Further, the present invention is not limited to the encoding device of the facsimile device and can be applied to other devices as long as the image data is encoded.

[Effect] As described above, according to the present invention, a micro program sequencer for executing a coding processing procedure and generating a two-dimensional code, a code discriminating means for performing run length counting and code mode detection, and a run length. , A run-length code generating means for generating a run-length code corresponding to, and a mode signal output from the code discriminating means when a code mode is detected is input as a microprogram address, and processing corresponding thereto is performed. Since the routine is branched to generate the corresponding code, there is an advantage that the encoding processing speed becomes high.

[Brief description of drawings]

FIG. 1 is a block diagram showing an encoding apparatus according to an embodiment of the present invention, FIG. 2 is a flowchart showing a main routine of encoding processing, and FIG. 3 (a) is an encoding processing routine in a horizontal mode. The flowchart shown in the figure, (b) of the same figure is a flowchart showing a subroutine, (c) of the figure is a flowchart showing an encoding processing routine in the vertical mode,
FIG. 6D is a flowchart showing the pass mode encoding processing routine, and FIG. 7E is a flow chart showing the one-dimensional mode encoding processing routine. 100: input / output section, 200: data generation section, 201: run length counting two-dimensional mode detection circuit, 202: MH coded R
OM, 300 ... Micro program sequencer.

Claims (1)

[Claims] 1. A microprogram sequencer for executing a coding procedure process and generating a two-dimensional code, a code discriminating means for counting run lengths based on an input image signal and detecting a code mode, and the code discrimination. The run length code generating means for generating a run length code corresponding to the run length output from the means, wherein the micro program sequencer outputs a micro mode signal output from the code discriminating means when the code mode is detected. An encoding device which inputs as a program address and branches to a processing routine corresponding to the program address to generate a corresponding code.