JPH07101718B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit in which active elements such as bipolar transistors and MOS transistors are formed on the same substrate. .

[Conventional technology and its problems]

In recent years, application-specific LSIs, namely, ASICs (Application Specific ICs)
ic IC)) is in the spotlight. General-purpose standard I such as memory
Market growth is expected to exceed that of C, and its applications are expanding.
Against this background, the integration of semiconductor devices is progressing,
Bi-CMOS technology in which a bipolar transistor and a MOS transistor are formed on the same substrate is one of them.

[Problems to be solved by the invention]

However, in advancing compounding of elements, major problems such as increase in manufacturing process, complication of manufacturing process, and extension of manufacturing period occur, and it is very difficult to manufacture a semiconductor integrated circuit with high yield in a short period of time. Has become. The purpose of the present invention is to
In a semiconductor integrated circuit in which a bipolar transistor and a MOS transistor are formed on the same substrate, manufacture of a semiconductor integrated circuit capable of forming a floating gate type nonvolatile memory device on the same substrate without the above-mentioned drawbacks that occur when the elements are combined. To provide a method.

[Means for Solving the Problems] In the method for manufacturing a semiconductor integrated circuit according to the first aspect of the present invention, a step of preparing a semiconductor substrate having a P-type surface region and an inner-type surface region, the P-type surface region and the N-type surface region are provided. A gate insulating film is formed on each surface of the mold surface region, and a base region of the NPN vertical transistor is formed on the surface of the N-type surface region, and then the N-type is not formed on the base region and the base region. A step of forming an emitter contact hole and a collector contact hole in the gate insulating film on the surface region, and a mask for depositing a polycrystalline silicon film and covering the emitter contact hole and its peripheral portion with the polycrystalline silicon film. After being formed, N-type impurities are introduced and then patterned to form on the P-type surface region, on the emitter contact hole and its peripheral portion, and before. The step of leaving the processed film for the floating gate, the emitter electrode and the collector electrode on the collector contact hole and its peripheral portion, respectively, and the exposed surface of the polycrystalline silicon film of the processed film for the floating gate, the emitter electrode and the collector electrode with an insulating film. A step of forming a control electrode and a floating gate electrode by patterning the conductive film and the processed film for the floating gate after depositing a conductive film on the entire surface after covering, and removing the mask by removing the emitter electrode by N The ion implantation for forming a pair of source / drain regions sandwiching the surface portion of the P-type surface region immediately below the floating gate electrode, and the N channel floating gate type memory transistor. Including a memory cell and an NPN vertical transistor comprising the memory cell and controlling the memory cell. Is that forming the peripheral circuit dynamic.

A second method of manufacturing a semiconductor integrated circuit according to the present invention comprises a step of preparing a semiconductor substrate having a P-type surface region and an N-type surface region, and a step of preparing a semiconductor substrate on each of the P-type surface region and the N-type surface region. Forming a gate insulating film and forming a base region of the NPN vertical transistor on the surface of the N-type surface region, and then forming a conductive film on the entire surface and patterning to leave a floating gate processed film on the P-type surface region. A step of coating the floating gate processed film with an insulating film, and the N on which the base region and the base region are not formed,
Forming an emitter contact hole and a collector contact hole in the gate insulating film on the mold surface region, and depositing a polycrystalline silicon layer on the entire surface and covering the emitter contact hole and its peripheral portion with the polycrystalline silicon film. Forming a mask for forming the mask, introducing N-type impurities, and patterning the processed film for the floating gate covered with the polycrystalline silicon film and the insulating film to pattern the collector contact hole and its periphery, and the emitter contact hole. A step of forming a collector electrode, an emitter electrode, a control electrode and a floating gate electrode on the periphery thereof and on the P-type surface region, respectively, and after removing the mask, doping the emitter electrode to an N-type and floating the same. A pair of source / drain regions sandwiching the surface portion of the P-type surface region immediately below the gate electrode Forming a peripheral circuit for controlling and driving the memory cell, the memory cell including the N-channel floating gate type memory transistor and the NPN vertical type transistor. is there.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a main part of an example of a semiconductor integrated circuit according to the present invention.

In this semiconductor integrated circuit, an electrically programmable read-only memory (EPROM) cell 100, which is one of floating gate nonvolatile memories, and an NPN vertical transistor 101 are formed on the same semiconductor substrate. A feature is that the floating gate electrode 5 or the control gate electrode 6 of the EPROM cell 100 is formed of the same electrode material as the emitter electrode 7 and the collector electrode of the NPN bipolar transistor 101. EPRO
If the M cell 100 is an N channel type, the gate electrode, the emitter electrode, and the collector electrode can all be formed of, for example, polycrystalline silicon doped with N type impurities. Polycrystalline silicon
It is an excellent electrode material used in both MOS transistors and bipolar transistors. Therefore, a composite integrated circuit including an EPROM with excellent characteristics can be realized.

FIG. 2 is a sectional view of a semiconductor chip showing a main part of a semiconductor integrated circuit for explaining a technique related to the present invention.

In this semiconductor integrated circuit, an electrically rewritable nonvolatile memory (EEPROM) and an NPN vertical transistor are integrated on the same semiconductor substrate. The floating gate electrode 5 or the control gate electrode 6 is used as the emitter electrode 7 and collector of the NPN transistor 101. It is made of the same material as the electrode 8.

Even in such a case, for example, the floating gate electrode 5, the emitter electrode 7, and the collector electrode 9 can be formed of polycrystalline silicon, and good characteristics can be realized as in the semiconductor integrated circuit of FIG.

3A to 3D are sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the method for manufacturing a semiconductor integrated circuit of the present invention.

First, as shown in FIG. 3A, P made of silicon is used.
After the N well region 2 is formed in the semiconductor substrate 1, the field oxide film 3 for element isolation, the gate oxide film 10, the base region 8 of the NPN vertical transistor are formed, and then the emitter contact hole 11 and the collector contact hole are formed. Forming twelve. Next, as shown in FIG. 3 (b), after a polycrystalline silicon layer 13 is formed on the entire surface by a CVD method to a thickness of 1000 to 4000 Å,
Selective thickness 2000-5000 covering over contact hole 11
A mask 14 made of a silicon oxide film of Å is formed, and then impurities such as phosphorus and arsenic are introduced into the polycrystalline silicon layer 13 by using a thermal diffusion method or an ion implantation method. At this time, the oxide film 14 serves as a mask on the emitter of the bipolar transistor, and impurities are not introduced. Next, as shown in FIG. 3 (c), the polycrystalline silicon layer 13 into which impurities have been introduced is selectively etched and then thermally oxidized to form a silicon oxide film 15 having a thickness of 100 to 1000Å. A processed film (polycrystalline silicon layer 13), a collector electrode 9 of a bipolar transistor, and an emitter electrode 7 are formed. Next, as shown in FIG. 3, a polycrystalline silicon layer 16 having a thickness of 1000 to 4000 Å is formed on the entire surface by a CVD method, and then impurities such as phosphorus and arsenic are polycrystalline silicon by a thermal diffusion method or an ion implantation method. Introduce to layer 16. Next, as shown in FIG. 1, the polycrystalline silicon layer 16, the silicon oxide film 15, and the polycrystalline silicon film 13 are sequentially etched to form the control gate electrode 6 and the floating gate electrode 5. Mask at this time
Since there is 14, the emitter electrode 7 is not etched. Next, after removing the mask 14, an impurity such as phosphorus or arsenic is added to the region for forming the source / drain region 4 of the memory cell and the emitter electrode 7 by ion implantation.
Introduce x10 ¹⁵ to 1 x 10 ¹⁶ cm ^-2 .

Then, source / drain regions 4 for heat treatment are formed. At the same time, the impurities previously implanted from the emitter electrode 7 are diffused into the base region 8 and are connected to the emitter electrode 7.
A type diffusion layer is formed.

According to the structure method described above, the emitter electrode of the NPN vertical transistor and the floating gate electrode can be formed of the same electrode material.

FIG. 4 is a sectional view of a semiconductor chip for explaining a second embodiment of the semiconductor manufacturing method of the present invention.

This embodiment is a method of forming the emitter electrode and the control electrode of the floating gate nonvolatile memory with the same electrode material.

As shown in FIG. 4, after forming the N well region 2 in the P type semiconductor substrate 1, the field oxide film 3 for element isolation, the gate oxide film 10 and the base region 8 of the NPN vertical transistor are formed to cover the entire surface. A polycrystalline silicon layer with a thickness of 1000 to 4000 Å is provided by the CVD method, etc. After introducing impurities into this polycrystalline silicon layer and patterning, the surface is oxidized to form an oxide film 15 of 2000 to 50
After forming a thickness of 00 Å, then removing the silicon oxide film on the emitter contact hole 11 and the collector contact hole 12, and providing a polycrystalline silicon layer 16 to a thickness of 2000 to 4000 Å on the entire surface by the CVD method etc. A mask 14 made of silicon oxide is formed above the contact hole 11. Next, impurities such as phosphorus and arsenic are introduced into the polycrystalline silicon layer 16. At this time, since the mask 14 exists in the emitter electrode region, impurities are not introduced. Next, as shown in FIG. 1, the control gate electrode 6, the floating gate electrode 5, the emitter electrode 7, and the collector electrode 14 are formed by etching similarly to the first embodiment, and then the memory is formed by using the ion implantation method. Impurities such as phosphorus and arsenic are introduced into the region forming the source / drain region 4 of the cell and the emitter electrode 7 at 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2 .

Then, heat treatment is performed to form source / drain regions 4. At the same time, the impurities previously implanted from the emitter electrode 7 are diffused into the base region 8 to form an N-type diffusion layer connected to the emitter electrode 7.

It should be noted that in the above description, the NPN vertical transistor is used in a peripheral circuit for controlling and driving the memory, and enables high speed operation of the memory device including the N-channel floating gate memory transistor.

〔The invention's effect〕

As described above, according to the present invention, the emitter electrode of the NPN vertical transistor and the floating gate electrode or control electrode of the N-channel floating gate type nonvolatile memory transistor are composed of the polycrystalline silicon layer formed at the same time, and the N-channel floating transistor is formed. Source of gate type non-volatile memory transistor
By introducing impurities into the above-mentioned emitter electrode in the ion implantation process for forming the drain region, a complex semiconductor integrated circuit including EPROM with excellent characteristics can be manufactured, suppressing the increase in manufacturing process and complicating the manufacturing process. There is an effect that can be realized by avoiding.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a main portion of an example of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a semiconductor chip showing a main portion of a semiconductor integrated circuit for explaining a technique related to the present invention. Sectional views, FIGS. 3A to 3D are sectional views of a semiconductor chip arranged in the order of steps for explaining the first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention.
The figure is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the method for manufacturing a semiconductor integrated circuit of the present invention. 1 ... P-type semiconductor substrate, 2 ... N well region, 3 ... Field insulating film for element isolation, 4 ... Source / drain region, 5 ... Floating gate electrode, 6 ... Control gate electrode,
7-emitter electrode, 8-base region, 9-collector electrode, 10-gate oxide film, 11-emitter contact hole, 12-collector contact hole, 13-polycrystalline silicon layer, 14- Mask, 15 …… Silicon oxide film, 16 ……
Polycrystalline silicon layer, 17 ... Tunnel oxide film, 100 ... EPR
OM cell, 101 ... NPN vertical transistor, 102 ... EEPROM
cell.

Claims (2)

[Claims] 1. A step of preparing a semiconductor substrate having a P-type surface region and an inner-type surface region, and a step of forming a gate insulating film on each of the P-type surface region and the N-type surface region to form the N-type surface. After forming a base region of the NPN vertical transistor on the surface of the region, an emitter contact hole and a collector contact hole are formed in the gate insulating film on the base region and on the N-type surface region where the base region is not formed, respectively. Forming step, and after depositing a polycrystalline silicon film and forming a mask for covering the polycrystalline silicon film on the emitter contact hole and its peripheral portion, introducing an N-type impurity and then patterning the P-type Floating gate processing is performed on the surface region, the emitter contact hole and its peripheral portion, and the collector contact hole and its peripheral portion, respectively. A step of leaving as a film, an emitter electrode and a collector electrode, and covering the exposed surface of the polycrystalline silicon film of the processed film for the floating gate, the emitter electrode and the collector electrode with an insulating film, and then depositing a conductive film on the entire surface, and then the conductivity. Forming a control electrode and a floating gate electrode by patterning the film and the processed film for the floating gate; and, after removing the mask, doping the emitter electrode into N type and at the same time the P type surface immediately below the floating gate electrode. A step of performing ion implantation to form a pair of source / drain regions sandwiching a surface portion of the region, and the memory cell including the N-channel floating gate type memory transistor and the NPN vertical type transistor. Of a semiconductor integrated circuit characterized by forming a peripheral circuit for controlling and driving Method. 2. A step of preparing a semiconductor substrate having a P-type surface region and an N-type surface region, and forming a gate insulating film on each surface of the P-type surface region and the N-type surface region to form an N-type surface region. Forming a base region of the NPN vertical transistor on the surface portion of the NPN transistor, and then forming a conductive film on the entire surface and patterning it to leave it as a floating gate processed film on the P type surface region; And a step of forming an emitter contact hole and a collector contact hole in the gate insulating film on the base region and on the N-type surface region where the base region is not formed, respectively. Before depositing a layer and forming a mask covering the polycrystalline silicon film on the emitter contact hole and its peripheral portion, and then introducing N-type impurities, The processed film for the floating gate covered with the polycrystalline silicon film and the insulating film is patterned to collect collector electrodes on the collector contact hole and its periphery, on the emitter contact hole and its periphery and on the P-type surface region, respectively. Forming a floating gate electrode with an emitter electrode and a control electrode; and removing the mask, doping the emitter electrode with N-type, and sandwiching a surface portion of the P-type surface region immediately below the floating gate electrode. A step of performing ion implantation for forming source / drain regions, and a memory cell including the N-channel floating gate type memory transistor,
A method of manufacturing a semiconductor integrated circuit, comprising forming a peripheral circuit including an NPN vertical transistor and controlling and driving the memory cell.