JPH07101720B2 - Semiconductor element - Google Patents

Description

The present invention relates to a semiconductor device having the performance of a MOS transistor of a bipolar transistor.

[Conventional technology]

Conventionally, a bipolar power transistor has been used as a power semiconductor element, but in order to improve its low-speed property and obtain a high-speed, large-current, high-voltage device, a module composed of MOS transistor elements, a bipolar transistor chip, and One that has been proposed and commercialized is one in which a circuit is formed by a MOS transistor chip that drives it or an insulated gate bipolar transistor (IGBT) in which the circuit is integrated in one semiconductor element.

[Problems to be solved by the invention]

However, the MOS module has a drawback in that it is difficult to increase the current because the ON resistance of the MOS transistor is large, and there are many wirings, which causes an influence of inductance.
In the bipolar MOS circuit, the area occupied by the chip is large, there are many wirings, and the effect of the inductance is exerted. Also, the number of steps such as chip bonding and wire bonding is large, and it is difficult to reduce the size and weight. Have.

On the other hand, the IGBT has a long tail when it is switched off. This is because the residual minority carriers are self-annihilation type, and it is necessary to introduce a lifetime killer in order to speed up the residual minority carriers and cope with high frequencies. Also, since there is a latch-up phenomenon, measures are taken to increase the latch-up tolerance and switching speed within the allowable range of V _{CE (Sat)} . However, these measures are in a trade-off relationship, and if a large amount of life time killer is introduced for high frequency, it will be drastic.
V _{CE (Sat)} increases, and a large chip size is required for large currents. Increasing the h _FE of the bipolar transistor in the IGBT in order to avoid it, in turn, speed is slower, also reduced latch-up immunity.

An object of the present invention is to solve many problems existing in the case of combining the performances of a bipolar transistor and a MOS transistor as described above, and to reduce the influence of wiring, to be small-sized, lightweight, high-speed, large-current, high-voltage semiconductor device. To provide.

[Means for solving problems]

In order to achieve the above object, the present invention provides a semiconductor element body, a MOS transistor having a gate electrode on one surface via a source electrode and an insulating film, a drain electrode on the other surface, an emitter electrode on one surface, and A base electrode connected to the source electrode and a bipolar transistor having a collector electrode connected to the drain electrode on the other surface are formed, and a part of a base layer of the first conductivity type of the bipolar transistor has a predetermined impurity concentration of a first electrode. A speed-up diode comprising a region of one conductivity type and a region of the second conductivity type exposed on one surface of the semiconductor element and contacting an electrode connected to the gate electrode, and a part of a collector layer of the second conductivity type And a flywheel diode comprising a part of the base layer in contact with the emitter electrode and an electrode connected to the emitter electrode. Paula transistor portion and selectively lifetime killer in flywheel diode portion is assumed to be introduced.

[Action]

A bipolar transistor and a MOS transistor are separately formed in one semiconductor element, and a lifetime killer is introduced only in the bipolar transistor section to eliminate the influence of an increase in the on-resistance of the MOS transistor. In addition, in order to eliminate the drawbacks of self-destructing devices, a speed-up diode is built in so that residual carriers can be extracted.
It also has a flywheel diode built-in, eliminating the need for external wiring as well as a speed-up diode. Further, since there is no four-layer parasitic thyristor structure, there is no latch-up phenomenon due to thyristor operation.

〔Example〕

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof, in which parts corresponding to the respective parts in FIG. This device uses a substrate in which an n ^- epitaxial layer 2 is grown on an n-type silicon substrate 1, and n ⁺ is formed in a portion where a MOS transistor is formed.
Layer 3 is embedded. On the surface of n ^- layer 2, p ⁺ layers 41 and 42
Are formed. The p ⁺ layers 41 and 42 can be formed in the same process. The p ⁺ layer 41 is a channel region of a MOS transistor, and an n ⁺ source region 51 is provided therein. Both channel regions 51
A gate electrode 7 is provided on the n ⁻ layer 2 exposed between the gate electrodes 7 through the insulating film 6 and connected to the gate terminal G. n ⁺
The source electrode 8 is in contact with the layer 51 and the p ⁺ layer 41. As a result, the MOS transistor 10 is formed. One p ⁺ layer 4
Reference numeral 2 is a base layer of a bipolar transistor, in which an n ⁺ emitter region 52 is provided. The emitter electrode 9 is in contact with the n ⁺ emitter region 52 and is connected to the emitter terminal E. n ⁻ layer 2 and n ⁺ layer 1 are collector layers, which are commonly connected to the drain of the MOS transistor 10 and to the collector terminal C,
As a result, the NPN bipolar transistor 20 is completed. Higher impurity concentration P ⁺⁺ region 4 in part of P ⁺ layer 42
3 is formed, and a zener diode 30 is completed between the n 3 and the n ⁺ layer 53 therein. The n ⁺ regions 51, 52, 53 can be formed in the same process. The anode electrode 11 that contacts the anode region 43 of the diode 30 is connected to the source electrode 8 of the MOS transistor and the base electrode 12 that contacts the base layer 42 of the bipolar transistor, and the cathode electrode 13 that contacts the cathode region 53 has the gate terminal G. To realize a part of the circuit shown in FIG. Further, since the electrode 14 that contacts a part of the base layer 42 is connected to the emitter terminal E, the p ⁺ base layer 42
The diode formed between the n ^- epitaxial layer 2 and the n ^- epitaxial layer 2 forms a flywheel diode 40 which bypasses between the emitter terminal E and the collector terminal C. Then, the resistor 15 in the emitter electrode 9 and the resistor 16 in the base layer below the emitter region 52 are inserted to realize the entire equivalent circuit of FIG.

Further, the lifetime killer 17 such as gold is selectively diffused in the bipolar transistor section 20 and the flywheel diode section 40, and the high frequency can be achieved without affecting the MOS transistor section. Further, the n ⁺ buried layer 3 is formed only in the MOS transistor portion to reduce the on resistance thereof.

〔The invention's effect〕

According to the present invention, by incorporating a MOS transistor, a bipolar transistor, a speed-up diode, and a flywheel diode in one semiconductor body to form one element, the inductance due to external wiring is significantly reduced, and the number of assembly steps is also reduced. As a device capable of extracting residual carriers from a self-annihilation device with a speed-up diode, it has become possible to maintain high-speed performance even with high withstand voltage and large current devices. And switching speed
The trade-off relationship of V _{CE (sat} ) was resolved by introducing a lifetime killer only in the bipolar transistor and flywheel diode parts. In addition, this element
Unlike IGBTs, there is no latch-up phenomenon, so there is no need to consider the trade-off between improved latch-up resistance and other characteristics, and a device with high characteristics and high reliability could be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. 1: n ⁺ silicon substrate, 2: n ^- silicon epitaxial layer, 41 and 42: p ⁺ layer, 43: p ⁺⁺ layer, 51, 52, 53: n ⁺ region, 6:
Insulating film, 7: Gate electrode, 8: Source electrode, 9: Emitter electrode, 12: Base electrode, 10: MOS transistor, 20: Bipolar transistor, 30: Speed-up diode, 40: Flywheel diode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78

Claims (1)

[Claims] 1. A MOS transistor having a gate electrode on one surface through an insulating film and a drain electrode on the other surface of one semiconductor element, an emitter electrode and a base electrode connected to the source electrode, and the like. A bipolar transistor having a collector electrode connected to the drain electrode on its surface, and a region of the first conductivity type having a predetermined impurity concentration and a semiconductor element body in a part of a base layer of the first conductivity type of the bipolar transistor. A speed-up diode, which is exposed on one surface and is in contact with an electrode connected to the gate electrode, and a part of a collector layer of the second conductivity type and an electrode connected to the emitter electrode A flywheel diode formed of a part of the base layer in contact with the bipolar transistor part of the semiconductor element body and the flywheel diode. The semiconductor device characterized selectively be lifetime killer is introduced into the wheel diode portion.