JPH0710258B2 - Ultrasonic wave reception phasing circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the configuration of a wave-receiver phaser used in an electronic scanning ultrasonic tomographic imaging apparatus.

[Background of the Invention]

FIG. 1 shows the configuration of a conventional wave receiving and phasing device. , N are elements of the array oscillator, 10-1 to 10-N are analog inductance capacitance delay circuits, 11 is an adder, and 12 is an output terminal. 16 is the wavefront of the received signal. In this way, since the received signals of the elements on the center side of the array element are received in advance with respect to those of the outer elements, it is possible to add the received signals of all the elements in phase by delaying the elements on the center side.

The drawbacks of this conventional wave-receiver / phase-matcher are the limitation of frequency characteristics, difficulty of minute delay control, and enlargement of hardware scale.

On the other hand, a method as shown in FIG. 2 has been proposed. Here, 13-1 to 13-N are signal holding means using capacitors called sample hold, 14 is a control layer, C1 to CN are control signals, 17-1 to 17-N are control signals C1 to
It is an example of CN.

In this way, all the received signals can be added in phase by sampling and adding them on the concave surface corresponding to the arrival time of the received signals at the array element.

Problems of the conventional method shown in FIG. 2 will be described with reference to FIG. Here, Cik is a control signal of the sample hold 13-i in FIG. 2, i = 1 to N (N is the number of array elements), k = 1 to M (M
Is a number indicating a time series). T is a sampling interval time, for example, a value of 100 to 500 ns. τ ₀ is the settling time of sampling and holding, and is a value of about 10 ns, for example. Ci′k ′ is a control signal of a received signal of an array element different from Cik, and the time difference between Cik and Ci′k ′ is τ. Here, for the sake of convenience, τ ₀ and τ are displayed larger than T.

Now, FIG. 3A shows a case where the received signal α is ideally sampled and held to obtain the output β. Here, in the range from the control signal Cik to the settling time τ ₀ , the sample hold output is in a transient state, and the accurate output is obtained after the time τ ₀ .

However, when the control signal Ci′k ′ of the received signal of the array element of i ′ different from i exists in Cik after τ (τ <τ ₀ ) time, the received signal α is changed to the received signal α by electrical coupling. Noise is mixed and becomes the received signal α ′. Since the appearance time of this noise is smaller than the settling time τ _{0 of} the sample hold, the sample hold output becomes β ′ as shown in FIG. 3 (b), and an error ε is generated between the sample hold output and the ideal output β. become. As a result, problems occur in the operation of the wave rectifier, particularly in the signal dynamic range and the signal-to-noise ratio.

[Object of the Invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a wave-receiver phaser having a larger signal-to-noise ratio and a wider dynamic range in view of the above-mentioned drawbacks of the prior art in phasing a wave-received signal to an array element.

[Outline of Invention]

According to the present invention, when the phase difference of the received signals to the arrayed elements is shorter than the settling time τ ₀ of the sample hold, the accuracy of phase alignment is sacrificed and the settling time τ ₀ of the sample hold is set. The feature is that the sample and hold is performed with a phase difference equal to or greater than the threshold value.

This will be described in more detail below with reference to the drawings.

FIG. 4 describes the control signal of the present invention in comparison with the conventional method.

(A) shows the control signals ΣCik of all the array elements in the same time series with respect to the control signal Cik of the conventional method,
Of course, the time interval of each control signal Cik may exist within the settling time τ ₀ of sample hold,
The above problem occurs.

Therefore, in the present invention, as shown in FIG. 7B, if the time interval of each control signal is Cik-Ci'k '(-is a difference) is larger than a constant threshold value (= settling time) τ ₀ , Ci'k'. = Ci′k ′, and if τ ₀ or less, Ci′k ′ = Cik.

The validity of this operation will be described below.

In general, if the phase alignment accuracy deteriorates, the sensitivity of the main beam in the acoustic beam deteriorates, the beam width of the main beam increases, and the unnecessary acoustic level increases. Of these, the third party is particularly problematic. Now, the ultrasonic frequency of general-purpose ultrasonic tomography equipment is 3.5 to 5.0 MH
In the case of z, if the phase matching accuracy of the phaser is about 10 to 30 ns or less, the increase in the unnecessary acoustic level is practically negligible. On the other hand, since the sample hold settling time τ ₀ is about 10 ns, even if the time of the sample hold control signal is quantized by the operation of the present invention, the acoustic characteristics are not affected and the problems of the conventional method can be solved.

Here, various modifications can be considered as the quantization method.
For example a method for the quantization units and tau _0/2, i.e. Cik~C
If i′k ′ ≧ τ _0, then Ci′k ′ = Ci′k ′, Cik∼Ci′k ′
≧ τ _0/2 if _{Ci'k '= Cik + τ 0,} Cik~Ci'k'<τ 0/2
If so, a method of Ci′k ′ = Cik may be adopted.

Example of Invention

FIG. 5 shows an embodiment of the present invention, in which 20 is a memory for the control signal Cik, 21 is a memory for the control signal Ci'k ', 22 is a subtractor, a and b are input terminals, and c is an output terminal. is there. Reference numeral 23 is a comparator, d is an input terminal of the control signal time difference Cik to Ci′k ′, e is an input terminal of a constant threshold value (settling time τ ₀ ), and f is an output terminal, the time difference Cik to Ci ′. The control signal 1 is output when k ′ exceeds the threshold value τ ₀ , and the control signal 0 is output when k ′ does not exceed the threshold value τ ₀ . Reference numeral 24 is a switch, g and h are input terminals, p is an input terminal of the control signal f, and g is an output terminal. When the control signal f is 1, the terminals h and g are connected,
The control signal Ci'k 'is output from the terminal q. On the other hand, when the control signal f is 0, the terminals g and q are connected and the control signal Cik is output from the terminal q. This output is stored in the memory 25. This memory 25 is stored in the controller 14 of the wave rectifier shown in FIG.

The operation of FIG. 5 will be further described with reference to FIG. When the number of array elements is N = 8, first, i = 1, i ′ = 2, and C _{2 k} is determined based on C _{1 k} . C _{2 k} −C _{1 k} <τ
_Since it is _0, it is corrected as shown by the arrow. Next, for C _{3 k} and corrected C _{2 k} , since C _{3 k} is -C _{2 k} > τ ₀ ,
Let C _{3 k} = C _{3 k} (invariant). Next, for C _{4 k} and C _{3 k} , the reference point moves by δ. By the same operation, the correction of all control signals is completed.

In this explanation, the adjacent channels are corrected, but there is also a simple method as follows. That is, this is a method of uniformly quantizing all control signals Cik with a predetermined threshold value τ ₀ .
Even in this case, it is apparent that the effect of the present invention shown in FIG. 4 (b) can be realized. In this case, the time difference δ in FIG. 6 =
Equivalent to 0. The phaser characteristics are almost the same.

Obviously, the embodiment of FIG. 5 implements the operation of FIG. 4 (b).

In the above description, the configuration of FIG. 2, that is, the wave-receiver phasing device by the sample hold is explained, but the same effect can be expected for the wave-receiving phase maker including the analog-digital converter as shown in FIG. . In the figure, 30-1 to 30
-L (L is a positive integer, L = N / 3) is an analog / digital converter, 31-1 to 31-N are line memories, 32 is an adder,
33 is an output terminal.

Also in the case of such an analog-digital converter, the present patent is effective because other control signals are superposed on the analog signal via electrical coupling and deteriorate the characteristics of the phase rectifier.

In the above description, the convergence point of the ultrasonic beam is one,
The case of fixed convergence is described. The present invention is also effective in the case of so-called dynamic focus, which changes the convergence point in real time.

Further, although the ultrasonic beam focusing has been described in the above description, the present patent is also effective for beam deflection.

〔The invention's effect〕

As described above, according to the present invention, since the time difference between the control signals of the array elements is zero or more than the settling time, the sample hold and / or the analog-digital conversion output is stable, and thus the signal of the wave receiver / phaser is obtained. It greatly contributes to the improvement of noise ratio and dynamic range.

[Brief description of drawings]

FIG. 1 is an explanatory view of a conventional device, FIG. 2 is an explanatory view of a sample hold type phaser, FIG. 3 is an explanatory view of problems of a conventional method, and FIG. 4 is a control signal of an embodiment of the present invention. 5 is a block diagram showing an embodiment of the present invention, FIG. 6 is an operation explanatory diagram of FIG. 5, and FIG. 7 is a block diagram showing another embodiment of the present invention. 20,21,25 …… Memory, 22 …… Subtractor, 23 …… Comparator, 24
...... Switching device.

Front page continuation (72) Inventor Shinichi Kondo 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Shinichiro Umemura 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Keiyoshi Katakura 1-280, Higashi Koigakubo, Kokubunji, Tokyo (56) References: Central Research Laboratory, Hitachi, Ltd. (56) References JP-A 51-43879 (JP, A) JP-A 52-7233 (JP, A) JP-A-52-59974 (JP, A)

Claims (2)

[Claims] 1. A received signal to a plurality of elements is sampled on the basis of the time when a wave front of an ultrasonic wave from a desired position or direction reaches each of a plurality of transducer elements constituting an array vibrating element. Then, by adding, in the ultrasonic wave receiving and phasing circuit to obtain a phasing output of the ultrasonic wave receiving beam characteristic having sensitivity to the ultrasonic wave from the desired position or the desired direction, in each of the plurality of elements, An adder having a plurality of sampling means for sampling the received wave signal at a predetermined sampling period and a plurality of holding means for holding each sampled received wave signal, and adding the outputs of the holding means to form a phasing output And a control means for controlling the sampling time of each of the plurality of sampling means, any sample of the plurality of sampling means Timing also, ultrasonic receiving phasing circuit or with a longer time difference than the output settling time of each sampling means with respect to the sample timing of the other sampling means, otherwise the time difference is characterized in that it is a zero. 2. The ultrasonic wave receiving and phasing circuit according to claim 1, wherein the sampling means is an analog-digital converter.