JPH07104902B2 - Bar code reader - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a bar code reading device for reading a bar code attached to a product, for example.

[Prior Art] Bar code readers include those using a hand-held scanner and those using a stationary scanner.

Conventionally, as the one using a hand-type scanner,
As shown in FIG. 10, a bar code is scanned and read by, for example, a pen-type scanner 1, the signal is binarized by a binarization circuit 2, and the binarized signal is converted by a microcomputer 3
The soft processing is performed in order to recognize the barcode.

As described above, since the pen type scanner 1 is manually operated, the scanning speed of the bar code is slow, and therefore the software processing by the microcomputer 3 can sufficiently cope with it.

On the other hand, in the case of using a stationary scanner, as shown in FIG. 11, a laser light source 5 is provided in a box-shaped stand 4, and the laser beam from the light source 5 is deflected by a rotating polygon mirror 6. The reading window 7 on the stand 4 is scanned. Then, when the bar code is positioned on the window 7, the reflected light is received by the photodetector 8, and the signal from the photodetector 8 is binarized by amplifying and signal processing it in the binarizing circuit 9, and The digitized signal is quantized by the run length counter 10 into a digital amount corresponding to the width of the bar, and the digital signal is processed by the bar code recognition circuit 11 to determine the margin, the guard bar, the bar code or not, the character It is known that decoding is executed in real time at high speed, and thereafter, character editing, checking (parity check, modulus check), and interface which can be performed at relatively low speed are executed by the microcomputer 12. That is, in the case of using a stationary scanner, since the barcode is scanned at a high speed by using a laser beam, it is not possible to directly input the data processed by the run length counter 10 to the microcomputer 12 and process it in software. Since it is impossible because the speed is required, the barcode recognition circuit 11 is used to perform the high-speed processing part by hardware and then the microcomputer 12 processes it.

[Problems to be Solved by the Invention] However, since the conventionally used barcode recognition circuit 11 has a logic circuit configuration for performing all of margin, guard bar determination, barcode determination, and character decoding. The problem is that the circuit configuration becomes quite complicated, and if the recognition logic such as decoding or algorithm is changed or modified, the logic circuit configuration of the barcode recognition circuit 11 must be changed for that purpose, which is a very troublesome task. was there.

According to the present invention, only the detection of the bar code information is performed by the hardware process, and the bar code recognition process is performed by the software by the microcomputer. Therefore, if the recognition logic is changed or modified, it can be dealt with only by changing the program. SUMMARY OF THE INVENTION An object of the present invention is to provide a bar code reader which can relatively easily change or modify the recognition logic and can relatively easily configure the logic circuit of the hardware part.

[Means for Solving Problems] The present invention relates to a bar code detecting section, a binarizing circuit which processes a signal from the bar code detecting section and outputs a binarized signal, and the binarizing circuit. The run length counter for converting the binarized signal from the to the run length data, one or a plurality of shift registers for storing the counter output, the binarized signal from the binarization circuit and the data from the run length counter. A bar code pattern detection circuit for inputting and detecting a bar code pattern and a bar code recognition process in response to a bar code detection signal from the bar code pattern detection circuit to take in data of one or a plurality of shift registers Alternatively, the bar code pattern detection circuit is composed of a plurality of microcomputers, and the bar code pattern detection circuit sequentially operates in response to a change in the binarized signal and outputs one bar code. A plurality of counters that perform a counting operation in a character cycle, and a plurality of latch circuits that respectively latch the data of each counter,
A character width variation detecting circuit that detects variations in the character width in response to the outputs of the respective latch circuits and the respective counters, and it is determined in response to the outputs of the detection circuit that the variations in the character width continue within the specified range. And a data holding circuit for holding the data obtained by multiplying the data for one character at that time by a constant value that determines the specified lower limit value of the variation of the character width when this determination circuit determines continuity, The comparison output circuit compares the data held in the data holding circuit with the data of the run length counter, and outputs a bar code detection signal when the counter data becomes larger than the data of the holding circuit.

[Operation] In the present invention having such a configuration, the read data of the bar code binarized by the binarization circuit is quantized by the run length counter to become run length data, which is stored in the shift register.

On the other hand, in response to a change of 0 or 1 in the binarized signal, a plurality of counters are sequentially operated, and each performs a count operation in one character cycle of the bar code, and the count data of each counter is latched by a latch circuit. Then, the variation of the character width is detected by the output of each latch circuit and the output of each counter, and it is determined whether or not the variation is continuous within the regulation.

Then, it is judged that the fluctuation is continuous within the regulation, and at that time, the data obtained by multiplying the data for one character by a constant value is compared with the data of the run length counter, and when the data of the counter is larger, the bar code information is obtained. A bar code detection signal for notifying the microcomputer that the data has been stored in the shift register is output to the microcomputer. As a result, the microcomputer reads the data stored in the shift register and performs a barcode recognition process.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a laser light source 22 is provided in a box-shaped base 21, and a laser beam from the light source 22 is deflected by a rotating polygon mirror 23 to read a reading window on the base 21.
It scans 24 surfaces. When, for example, a bar code attached to the product is located on the upper surface side of the window 24, the laser beam is reflected by the bar code, and the reflected light is the light receiver.
It is designed to be received by 25.

The output signal from the light receiver 25 is input to the binarization circuit 26,
The binarizing circuit 26 performs binarization by performing amplification, signal processing and the like. The binarized signal from the binarization circuit 26 is input to a run length counter 27 and quantized by the counter 27 into a digital amount corresponding to the width of the bar.

The digital data quantized by the run-length counter 27 is supplied to a FIFO (first-in-first-out) register 28 having a storage capacity of, for example, 256 bytes, in which data that is a kind of shift register is first-in / first-out. .

The binarized signal from the binarization circuit 26 and the digital data from the run length counter 27 are supplied to the bar code pattern detection circuit 29. The bar code pattern detection circuit 29 detects a bar code pattern by using the input binarized signal and digital data, and outputs the FIFO register 28.
The microcomputer 30 is informed by a bar code detection signal that the bar code information is stored in.

When the barcode detection signal is input from the barcode pattern detection circuit 29, the microcomputer 30 reads the data in the FIFO register 28 by interruption and performs the barcode recognition process.

The circuit composed of the run length counter 27, the FIFO register 28 and the bar code pattern detection circuit 29 is specifically constructed as shown in FIG.

That is, the binarized signal from the binarization circuit 26 is input to a circuit composed of the two-stage D-type flip-flops 31, 32 and the exclusive OR circuit 33 to generate the edge signal EDG. Further, the edge signal EDG is input to the D-type flip-flop 34 to produce an edge signal EDG '. The clock CLK generated from the clock generator 35 is input to the clock input terminals CK of the flip-flops 31, 32 and 34, respectively.

That is, when the binarized signal is input as shown in FIG. 3A, the flip-flop 31 receives the clock CLK shown in FIG. The flip-flop 32 operates at the timing shown in FIG. 3 and receives the output of the flip-flop 31 and the clock CLK to operate at the timing shown in FIG.
The edge signal EDG shown in FIG. 3 (e) is output from 33. Then, the edge signal EDG and the clock CLK are input to the flip-flop 34, and the flip-flop 34
Outputs an edge signal EDG 'shown in FIG. 3 (f).

The edge signal EDG is ANDed with the write enable from the microcomputer 30 and is supplied to the FIFO register 28 as a write signal. Note that the data can be read from and read from the FIFO register 28 by the microcomputer 30.
It is designed to be performed by a read clock from the.

The edge signal EDG 'is supplied to the clear terminal CLR of the run length counter 27. The run-length counter 27 is, for example, a 9-bit counter, and inputs the clock CLK from the clock generator 35 to the clock input terminal CK to count the width of the bar into digital data having the clock CLK as a minimum unit. I have to.

The edge signal EDG is also input to the G input terminal of the 2-bit counter 36 and the decoder 37. Counter 36
The Q _A and Q _B outputs are input to the A and B input terminals of the decoder 37, respectively, and are also input to the A and B input terminals of the 7-bit multiplexers 67 and 68, respectively.

That is, the counter 36 receives the edge signal EDG shown in FIG. 4 (b), sends out the Q _A output shown in FIG. 4 (c), and outputs the Q _B output shown in FIG. 4 (d). Send out. The decoder 37 receives the edge signal EDG and the Q _A output and the Q _B output from the counter 36 and receives the respective input / output terminals Y ₀ , Y ₁ ,
From Y ₂ and Y ₃ to the output E ₀ shown in (e) of FIG. 4, the output E ₁ shown in (f) of FIG. 4, the output E ₂ shown in (g) of FIG. The output E ₃ shown in h) is output.

The outputs E ₀ , E ₁ , E ₂ , E ₃ from the decoder 37 are supplied to the clear terminals CLR of the four 7-bit counters 38, 39, 40, 41. The clock CLK from the clock generator 35 is supplied to the clock input terminal CK of each of the counters 38 to 41 by the 1/4 frequency divider 42.
The clock CLK ′ divided by 1/4 is input.

The counter data of the counters 38, 39, 40, 41 are latched by four 7-bit latch circuits 43, 44, 45, 46, respectively. The outputs E ₀ , E ₁ , E ₂ , E _{3 of the} decoder 37 are input to the clock input terminals CK of the latch circuits 43 to 46, respectively.

The data latched by each of the latch circuits 43 to 46 is input to the input terminals X ₀ , X ₁ , X ₂ , and X ₃ of the _one multiplexer 67 described above, and the count data of each of the counters 38 to 41 is described above. Input terminal of the other multiplexer 68
Inputting in X ₀ , X ₁ , X ₂ , X ₃ . Each multiplexer 67,
68 receives the outputs Q _A and Q _B of the counter 36 and receives an input terminal X
_The data input to ₀ , X ₁ , X ₂ and X ₃ are selectively output from the output terminal Y.

The output data from the multiplexer 67 is supplied to the 28/32 multiplier 4
Supply to 7 and 36/32 multiplier 48. The 28/32 multiplier 47 is, for example, a 7-bit subtractor as shown in FIG. 6, and the output F is AB, which connects A _{0 to} A ₆ and B _{0 to} B ₆ as shown in the figure. As a result, A−A / 8 = 7 / 8A = 28 / 32A
Becomes And by using the subtractor in this way, multiplication can be performed in real time. The 36/32 multiplier 48 can be realized by replacing the subtractor used in the 28/32 multiplier 47 with an adder. That is, F = A + A / 8 = 9/8
A = 36 / 32A.

The output of the 28/32 multiplier 47 is supplied to the 7-bit comparator 49 as data A and the 7-bit latch circuit 50
Is being supplied to. The output of the 36/32 multiplier 48 is supplied to the 7-bit comparator 51 as data A. The output from the multiplexer 68 is also input as the data B to the comparators 49 and 51.

The comparator 49 compares the data A and the data B,
A signal is output when A ≦ B, the comparator 51 compares the data A with the data B, and a signal is output when A ≧ B. Then, the logical product of the signal outputs from the comparators 49 and 51 and the write enable from the microcomputer 30 is taken. The multipliers 47 and 48 and the comparators 49 and 51 constitute a character width variation detection circuit, and the ratio of the current character width to the previous character width is ± 12.5% by this circuit.
It will detect whether it is within the range of.

JK flip-flops 52,53,54 and 55,56,57 and 58,59,60
The circuit constituted by 61, 62, 63 is a judgment circuit for judging whether or not the variation of the character width of consecutive characters, which is inputted with the logical product output, continues for 4 characters within the regulation (within ± 12.5%). In each of the flip-flops 52 to 63, the flip-flops 52 to 54 operate in synchronization with the output E _{3 of the} decoder 37, and the flip-flops 55 to 57 output the decoder 37.
Operates in synchronization with E _2, as flip-flops 58 to 60 is activated and the output E ₁ in synchronism with the decoder 37, and flip-flops 61 to 63 are operated in synchronization with the output E ₀ of the decoder 37 Has become.

Bar codes generally called UPC and JAN codes are known to be the standard version shown in (a) of FIG. 8 and the shortened version shown in (b) of FIG. It is expressed in 7 modules. In addition,
One module refers to the minimum dimension that constitutes a bar or space. Therefore, in order to distinguish the bar code from other information and noise, this regularity (1 character, that is, 4 consecutive bars, the length of the space is approximately equal to the length of the adjacent character continues for 4 or more characters) can be examined. It will be good. The determination circuit described above does this.

For example, considering the case where the bar code is the shortened version shown in FIG. 8B, as shown in FIG.
When the digitized signal is input, the output E ₀ from the decoder 37 as shown in FIGS. 5 (b), (c), (d) and (e),
E ₁ , E ₂ , and E ₃ are output. Considering now the flip-flops 52 to 54, the flip-flop 52 operates in synchronization with the output E ₃ as shown in (f) of FIG. Then, the flip-flop 53 responds to the output of the flip-flop 52 and outputs the signal shown in (g) of FIG.
54 is the output of the flip-flop 53 and each comparator 49, 51
The signal shown in (h) of FIG. 5 is output by the logical product with the logical product output of. That is, at the time of the output E ₃ of the decoder 37, the logical product output of the comparators 49 and 51 may be at the high level, but at the next time, the margin (7 modules) + guard bar (3 modules)> 1 character (7 modules), the logical product output becomes low level, and the flip-flops 52 and 53 are cleared. At the further point in time, the current character width and the previous character width become substantially equal, so the logical product output becomes high level, and the flip-flop 52 is set at the rise of the output E ₃ . At the same time, the current character width and the previous character width are almost equal, so the logical product output goes high and the output E ₃ rises and the flip-flop rises.
52 flipped and reset, instead flip-flop
53 is set. The same is true at the further point in time, and the flip-flop 52 is set, and further the flip-flop 54 is set. The same is true at the further time point, and the flip-flop 52 is reset and the flip-flop 53 is reset.

In this way, the flip-flop 54 is set when the character widths of four consecutive characters are substantially equal to each other and outputs a set signal to the AND gate 65 via the OR gate 64.

The latch circuit 50 rises to 28 when the output of the OR gate 64 rises.
Latch the output of the / 32 multiplier 47. That is, the latch circuit 50 has the character width of the determined 7 modules.
Data of 28/32, that is, a width of about 6 modules will be latched. The data of the latch circuit 50 is supplied to the 7-bit comparator 66 as B data.
The comparator 66 still has the run length counter.
27 count data are input as A data.
Then, this comparator outputs a signal to the unload gate 65 when A> B, that is, when the width indicated by the data of the run length counter 27 becomes larger than the width indicated by the data of the latch circuit 50. Then, at this timing, a bar code detection signal is output from the AND gate 65 to the microcomputer 30, and the microcomputer 30 is interrupted. At this time, the run length data corresponding to the margin is stored in the last byte of the FIFO register 28, and the data judged to be the bar code information before that is stored.

When the microcomputer 30 reads the data stored in the FIFO register 28, it performs the barcode recognition process shown in FIG. First, the positions of the margin and the guard bar are searched. Subsequently, the bar code in the first half is decoded character by character, the center bar is confirmed, and then the bar code in the latter half is decoded character by character. And finally the margin on the other side,
When the guard bar is detected, the parity check is performed subsequently, and the modulus check is further performed. If there is an abnormality in these two checks, it is regarded as an error. Also this 2
If all the two checks are OK, the decoded data is transferred to, for example, the product sales data processing unit.

In the present embodiment having such a configuration, the run length processing is performed based on the binarized signal of the signal read by the bar code pattern detection circuit 29, and the information stored in the FIFO register 28 is the bar code information. If it is determined that there is barcode information, it is controlled to interrupt the microcomputer 30 to read the information stored in the FIFO register 28. Since the program processing is performed by the computer 30, the portion requiring high-speed processing can be processed by the hardware circuit of the barcode pattern circuit 29, and the microcomputer 30 only needs to perform the barcode recognition processing. it can. When changing or correcting the recognition logic such as decoding or algorithm, the barcode pattern detection circuit 29 can be used without any change, and only the program of the microcomputer 30 needs to be changed, so it is necessary to recreate the hardware circuit. The change work can be done very easily.

Further, the bar code pattern detection circuit 29 only needs to have a circuit configuration for detecting whether or not it is pattern information, and does not need to perform bar code recognition processing or character decoding as in the conventional case, so that the hardware circuit part The configuration of can be simplified.

In the above embodiment, one FIFO register and one microcomputer are used, but the present invention is not limited to this. For example, as shown in FIG. 9, two FIFO registers 281, 282 are used. If a master microcomputer 301 and a slave microcomputer 302 are provided, and the microcomputer 301 controls the switching unit 71 so that the information is alternately loaded into the registers 281, 282, it is possible to sufficiently deal with the use of a microcomputer with a slow processing speed. can do. In this case, the master microcomputer 301 will edit the read data.

In the above embodiment, the clock CLK 'used by the run-length counter is divided by 1/4 to count the character width, but the clock CLK' is not limited to this.

Further, in the above-described embodiment, the multiplexer is used to select the data from each latch circuit, but the present invention is not limited to this, and the multiplexer is not used.
2 multiplier, 36/32 multiplier and 7-bit comparator 49, 51
It is possible to realize a circuit having the same function even if each of the outputs E _{0 to} E ₃ is individually provided and configured.

Further, in the above embodiment, the regulation of the variation of the character width is ± 1.
Although it is set within 2.5%, this value is not necessarily limited to this value and may be set arbitrarily according to the conditions.

[Effects of the Invention] As described in detail above, according to the present invention, only the detection of whether the information is barcode information is performed by hardware processing, and the barcode recognition processing is performed by software by a microcomputer. It is possible to provide a bar code reading device in which the change and correction of the recognition can be dealt with only by changing the program, and the change and correction of the recognition logic can be relatively easily performed and the logic circuit configuration of the hardware part can be relatively easy. .

[Brief description of drawings]

1 to 8 show an embodiment of the present invention. FIG. 1 is a block diagram partially including a schematic configuration, and FIG. 2 shows a specific circuit configuration of the bar code pattern detection circuit in FIG. The circuit diagram, FIG. 3, FIG. 4 and FIG. 5 are timing waveform diagrams showing the operation timing of each part of FIG. 2, and FIG. 6 is a diagram showing the configuration of the 28/32 multiplier of FIG. FIG. 7 is a flow chart showing the barcode recognition processing by the microcomputer,
FIG. 8 shows an example of a bar code, (a) is a standard version bar code diagram, (b) is a shortened version bar code diagram, and FIG. 9 is a block diagram showing another embodiment of the present invention. , FIG. 10 and FIG. 11 are block diagrams showing a conventional example. 22 …… Laser beam, 25 …… Receiver, 26 …… Binarization circuit,
27 …… Run length counter, 28 …… FIFO register, 29
…… Bar code pattern detection circuit, 30 …… Microcomputer, 36 …… 2-bit counter, 37 …… Decoder,
38-41 …… 7-bit counter, 43-46 …… 7-bit latch circuit, 47 …… 28/32 multiplier, 48 …… 36/32 multiplier, 49,5
1 …… 7-bit comparator, 50 …… 7-bit latch circuit, 52 to 63 …… JK flip-flop, 66 …… 7-bit comparator.

Claims (1)

[Claims] 1. A bar code detecting section, a binarizing circuit for processing a signal from the bar code detecting section and outputting a binarized signal, and a run length of the binarizing signal from the binarizing circuit. A run length counter for converting to data, one or a plurality of shift registers for storing the counter output, a binarized signal from the binarization circuit and data from the run length counter are input to detect a bar code pattern. And a bar code pattern detection circuit that operates in response to a bar code detection signal from the bar code pattern detection circuit.
Or one or a plurality of microcomputers for fetching data from a plurality of shift registers and performing a barcode recognition process, wherein the barcode pattern detection circuit sequentially and in response to a change in a binarized signal A plurality of counters that perform a counting operation in one character period, and a plurality of latch circuits that respectively latch the data of the respective counters,
A character width variation detecting circuit that detects variations in the character width in response to the outputs of the respective latch circuits and the outputs of the counters, and a variation of the character width in response to the outputs of the detection circuit are continuously within a specified range. A judgment circuit for judging, and a data holding circuit for holding data obtained by multiplying the data for one character at that time by a constant value for determining a prescribed lower limit value of fluctuation of the character width when this judgment circuit judges continuity. A comparison output circuit for comparing the data held in the data holding circuit with the data of the run length counter and outputting a bar code detection signal when the data of the counter becomes larger than the data of the holding circuit. Bar code reader characterized by.