JPH07105155B2 - Programmable semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a programmable semiconductor integrated circuit, and in particular, an electrically writable programmable element is 2 ^m rows ×
The present invention relates to a programmable semiconductor integrated circuit having memory cell arrays arranged in 2 ⁿ columns (m and n are both natural numbers).

[Conventional technology]

Conventionally, this type of programmable semiconductor integrated circuit (hereinafter,
Various methods have been announced for PROM), and is usually a fuse type that uses nichrome or the like as a memory cell.
A PROM and a junction destruction type PROM using an open base transistor as a memory cell are generally known.

The read and program operations of these PROMs will be described using a junction destruction PROM as an example. FIG. 2 is a circuit diagram showing an example of a junction destruction type PROM using an open base transistor as a memory cell.

Memory cell Q ₁₁ to Q _4m is a collector row line X ₁ to X _m, the emitter are respectively connected to the column lines Y ₁ to Y _4, and the row lines X ₁ ~
X _m are respectively guided to the row selection circuit 1. Column line Y ₁ ~
Y ₄ is connected to the resistors R _{6 to} R ₉ through the diodes D _{1 to} D ₄ , respectively, and is further connected to the column selection diode matrix composed of the diodes D _{5 to} D ₁₂ and the output circuit 3. The address terminals A ₀ and A ₁ are connected to the address circuits G ₁ and G ₃ respectively.
And their outputs are connected to address circuits G ₂ and G ₄ . The output of these address circuits is a diode
It is connected to a column selection diode matrix consisting of D _{5 to} D ₁₂ . Although the chip select terminal CS is connected to the chip select circuit 4 and the output of the chip select circuit 4 is connected to the output circuit 3, the output circuit 3 is activated / inactivated according to the input level of the chip select terminal CS. Is controlled.

In the read operation, the output circuit 3 is activated via the chip select terminal CS and the chip select circuit 4 and then the row line X ₁ is selected by the row selection circuit 1 and the address terminal A _0. Taking the case where all the levels at, A ₁ are "L" level as an example, the address circuits G ₁ , G _1
3 output is “H” level, address circuits G ₂ and G ₄ output is “L”
It becomes a level. As a result, the column lines Y _{1 to} Y ₃ are connected to the diodes D ₁ to Y _3.
The currents in the resistors R _{6 to} R ₈ connected via D ₃ are respectively caused by the diodes D ₅ , D ₆ ,, in the column selection diode matrix.
Since it flows into the address circuits G ₂ and G ₄ in the “L” level state through D ₈ and D ₉ , it is suppressed to a low level and becomes a non-selected state. In this state, the column line Y ₄ is in the selected state because the current of the resistor R ₉ connected through the diode D ₄ is not pulled by the address circuit.

In the above state, the selected column line Y ₄ and row line X ₁
If the memory cell Q ₄₁ connected to the selected memory cell is the selected memory cell and this memory cell Q ₄₁ is in the unwritten state, the current flowing through the resistor R ₉ is supplied to the output circuit 3 and is set in the written state. If so, the current flowing through the resistor R ₉ flows into the row selection circuit 1 from the diode D ₄ through the written memory cell Q ₄₁ , and is not supplied to the output circuit 3.
Therefore, the state of the output circuit 3 changes depending on whether or not the current of the resistor R ₉ is supplied to the output circuit 3, and as a result, the content of the selected memory cell is output from the output terminal OUT. . The above is the description of the operation during reading.

On the other hand, during the program operation, the output circuit 3 is connected via the chip select terminal CS and the chip select circuit 4.
Is deactivated, the row selection circuit 1 and the address terminals are
A _0, the address circuit G ₁ that is by connexion determined level state of the A ₁
By the level of ~G _4, are respectively the row and column lines are selected, the memory cells connected to the selected row and column lines, the program power from the output terminal OUT (e.g. pulsed constant current) A predetermined program is formed by applying the voltage. The diodes D _{1 to} D ₄ prevent the program power applied from the output terminal OUT from flowing out to the address circuits G _{1 to} G ₄ and the output circuit 3 through the column selection diode matrix, and to the selected memory cell. It is provided to allow inflow.

[Problems to be Solved by the Invention]

In the conventional programmable semiconductor integrated circuit described above, for example, in the case of the conventional example, the address terminals A ₀ and A ₁ are set to the “L” level in order to deselect the column lines during the read operation and the program operation. At times, the current in resistors R ₆ -R ₈ is driven by diodes D ₅ , D in the column select diode matrix.
Through ₆ , D ₈ and D ₉ , the output side flows into the address circuits G ₂ and G ₄ in the “L” level state. It is clear that this current is always present during the read operation and is consumed as part of the power supply current. In the conventional example of FIG. 2, the number of output terminals is one, but as the number of outputs increases,
The amount of current required to deselect a column line increases proportionally. Therefore, in order to increase the capacity of the PROM like a general LSI, the number of the column lines inevitably increases, and the power supply for deselecting the column lines other than the column line to be selected. Since the amount of current is greatly increased, it has a drawback that it is a great obstacle to increasing the capacity of the PROM.

[Means for Solving the Problems]

In the programmable semiconductor integrated circuit of the present invention, electrically writable programmable elements are 2 ^m rows × 2 ⁿ columns (m,
In a programmable semiconductor integrated circuit having at least a memory cell array arranged with n being a natural number and a column selection circuit and an output circuit for decoding the 2 ⁿ column lines by n address inputs, each of the emitters has a cathode. Are connected to the anodes of the diodes connected to the corresponding column lines, the bases are connected to the corresponding column selection circuits, and the collectors are each provided with 2 ⁿ transistors commonly connected to the output circuit. Composed.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a row selection circuit 1, a writing circuit 2, an output circuit 3, a chip selection circuit 4, memory cells Q _{11 to} Q _4m , and diodes D _{1 to} D. ₄ and transistor
And Q ₁ to Q _4, a diode D ₅ to D ₁₂ forming a column selection diode matrix, and a resistor R ₁ to R _5, the address circuit G ₁ ~G
₄ and.

In FIG. 1, the present invention is different from the conventional example shown in FIG. 2 in that the emitters are diodes D ₁ respectively.
It is connected to the column line Y ₁ to Y ₄ through to D _4, diode D ₅ whose base forms a column selection diode matrix respectively
~ D ₁₂ and collectors are output circuit 3 respectively
That is, a predetermined number of transistors Q _{1 to} Q _{4 that} are connected to each other are incorporated.

In the read operation, as in the case of the conventional example, the output circuit 3 is activated and then the row selection circuit 1 causes the row line X ₁
For example, when is selected, and when the levels at the address terminals A ₀ and A ₁ are all “L” level,
The output of the address circuits G ₁ and G ₃ is at "H" level, and the address circuit G
The output of ₂ and G ₄ becomes “L” level. Therefore, the resistors R _{1 to} R ₃
The current flowing in the transistors Q _{1 to} Q ₃ flows into the address circuits G ₂ and G ₄ in the “L” level state through the diodes D ₅ , D ₆ , D ₈ and D ₉ in the column selection diode matrix, respectively. No current is supplied to the base.
Slave go-between, the transistor Q ₁ ~Q ₃ in a state of off, the column lines
Y ₁ to Y ₃ is in a non-selected state.

On the other hand, the current flowing through the resistor R ₄ is supplied to the transistor 4 as the base current without being pulled by the address circuit, so that the column line Y ₁ is in the selected state.

If the memory cell Q ₄₁ connected to the column line Y ₄ and the row line X _{1 in} this selected state is the selected memory cell and the memory cell Q ₄₁ is in the unwritten state, the resistor R ₄ flows. Current flows from the base of transistor Q ₄ to the collector, and
It is supplied to the output circuit 3 together with the current flowing through the resistor R ₅ . Conversely, if there is a memory cell Q ₄₁ that is selected in the write state, the current flowing through the resistor R ₄ is supplied as a base current of the transistor Q _4, the transistor Q ₄ is turned on and the summer, it flows through the resistor R ₅ Along with the current, it flows into the row selection circuit 1 through the diode D ₄ and the memory cell Q ₄₁ in the written state, and the current is not supplied to the output circuit 3.

Therefore, the operation state of the output circuit 3 changes depending on whether or not the currents of the resistors R ₄ and R ₅ are supplied to the output circuit 3, and as a result, the contents of the selected memory cell Q ₄₁ are changed. It appears at the output terminal OUT through the output circuit 3.

As is clear from the above description, the operation as the reading function of this embodiment is the same as that of the above-mentioned conventional example.

On the other hand, during the program operation, the output circuit 3 is deactivated and the row selection circuit 1 is operated, as in the conventional example.
And the level of the address circuits G _{1 to} G ₄ determined by the level state of the address terminals A ₀ and A ₁ respectively select the row line and the column line, and connect to the selected row line and column line. By applying program power (for example, pulsed constant current) from the output terminal OUT to the memory cell
A predetermined program is formed. The diodes D _{1 to} D ₄ are
It is provided to prevent the program power applied from the output terminal OUT from flowing out to the address circuits G _{1 to} G ₄ and the output circuit 3 through the column selection diode matrix and to flow into the selected memory cell. Has been. The operation in this case is similar to that in the conventional example.

As described above, in the present embodiment, the current consumption in the column line depends on the current of the resistors R ₄ and R _{5 related to} the selected column line Y ₄ and the “L” level on the output side. To the addressing circuits G ₂ and G ₄ through the diodes D ₅ , D ₆ , D ₈ and D ₉ through the resistors R _{1 to} R ₃ . On the other hand, the current consumption of the column line in the above-mentioned conventional example is the current of the resistor R _{9 related to} the selected column line Y ₄ and the address circuits G ₂ and G ₄ whose output side is at “L” level. The resistances R _{6 to} R ₈ flowing in through diodes D ₅ , D ₆ , D ₈ and D _9.
It depends on the current of.

Below, a comparison of the magnitude of the current consumption of the column lines between the present embodiment and the conventional example will be explained. Related to the selected column line Y ₄ above. The current flowing through the resistor R ₉ in the conventional example and the current flowing through the resistors R ₄ and R ₅ in this embodiment are set to the same current in terms of the read function. In the conventional example, if the selected memory cell is in the write state, the selected column line
Assuming that the potential of Y ₄ is V ₁ power supply voltage is Vcc and the voltage drop of the diode D ₄ is V ₂ , the consumption current I ₁ flowing through the resistor R ₉ is given by the following equation.

I ₁ = (Vcc-V ₁ -V ₂ ) / R ₉ (1) On the other hand, in the present embodiment, the potential difference between the collector and the emitter of the transistor Q ₄ in the on state is V ₃ , and the base and the emitter. If the potential difference between them is V ₄ , the consumption current I ₂ flowing through the resistors R ₄ and R ₅ is given by the following equation.

_{I 2 = (Vcc-V 1} -V 2 -V 3) / R 5 + (Vcc-V 1 -V 2 -V 4) /
R ₄ (2) If the grounded emitter current amplification factor of the transistor Q ₄ is β, the current flowing through the resistor R ₅ may be β times the current flowing through the resistor R ₄ , so the resistor R ₄ is _It turns out that the resistance value (R ₄ >> R ₅ ) is much higher than that of ₅ . In addition, the potential difference V ₃ between the collector and the emitter of the transistor Q ₄ which is on.
Is a minute voltage of about 0.1 to 0.3 V, the current I ₂ is approximately represented by the following equation.

I ₂ ≈ (Vcc-V ₁ -V ₂ ) / R ₅ (3) Therefore, the value of the resistor R ₅ in this embodiment should be set equal to the value of the resistor R ₉ in the conventional example. For example, it can be seen that the values of the consumption currents I ₁ and I ₂ are almost equal (I ₁ ≈I ₂ ). Therefore, if the selected memory cell is in the unwritten state, the selected column line Y ₄ in the conventional example and the present embodiment is selected.
Current consumption is the same. If the voltage on the output side of the address circuit in the “L” level state is V ₅ , and the voltage drop of each of the diodes D ₅ , D ₆ , D ₈ and D ₉ is V ₆ , the current consumption of the column line in the conventional example is I _P1 is R ₆ = R ₇ = R ₈ = R _9
9, when expressed as a representative of the resistance R _6, R _7, R ₈ and R _9,
Corresponding to the current consumption I ₁ of the selected column line Y ₄ , it is given by the following equation.

I _P1 = I ₁ + 3 × (Vcc−V ₅ −V ₆ ) / R ₉ (4) On the other hand, the column line current consumption I _P2 in this embodiment is R ₁ = R ₂
= From R ₃ = R _4, and R _4, expressed as a representative of the resistance R _1, R _2, R ₃ and R _4, in response to the consumption current I ₂ of the column lines Y ₄ selected, the following formula Given.

I _P2 = I ₂ + 3 × (Vcc−V ₅ −V ₆ ) / R ₄ (5) From the above equations (4) and (5), the column lines Y _{1 to} Y ₄ in the conventional example and the present example are obtained. The difference in current consumption of is expressed by the following equation by introducing the condition of I ₁ ≈I ₂ .

_{ΔI P = 3 × [(Vcc} -V 5 -V 6) / R 9 - (Vcc-V 5 -V 6) /
R ₄ ] ... (6) From the above formula (6), it can be seen that the difference in consumption current ΔI _P = I _P1 −I _P2 is affected by the difference in resistance values of the resistors R ₉ and R ₄ . As described above, since R ₄ >> R ₉ , for example, assuming that the grounded-emitter current amplification factor of the transistor Q ₄ is 20,
(Resistance value of the resistor R ₉ ) × 20 = (Resistance value of the resistor R ₄ ), and in this case, the consumption current difference ΔI _P
Is given by the following equation (7).

_{ΔI P = [3 × (Vcc} -V 5 -V 6) / R 4] × (19/20) ......
(7) That is, it can be seen that the current consumption of the non-selected column line is 95% smaller in the present embodiment than the current consumption in the conventional example.

In the above description, the operation has been described for the case of four column lines. Generally, when the number of column lines is k (k is a natural number), equation (7) is Given in.

_{ΔI P = [(K-1} ) × (Vcc-V 5 -V 6) / R 4] × (19/2
0) (8) As is clear from the equation (8), as the number of column lines increases,
The difference in current consumption ΔI _P of the column line between the conventional example and the present invention is
It increases in proportion to the number of line lines. This means that, by applying the present invention, as the number of column lines increases, the current consumption of the column lines decreases almost proportionally to the number of column lines as compared with the case of the conventional example. It shows that.

Further, in the above embodiment, the case of the junction destruction type PROM has been described as an example, but it goes without saying that the present invention can be similarly applied to other fuse type PROMs.

〔The invention's effect〕

As described above in detail, according to the present invention, in a programmable semiconductor integrated circuit, by providing a transistor in which an emitter is connected to a column line, a base is connected to a column selection circuit, and a collector is connected to an output circuit, It is possible to significantly reduce the current consumption of the column line, and it is possible to provide a programmable semiconductor integrated circuit including a large-capacity PROM with low current consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
It is a circuit diagram of a prior art example. In the figure, 1 ... Row selection circuit, 2 ... Writing circuit, 3
...... Output circuit, 4 …… Chip select circuit, Q _{1 to} Q ₄ ……
Transistors, R _{1 to} R ₉ ...... Resistors, D _{1 to} D ₁₂ ...... Diodes, G _{1 to} G ₄ ...... Address times, Q _{11 to} Q _{4 m} ...... Memory cells.

Claims (1)

[Claims] 1. A memory cell array in which electrically writable programmable elements are arranged in 2 ^m rows × 2 ⁿ columns (m and n are both natural numbers), and the column lines of the 2 ⁿ columns are n addresses. A column selection circuit and an output circuit for decoding by input,
In a programmable semiconductor integrated circuit having at least, an emitter is connected to an anode of a diode whose cathode is connected to a corresponding column line, a base is connected to the corresponding column selection circuit, and a collector is connected to the output circuit, respectively. A programmable semiconductor integrated circuit comprising 2 ⁿ transistors connected in common.