JP3010664B2 - Programmable read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a programmable read only memory (hereinafter referred to as P-
In particular, the present invention relates to a P-ROM having fixed test memory cells.

[Prior Art] P-ROMs have the flexibility of allowing a user to write data to be stored for each memory cell for any reason, and are frequently used in various fields of information processing and control. FIGS. 3 (a) and 3 (b) show the storage cells of such a P-ROM.
(B) and a fuse blown type shown in FIGS. 4 (a) and 4 (b).

The junction breakdown type uses an element that becomes an open base transistor as indicated by 91 in FIG. 3A in an unwritten state, and keeps a non-conductive state in this state. When writing is performed by burning the cell between the emitter and the base and short-circuiting the cell, the cell becomes a diode-shaped transistor 92, as shown in FIG. 3 (b).

As shown in FIG. 4 (a), the fuse blown type is composed of a diode 93 and a fuse 94, and is in a conductive state in an unwritten state. FIG. 4 (b) shows the state of the cell after data writing.

By the way, there is a problem of writing yield when writing data to such a cell. As a conventional measure for improving yield, there is a dummy cell method.
This is because, in addition to a regular storage cell matrix, test fixed storage cells in which an appropriate logical information pattern has been written in advance in the manufacturing stage are added in the row direction and / or the column direction. Each function test is performed.

FIG. 5 shows a conventional P-ROM having such a dummy cell.
FIG. In this example, an unwritten state (this state is referred to as an intersection) between the eight row lines 000X to 111X selected by the row decoder 10 and the eight column lines 000Y to 111Y selected by the row decoder 20. (Set to “0”). Further, a dummy column line 70 is provided outside the column line,
Dummy cells 40 and 40a are alternately connected between this and each row line. Similarly, a dummy row line 80 is provided on the row line side, and dummy cells 40 and 40a are alternately connected between the dummy row line 80 and each row line. Here, the dummy cell 40 is an unwritten state (that is, a “0” state) cell having the same size as the regular storage cell 30, and the data “1” is previously written in the dummy cell 40 a at the manufacturing stage. It is a cell manufactured in a state. The test on the dummy cell column 52 and the dummy cell row 62 thus configured is performed as follows. The test for the dummy cell column 52 side is performed by accessing the dummy column line 70 and the row lines 000X to 111X decoded by the row decoder 10 and sequentially reading the dummy cells 40 and 40a. Are determined as non-defective products if they match, and defective if they do not match. The test on the dummy cell row 62 side is performed similarly. According to such a method, it is possible to detect some of the short-circuit failure between the row and the array wiring, the row and column decoding failure, and the failure of the output circuit.

FIG. 6 shows a conventional example in addition to a P-ROM in which dummy cells are arranged. In this figure, parts that are the same as the parts in FIG. 5 are given the same reference numerals. In this example, the dummy cell 40 in the unwritten state having the same shape as the normal memory cell 30 is arranged in each of the dummy cell column 53 and the dummy cell row 63. The test of the P-ROM on the side of the dummy cell column 53 is to write the dummy column line 70 and the dummy cell 40 selected by the row decoder 10 in accordance with the write specification used on the user side, and determine whether the write is successful. Performed by A similar test is performed on the dummy cell row 63 side. According to this method, by performing the same write test as the write specification on the dummy cell, a write characteristic test on a regular fixed storage cell can be equivalently performed in addition to the test items in the above-described conventional example. .

[Problems to be Solved by the Invention] Due to variations in the manufacturing process of the memory cell in the P-ROM, the area of the emitter and the base in the junction breakdown type shown in FIG. The fuse area of the fuse blown type a) varies. Since the area of each portion is directly related to the current value required for writing, the variation in these areas greatly affects the success or failure of the writing state. However, in the conventional P-ROM, there has been no effective means for determining whether or not the above-mentioned variation in each area is within an allowable range. The product had to be shipped as a non-defective product, so that the write failure rate on the user side could not be suppressed to a certain level or less.

[Means for Solving the Problems] A P-ROM according to the present invention includes regular fixed storage cells arranged in a matrix and a plurality of dummy cells extended in a row direction and / or a column direction. Wherein the dummy cell has an area of at least two different sizes, and a portion of the dummy cell has an area larger than that of the regular fixed storage cell and has a regular write area. It is configured to be writable on condition.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing one embodiment of the present invention. In this figure, the same parts as those of the conventional example of FIG. 5 are denoted by the same reference numerals, and the duplicate description will be omitted.

In this embodiment, as shown in FIG.
In the above, dummy cells 40a in which "1" has been written in advance in the manufacturing stage and dummy cells (41, 42, 43) in an unwritten state are alternately arranged. Among the dummy cells in the unwritten state, the dummy cell 41 has a shape smaller than the regular fixed storage cell 30 (reduced by 5% in area), and the dummy cell 42 has a shape slightly larger than the cell 30 (increased in area by 5%). Further, the dummy cell 43 is formed in a shape larger than the cell 30 (increase in area by 10%). Also in the dummy cell row 60, the dummy cells 40a in which “1” has been written and the dummy cells (41, 4
2, 43) are arranged alternately.

By using the dummy cell column 50 and the dummy cell row 60 in the state of this chip, the short circuit failure between the row and column wiring, the failure of the row or column decoder, and the failure of the output circuit can be achieved as in the conventional example of FIG. Part can be detected.

Further, by writing data to the dummy cells 41 to 43 in an unwritten state, it is possible to determine the degree of variation of the storage cells as follows. Now, for a normally manufactured product, it is assumed that data can be normally written to the dummy cells 41 and 42 but cannot be written to the dummy cell 43 (that is, a normal write current is required for writing to the dummy cell 43). Is too small).

In the write test, it is tested whether or not the product can be written into the dummy cell as described above. As a result of the test, if the dummy cell 43 could be written, the memory cell of the product is abnormally small and is determined to be defective. On the other hand, if writing to the dummy cell 42 cannot be performed, the product is determined to be defective because the storage cell is manufactured abnormally large.

FIG. 2 is a block diagram showing another embodiment of the present invention.
The difference of this embodiment from the previous embodiment is that
The point is that all the dummy cells in the dummy cell row 61 and the dummy cell row 61 are in the unwritten state. That is, the dummy cell column 51 (dummy cell row 61) is composed of a dummy cell 41 having an area smaller than the area of the regular storage cell 30, a dummy cell 40 having the same area, a dummy cell 42 having a somewhat larger area, and a dummy cell 43 having a larger area. I have. According to this embodiment, similarly to the previous embodiment, it is possible to test whether or not the dimensional variation of the product is within an allowable range. In addition, the maker side performs writing based on the writing specifications used by the user side. Testing can be performed.

[Effects of the Invention] As described above, the present invention provides a P-ROM with:
According to the present invention, since the area of the unwritten cell of the test fixed memory cell added to the fixed memory cell is set to various sizes as compared with the fixed memory cell,
A write test that also serves as a determination as to whether or not manufacturing variations are within an allowable range can be performed. Therefore, according to the present invention, it is possible to provide a high-quality P-ROM with little variation and high write yield. Further, by feeding back the test data relating to the variation to the manufacturing line, appropriate process management can be performed, and a product with less variation can be manufactured.

[Brief description of the drawings]

FIGS. 1 and 2 are configuration diagrams showing an embodiment of the present invention, respectively, and FIGS. 3 (a) and 3 (b) and FIGS. 4 (a) and 4 (b).
Is a circuit diagram of a fixed storage cell, and FIGS. 5 and 6 are configuration diagrams of a conventional example. 10: row decoder, 20: column decoder, 30: regular fixed storage cell, 40 to 43: dummy cell (unwritten state), 40a: dummy cell to which "1" is written, 50 to 53
... Dummy cell column, 60 to 63... Dummy cell row, 70... Dummy column line, 80.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 17/00 G11C 17/06

Claims (1)

(57) [Claims] 1. A plurality of row lines, a plurality of column lines, a row line selection circuit for selecting a target row line from the plurality of row lines, and a target column line from the plurality of column lines. A column line selection circuit, a normal fixed storage cell connected between a row line and a column line at respective intersections of the plurality of row lines and the plurality of column lines, A plurality of fixed test cells connected to any of the
In the read-only memory, some of the test fixed storage cells have a first area larger than the area of the normal fixed storage cells in an unwritten state, and Some of the storage cells have a second area having a cell area different from the first area in the unwritten state in an unwritten state, and have a cell area of the normal fixed storage cell. A programmable read-only memory, wherein at least a part of an unwritten test fixed storage cell larger than an area is configured to be writable under normal write conditions.