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JPH07105302B2 - Chip inductor manufacturing method - Google Patents
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JPH07105302B2 - Chip inductor manufacturing method - Google Patents

Chip inductor manufacturing method

Info

Publication number
JPH07105302B2
JPH07105302B2 JP2209287A JP20928790A JPH07105302B2 JP H07105302 B2 JPH07105302 B2 JP H07105302B2 JP 2209287 A JP2209287 A JP 2209287A JP 20928790 A JP20928790 A JP 20928790A JP H07105302 B2 JPH07105302 B2 JP H07105302B2
Authority
JP
Japan
Prior art keywords
substrate
ferrite
film
manufacturing
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2209287A
Other languages
Japanese (ja)
Other versions
JPH0493005A (en
Inventor
昭夫 佐々木
栄作 宮内
晃 小野寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2209287A priority Critical patent/JPH07105302B2/en
Publication of JPH0493005A publication Critical patent/JPH0493005A/en
Publication of JPH07105302B2 publication Critical patent/JPH07105302B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0201Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/028Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers

Landscapes

  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Coils Or Transformers For Communication (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、電子機器等に用いられる小型のチップインダ
クタの製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a small chip inductor used in an electronic device or the like.

に関する。Regarding

(発明の概要) 本発明は、小型化に好適なチップインダクタの製造方法
であって、外面を除いた基板面に誘導性導体膜パターン
を形成しかつ棒状部が一体に形成されるようにスリット
穴を設けた未焼成積層基板を焼成し、焼成後の積層基板
の前記棒状部の両端部に端部電極を形成した後に個々の
チップインダクタに切断分離することにより、工程の連
続化、生産性の改善を図ることができる。また、得られ
たチップインダクタは、内部に誘導性導体膜パターン形
成したフェライトチップの両端部に金属薄膜と金属めっ
き膜とからなる端部電極を設けた構造となり、小型化を
図り、また製品寸法精度の向上と材料費の低減を図るこ
とができる。
(Summary of the Invention) The present invention is a method for manufacturing a chip inductor suitable for miniaturization, in which an inductive conductor film pattern is formed on a substrate surface excluding an outer surface and a slit is formed so that a rod-shaped portion is integrally formed. By firing an unfired laminated substrate with holes, forming end electrodes at both ends of the rod-shaped portion of the laminated substrate after firing, and then cutting and separating into individual chip inductors, continuous process and productivity Can be improved. In addition, the obtained chip inductor has a structure in which end electrodes composed of a metal thin film and a metal plating film are provided at both ends of a ferrite chip on which an inductive conductor film pattern is formed. It is possible to improve accuracy and reduce material costs.

(従来の技術) 従来のチップインダクタの構造の一例を第1従来例とし
て第12図に示す。この場合、チップインダクとして誘導
性導体パターンのターン数が1回未満のマイクロチップ
ビーズの例を示している。この図において、50はフェラ
イトチップであり、2個のスルーホール51A,51Bを有し
ている。前記スルーホール51A,51Bは、一方の開口端面
で導体パターン52A,52Bを介し当該フェライトチップ両
端に設けられた端部電極53A,53Bにそれぞれ接続されて
おり、他方の開口端面では導体パターン52Cにより相互
に接続されている。
(Prior Art) An example of the structure of a conventional chip inductor is shown in FIG. 12 as a first conventional example. In this case, as the chip inductor, an example of microchip beads in which the number of turns of the inductive conductor pattern is less than 1 is shown. In this figure, reference numeral 50 denotes a ferrite chip, which has two through holes 51A and 51B. The through holes 51A, 51B are respectively connected to the end electrodes 53A, 53B provided at both ends of the ferrite chip through conductor patterns 52A, 52B at one opening end face, and by the conductor pattern 52C at the other opening end face. Connected to each other.

このマイクロチップビーズの製造は、予め貫通穴を設け
たチップ形状の未焼成フェライトチップを焼成後、前記
スルーホール51A,51B及び導体パターン52A,52B,52C、さ
らには端部電極53A,53AをAg−Pd材等の導体ペーストの
印刷、塗布及び焼き付けにより形成し、端部電極53A,53
に電気めっきを施した後、前記端部電極部分を除いた面
に絶縁コートを施すことにより実行される。
This microchip bead is manufactured by firing a chip-shaped unfired ferrite chip provided with through holes in advance, and the through holes 51A, 51B and conductor patterns 52A, 52B, 52C, and further the end electrodes 53A, 53A are Ag. -The end electrodes 53A, 53 are formed by printing, applying and baking a conductor paste such as Pd material.
After electroplating, the surface except the end electrode portion is coated with an insulating coat.

また、第13図は第2従来例であり、チップインダクとし
て誘導性導体パターンのターン数が1回以上のワイドバ
ンドチョークの例を示している。この図において、フェ
ライトチップ55には、6個のスルーホール56A乃至56Fが
設けられており、それらは両開口端面で導体パターン57
A乃至57Gによりそれぞれ相互にあるいは当該フェライト
チップ両端部の端部電極58A,58Bに接続されている。す
なわち、導体パターン57Aは端部電極58Aとスルーホール
56Aを接続しており、導体パターン57B,57C,57D,57E,57F
は図の如く各スルーホールを接続しており垂直面内でタ
ーンしているコイルを形成している。そして、スルーホ
ール56Fと端部電極58Bが導体パターン57Gを介して接続
され、以上の構成により垂直面でターンしているワイド
バンドチョークが構成される。
Further, FIG. 13 is a second conventional example and shows an example of a wide band choke in which the number of turns of the inductive conductor pattern is one or more as a chip inductor. In this figure, the ferrite chip 55 is provided with six through holes 56A to 56F, which are conductor patterns 57 on both end faces.
The electrodes A to 57G are connected to each other or to the end electrodes 58A and 58B at both ends of the ferrite chip. That is, the conductor pattern 57A includes the end electrode 58A and the through hole.
56A is connected and conductor pattern 57B, 57C, 57D, 57E, 57F
Forms a coil that connects each through hole as shown in the figure and turns in a vertical plane. Then, the through hole 56F and the end electrode 58B are connected via the conductor pattern 57G, and a wide band choke that turns in a vertical plane is configured by the above configuration.

以上の構成による第2従来例のワイドバンドチョーク
は、第1従来例と同様の製造方法で製造される。
The wide band choke according to the second conventional example having the above configuration is manufactured by the same manufacturing method as that of the first conventional example.

(発明が解決しようとする課題) ところで、前述の第12図及び第13図の従来のチップイン
ダクタのようにフェライトチップ単体の一方の面から他
方の面に貫通するように長めのスルーホールを設けて導
体パターンで接続する構成の場合、小型になるとスルー
ホール間の接続が容易でないとともに、スルーホールを
設けることでフェライトチップの厚みが必要となり、第
2従来例のワイドバンドチョークの構成のようにターン
数が多い場合さらに厚みが大きくなり、小型化が困難に
なる欠点があった。
(Problems to be Solved by the Invention) By the way, as in the conventional chip inductor shown in FIGS. 12 and 13, a long through hole is provided so as to penetrate from one surface of the ferrite chip single body to the other surface. In the case of a structure in which a conductor pattern is used for connection, the connection between the through holes is not easy when the size is small, and the provision of the through holes requires the thickness of the ferrite chip. Therefore, as in the wide band choke structure of the second conventional example. When the number of turns is large, the thickness is further increased, and there is a drawback that miniaturization becomes difficult.

製法上も、チップ形状に成型された未焼成のフェライト
チップに貫通穴を形成してから焼成し、焼成後の各チッ
プに印刷焼き付けによるスルーホール、導体パターン、
端部電極の形成を行なうので(バルク処理)、各工程に
おいて分離した個別のチップを加工することになり、端
部電極の形成などにおいて、加工が面倒になる嫌いがあ
るとともに各工程間の搬送に手間がかかる。さらに、バ
ルク処理であると、製品の外観選別の自動化が困難で工
程の連続化も難しい。
Also on the manufacturing method, through holes are formed in an unfired ferrite chip molded into a chip shape and then fired, and through holes and conductor patterns by printing and baking are applied to each fired chip.
Since the end electrodes are formed (bulk processing), separate chips are processed in each process, and there is a concern that the processing will be troublesome when forming the end electrodes and transfer between each process. Takes time. Further, in bulk processing, it is difficult to automate the appearance selection of products and it is difficult to make the process continuous.

また従来のごとき端部電極をAg−Pd材等の塗布焼き付け
による厚膜で構成する場合、その厚さの管理が面倒であ
り、外形寸法のばらつきが発生しやすい嫌いがあり、材
料費も高くなる欠点があった。
Moreover, when the end electrodes are made of a thick film by coating and baking Ag-Pd material etc. as in the past, it is difficult to control the thickness, and there is a tendency that the outer dimensions are likely to vary, and the material cost is high. There was a drawback.

なお、特公昭60−50331号は、印刷法でインダクタンス
素子を作成するインダクタンス素子の製造方法である
が、各金属パターンを相互に絶縁する絶縁層の透磁率及
び体積を大きくできないため、得られるインダクタンス
値に限度がある。
In addition, Japanese Patent Publication No. 60-50331 is a method of manufacturing an inductance element in which an inductance element is formed by a printing method, but since the magnetic permeability and volume of the insulating layer that insulates each metal pattern from each other cannot be increased, the obtained inductance There is a limit to the value.

本発明は、上記の点に鑑み、チップインダクタの小型化
及び製品寸法精度の向上が可能で、材料費の低減を図る
ことができ、製造工程の簡略化及び合理化や量産性の改
善が可能なチップインダクタの製造方法を提供すること
を目的とする。
In view of the above points, the present invention can reduce the size of the chip inductor and improve the product dimensional accuracy, can reduce the material cost, and can simplify and rationalize the manufacturing process and improve mass productivity. An object is to provide a method for manufacturing a chip inductor.

(課題を解決するための手段) 上記目的を達成するために、本発明のチップインダクタ
の製造方法は、複数枚の未焼成フェライト・シート基板
を積層しかつ外面となる面を除く前記未焼成フェライト
・シート基板のいずれかの基板面に誘導性導体膜パター
ンを設けるとともに棒状部が一体に形成されるようにス
リット穴を形成してなる未焼成積層基板を焼成し、焼成
後の積層基板の前記棒状部の端部を略コ字状に囲むよう
に薄膜技術による金属薄膜を形成し、該金属薄膜上に金
属めっき膜を設けて端部電極を形成した後、前記棒状部
を複数個に切断分離するものである。
(Means for Solving the Problems) In order to achieve the above-mentioned object, a method for manufacturing a chip inductor of the present invention is such that the unfired ferrite is formed by laminating a plurality of unfired ferrite sheet substrates and excluding a surface to be an outer surface. -The unbaked laminated substrate formed by forming an inductive conductor film pattern on any one of the substrate surfaces of the sheet substrate and forming slit holes so that the rod-shaped portions are integrally formed is fired, and the laminated substrate after firing is baked. After forming a metal thin film by a thin film technique so as to surround the end of the rod-shaped portion in a substantially U-shape, forming a metal plating film on the metal thin film to form an end electrode, and cutting the rod-shaped portion into a plurality of pieces. To separate.

(作用) 本発明に係る製造方法においては、外面となる基板面を
除き導体膜パターンを設けた複数枚の未焼成フェライト
・シート基板を積層したものに棒状部が一体に形成され
るようにスリット穴を施し、それを焼成一体化した積層
基板を使用し、各工程においては複数個のフェライトチ
ップがつながった1枚の基板として処理することにより
(基板処理工法)、端部電極成膜工程や外観選別工程等
において、多数個のチップインダクタ同時処理がパレッ
ト等を使用することなく可能になり、工程のライン化
(工程間搬送の統一化)や量産が容易になり、製造原価
の低減及び製造所要時間の短縮を図ることができる。
(Operation) In the manufacturing method according to the present invention, a slit is formed so that the rod-shaped portion is integrally formed in a laminate of a plurality of unfired ferrite sheet substrates provided with a conductor film pattern except the substrate surface which is the outer surface. By using a laminated substrate in which holes are formed and fired and integrated, and processing is performed as one substrate in which a plurality of ferrite chips are connected in each process (substrate processing method) In the appearance selection process, etc., multiple chip inductors can be processed simultaneously without using a pallet, etc., making process lines (unification of transfer between processes) and mass production easy, reducing manufacturing costs and manufacturing. The required time can be shortened.

さらに、端部電極材にAg−Pb等の導体ペーストを使用せ
ず、焼成後の積層基板の棒状部に、スパッタ、イオンプ
レーティング、P−CVD等の薄膜技術によって端部電極
の下層となる金属薄膜を被着形成し、さらに金属めっき
膜を設けるので、端部電極の厚みの管理を高精度で行う
ことが容易で、端部電極成膜工程の簡略化と同時成膜に
よる量産化が可能になり、材料費と製造工程の削減とと
もに、製品寸法精度と搭載率の向上を図ることができ、
さらに小型化や薄形化にも十分対応できる。
Further, without using a conductor paste such as Ag-Pb for the end electrode material, the lower electrode of the end electrode is formed on the rod portion of the laminated substrate after firing by a thin film technique such as sputtering, ion plating, or P-CVD. Since the metal thin film is deposited and the metal plating film is further provided, the thickness of the end electrodes can be easily controlled with high accuracy, and the end electrode film forming process can be simplified and mass production by simultaneous film formation can be performed. It is possible to reduce the material cost and manufacturing process, and improve the product dimensional accuracy and mounting rate.
Furthermore, it can be made smaller and thinner.

(実施例) 以下、本発明に係るチップインダクタ及びその製造方法
の実施例を図面に従って説明する。
(Example) Hereinafter, an example of a chip inductor and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

第1図はチップインダクタとしてのマイクロチップビー
ズの製造工程を説明する工程図である。まず、第2図に
示した未焼成のフェライト・シート基板1を受け入れ、
導体膜パターン印刷工程2において、フェライト・シー
ト基板1の一方の基板面に第3図の如く導体ペーストの
印刷により所定の誘導性導体膜パターン11を複数個並列
に設ける。この導体膜パターン11は図の如く基板平面内
で半ターンし、両端は後に端部電極と接続するように突
出した形状に形成されている。つまり、この場合ターン
数が1回未満なのでマイクロチップビーズを構成する。
FIG. 1 is a process diagram for explaining a manufacturing process of microchip beads as a chip inductor. First, accept the unfired ferrite sheet substrate 1 shown in FIG.
In the conductor film pattern printing step 2, a plurality of predetermined inductive conductor film patterns 11 are provided in parallel on one substrate surface of the ferrite sheet substrate 1 by printing a conductor paste as shown in FIG. The conductor film pattern 11 is half-turned in the plane of the substrate as shown in the drawing, and both ends thereof are formed in a projecting shape so as to be connected to the end electrodes later. That is, in this case, since the number of turns is less than one, a microchip bead is formed.

次に積層工程3において、第4図の如く、前記導体膜パ
ターン11を施したフェライト・シート基板1Aを挟む如く
導体膜の無いフェライト・シート基板1B,1Cを積層す
る。そして次のスタック(プレス)工程4において一様
に加圧処理することにより3層構造の未焼成積層基板が
作製される。
Next, in a laminating step 3, as shown in FIG. 4, ferrite sheet substrates 1B and 1C having no conductor film are laminated so as to sandwich the ferrite sheet substrate 1A provided with the conductor film pattern 11. Then, in the next stacking (pressing) step 4, a uniform pressure treatment is carried out to produce an unfired laminated substrate having a three-layer structure.

その後、スリット形成工程5において前記未焼成積層基
板に第5図に示す如く複数のスリット穴12を所定間隔で
平行にパンチングもしくはレーザー加工であけ、平行な
スリット穴間に多数の棒状部13を形成することにより、
未焼成の穴あき積層基板14が作製される。なお、各未焼
成フェライト・シート基板上のスリット穴12の位置は第
2図乃至第4図においても仮想線で示した。
After that, in the slit forming step 5, a plurality of slit holes 12 are punched or laser-processed in parallel at predetermined intervals in the unfired laminated substrate as shown in FIG. 5, and a large number of rod-shaped portions 13 are formed between the parallel slit holes. By doing
An unfired perforated laminated substrate 14 is produced. The positions of the slit holes 12 on each unfired ferrite sheet substrate are shown by imaginary lines in FIGS. 2 to 4.

それから、焼成工程6において前記穴あき積層基板14を
焼結することにより、積層及びスリット穴加工された各
シート基板1A,1B,1Cは一体となり、内部に誘導性導体膜
パターン11を有する複数個の棒状部13が形成された穴あ
きフェライト基板15が得られる。その際、後工程で各チ
ップに分離する際の切断代となるV乃至U字状溝を前記
スタック工程4もしくはスリット形成工程5において予
め形成しておいて焼成するようにしてもよい。なお、誘
導性導体膜パターン11の両端はスリット穴12を設けるこ
とにより棒状部13の端面に露出している。
Then, by sintering the perforated laminated substrate 14 in the firing step 6, the laminated and slit-hole-processed sheet substrates 1A, 1B, 1C are integrated, and a plurality of inductive conductor film patterns 11 are provided inside. A perforated ferrite substrate 15 having the rod-shaped portion 13 is obtained. At this time, V to U-shaped grooves, which serve as a cutting allowance when the chips are separated in a later step, may be formed in advance in the stacking step 4 or the slit forming step 5 and baked. It should be noted that both ends of the inductive conductor film pattern 11 are exposed at the end faces of the rod-shaped portion 13 by providing slit holes 12.

それから、端部電極成膜工程7において、第6図の如
く、端部電極の下層部分を構成する金属薄膜16A,16Bの
成膜をスパッタにより前記穴あきフェライト基板15の状
態で行ない、すなわち各棒状部13の両端部を略コ字状に
囲む如く金属薄膜16A,16Bを形成する。ここで金属薄膜1
6A,16Bはそれぞれ第3図に図示した前記誘導性導体膜パ
ターン11のスリット穴12に面する両端部に電気的に接続
するもので、それぞれ2層構造であり、例えば下層がフ
ェライトに付着性の良いNiCr,TiまたはCrのスパッタ
膜、上層が低抵抗のCuスパッタ膜である。なお、薄膜形
成時、穴あきフェライト基板15両面及び棒状部13側面の
不要部部分を予めマスキング処理しておく。
Then, in the end electrode film forming step 7, as shown in FIG. 6, the metal thin films 16A and 16B forming the lower layer part of the end electrode are formed by sputtering in the state of the perforated ferrite substrate 15, that is, Metal thin films 16A and 16B are formed so as to surround both ends of the rod-shaped portion 13 in a substantially U-shape. Metal thin film here 1
6A and 16B are electrically connected to both ends facing the slit hole 12 of the inductive conductor film pattern 11 shown in FIG. 3, and each has a two-layer structure. For example, the lower layer is adhesive to ferrite. A good sputtered film of NiCr, Ti or Cr, and a Cu sputtered film with a low resistance in the upper layer. At the time of forming the thin film, masking processing is performed in advance on both surfaces of the perforated ferrite substrate 15 and unnecessary portions on the side surfaces of the rod-shaped portion 13.

さらに、端部電極めっき工程8において、穴あきフェラ
イト基板15のままで各棒状部13の金属薄膜16A,16B上に
めっきを施し、第7図に示すように、金属めっき膜17A,
17Bを金属薄膜16A,16B上に被着形成して端部電極18A,18
Bを構成する。ここで、金属めっき膜17A,17Bは2層構造
であり、金属薄膜16A,16B上に直接被着形成される下層
が耐はんだ性(はんだの拡散防止及びはんだ耐熱性)の
Niめっき膜、上層がはんだ付着性の良いPb−SnまたはSn
めっき膜である。なお、めっきは電解(湿式)めっきで
あっても無電解めっきであっても良い。
Further, in the end electrode plating step 8, the metal thin films 16A and 16B of each rod 13 are plated with the perforated ferrite substrate 15 as it is, and as shown in FIG.
17B is deposited on the metal thin films 16A, 16B to form end electrodes 18A, 18B.
Make up B. Here, the metal plating films 17A and 17B have a two-layer structure, and the lower layer directly deposited on the metal thin films 16A and 16B has solder resistance (prevention of solder diffusion and solder heat resistance).
Ni plating film, Pb-Sn or Sn whose upper layer has good solder adhesion
It is a plated film. The plating may be electrolytic (wet) plating or electroless plating.

その後、穴あきフェライト基板15を粘着シートの上に載
置し、切断工程9において、1個の誘導性導体膜パター
ン11を有するように第7図に一点鎖線Xで示した切断代
(第3図及び第6図にも同様に図示した)に沿って前記
棒状部13をダイシングソー等により切断、分離し、第8
図及び第9図の如く内部に1個の誘導性導体膜パターン
11を持ち、かつこれに接続する端部電極18A,18Bを有す
る1個のマイクロチップビーズが得られる。ただし、裏
面の粘着シートにより切断後も相互の平面的な位置関係
は変わらないようにしておき、この状態において次の外
観選別工程10において、画像処理を利用して外観選別を
自動的に行なう。画像処理により外観不良と判断された
ものは選別除去される。外観が良品と判定されたものが
製品となる。
After that, the perforated ferrite substrate 15 is placed on the adhesive sheet, and in the cutting step 9, the cutting allowance (third part) indicated by the one-dot chain line X in FIG. 7 so as to have one inductive conductor film pattern 11 (third part). (Also shown in FIGS. 6 and 6), the rod-shaped portion 13 is cut and separated by a dicing saw or the like along
As shown in Fig. 9 and Fig. 9, one inductive conductor film pattern is provided inside.
One microchip bead having 11 and having end electrodes 18A, 18B connected to it is obtained. However, the two-dimensional pressure-sensitive adhesive sheet does not change the mutual planar positional relationship even after cutting, and in this state, in the next appearance selection step 10, image selection is automatically performed using image processing. Those that are judged to have a poor appearance by image processing are selectively removed. Products that are judged to be good in appearance are products.

第8図及び第9図は上記製法によって得られた完成品の
マイクロチップビーズ20を示すものであり、第8図の分
解斜視図からわかるように、半ターンの誘導性導体膜パ
ターン11を有するチップ状のフェライト板21Aの両面に
導体膜の無いチップ状フェライト板21Bと21Cを積層し焼
成一体化してなるフェライトチップ22の両端部に前記誘
導性導体膜パターンに接続する端部電極18A,18Bを有し
ている構造となっている。ただし、第9図の斜視図から
明らかなように、端部電極18A,18Bはフェライトチップ2
2の両端部を略コ字状に囲むものであり、フェライトチ
ップ22の側面を覆わない形状となっている。このことは
端部電極18A,18Bとして薄膜技術による金属薄膜及び金
属めっき膜の組み合わせを採用したことによる製品寸法
のばらつき縮小と共に大きな利点となる。
8 and 9 show a finished microchip bead 20 obtained by the above-mentioned manufacturing method, and as shown in the exploded perspective view of FIG. 8, have a half-turn inductive conductor film pattern 11. End electrodes 18A, 18B connected to the inductive conductor film pattern on both ends of a ferrite chip 22 formed by laminating chip ferrite plates 21B and 21C having no conductor film on both sides of a chip ferrite plate 21A and firing and integrating them. It has a structure that has. However, as apparent from the perspective view of FIG. 9, the end electrodes 18A and 18B are the ferrite chips 2
Both ends of 2 are enclosed in a substantially U-shape, and the side surface of the ferrite chip 22 is not covered. This is a great advantage as well as reduction of variations in product dimensions due to the use of a combination of a metal thin film and a metal plating film by the thin film technology as the end electrodes 18A and 18B.

第10図及び第11図は本発明の他の実施例を示しており、
前述の実施例では誘導性導体膜パターンを未焼成フェラ
イト・シート基板の1つの基板面に設けていたが、この
場合は複数の未焼成フェライト・シート基板のそれぞれ
一方の基板面に誘導性導体膜パターンを形成し(但し積
層基板の外面となる基板面は除く)、誘導体膜パターン
を相互にスルーホールで接続するように積層しており、
チップインダクタにおいてターン数を1回以上としたワ
イドバンドチョークを構成したものである。
10 and 11 show another embodiment of the present invention,
In the above-described embodiment, the inductive conductor film pattern is provided on one substrate surface of the unfired ferrite sheet substrate, but in this case, the inductive conductor film is formed on each substrate surface of the plurality of unfired ferrite sheet substrates. A pattern is formed (excluding the substrate surface that is the outer surface of the laminated substrate), and the dielectric film patterns are laminated so that they are connected to each other through holes.
In the chip inductor, a wide band choke having one or more turns is constructed.

このワイドバンドチョークの実施例の製造工程はやは
り、第1図の工程図と同様であるが、導体膜パターン印
刷工程2において、第10図の如く例えば3枚のフェライ
ト・シート基板31A,31B,31Cの基板面の一方にそれぞれ
所定の誘導性導体膜パターン32A,32B,32Cを形成する。
また、それらのフェライト・シート基板31A,31B,31Cに
は、1回以上ターンするコイルを成すように各導体膜パ
ターンを相互に接続する位置にスルーホール33を施して
おく(第11図にも同符号で示してある。)。
The manufacturing process of the embodiment of this wide band choke is the same as that of the process chart of FIG. 1, but in the conductor film pattern printing step 2, as shown in FIG. 10, for example, three ferrite sheet substrates 31A, 31B, Predetermined inductive conductor film patterns 32A, 32B, 32C are formed on one of the substrate surfaces of 31C.
Further, through holes 33 are formed in the ferrite sheet substrates 31A, 31B, 31C at positions where the conductor film patterns are connected to each other so as to form a coil that turns one or more times (see also FIG. 11). It is indicated by the same symbol.).

次の積層工程3及びスタック工程4において、上記の誘
導性導体膜パターンを有する3枚のフェライト・シート
基板31A,31B,31Cの両面に導体膜の無いフェライト・シ
ート基板31D,31Eを積層することで5層の未焼成積層基
板が作製される。この際、各導体膜パターンがスルーホ
ール33を介して相互に接続されターン数が1回以上のコ
イルを構成する。その後、スリット形成工程5でスリッ
ト穴12を形成してから焼成して穴あきフェライト基板を
作成する。
In the following laminating step 3 and stacking step 4, laminating ferrite sheet substrates 31D, 31E having no conductor film on both surfaces of the three ferrite sheet substrates 31A, 31B, 31C having the above-mentioned inductive conductor film pattern. Thus, a 5-layer unbaked laminated substrate is produced. At this time, the respective conductor film patterns are connected to each other through the through holes 33 to form a coil having one or more turns. Then, in the slit forming step 5, slit holes 12 are formed and then fired to form a perforated ferrite substrate.

それから、前記実施例と同様に各工程を経て製品とな
る。第11図はこの製法によって得られたワイドバンドチ
ョーク30の完成品の分解斜視図を示しており、同図から
わかるようにターン数が1回以上のコイルを構成してい
る誘導性導体膜パターン32A,32B,32Cとスルーホール33
を有する3層のチップ状のフェライト板34A,34B,34C
と、導体膜の無いフェライト板34Dと34Eを積層し焼成一
体化してなるフェライトチップの両端部に前記誘導性導
体膜パターン32A,32Cに接続する端部電極35A,35Bを有す
る構造となっている。
Then, a product is obtained through each step as in the above embodiment. FIG. 11 shows an exploded perspective view of the finished product of the wide band choke 30 obtained by this manufacturing method. As can be seen from the figure, the inductive conductor film pattern forming a coil having one or more turns. 32A, 32B, 32C and through hole 33
3-layer chip-shaped ferrite plates 34A, 34B, 34C having
And, it has a structure having end electrodes 35A, 35B connected to the inductive conductor film patterns 32A, 32C at both ends of a ferrite chip formed by laminating and firing and integrating ferrite plates 34D and 34E without conductor films. .

上記第10図及び第11図で説明した実施例の場合、誘導性
導体膜パターンを3層積層し、コイルのターン数が1回
半の場合を示したが、任意のターン数を得るため様々な
形状のパターンを形成したり、積層数を増減してもよ
い。
In the case of the embodiment described with reference to FIGS. 10 and 11 above, the case where three layers of inductive conductor film patterns are laminated and the number of turns of the coil is one and a half is shown. A pattern having a different shape may be formed, or the number of stacked layers may be increased or decreased.

さらに、上記実施例において誘導性導体膜と端部電極と
の接続をスルーホールで行うようにしても良い。
Further, in the above embodiment, the connection between the inductive conductor film and the end electrode may be made by a through hole.

また、端部電極成膜工程7において、金属薄膜を2層の
スパッタ膜で形成したが、最下層をNiCrのスパッタ膜、
中間層をCuNiのスパッタ膜、上層をCuのスパッタ膜とし
た3層構造としてもよい。また、Cuのスパッタ膜1層の
みの構造としてもよい。
Further, in the end electrode film forming step 7, the metal thin film was formed of two layers of sputtered film, but the bottom layer was formed of NiCr sputtered film,
A three-layer structure in which the intermediate layer is a CuNi sputtered film and the upper layer is a Cu sputtered film may be used. Further, the structure may be made of only one Cu sputtered film.

また、スパッタの代わりにイオンプレーティング、P−
CVD等で金属薄膜を形成しても良い。
Also, instead of sputtering, ion plating, P-
The metal thin film may be formed by CVD or the like.

(発明の効果) 以上説明したように、本発明に係るチップインダクタの
製造方法によれば、複数枚の未焼成フェライト基板を積
層したものに棒状部が一体に形成されるようにスリット
穴を施し、それを焼成一体化した積層基板を使用するこ
とにより(基板処理工法)、製造時においては複数個の
チップを1枚の基板として処理が可能であり、多数個の
チップインダクタの同時処理がパレット等を使用するこ
となく可能である。従って、工程のライン化(工程間搬
送の統一化)や量産が容易になり、画像処理による外観
選別の自動化も可能で、製造原価の低減及び製造所要時
間の短縮を図ることができる。
(Effects of the Invention) As described above, according to the method for manufacturing a chip inductor according to the present invention, a slit hole is formed in a laminate of a plurality of unfired ferrite substrates so that the rod-shaped portion is integrally formed. By using a laminated substrate that is integrated by firing (substrate processing method), it is possible to process multiple chips as one substrate at the time of manufacturing, and it is possible to process multiple chip inductors simultaneously. It is possible without using Therefore, the process can be made into a line (unification of conveyance between processes) and mass production can be facilitated, the appearance selection can be automated by image processing, and the manufacturing cost and the manufacturing required time can be shortened.

さらに、前記積層基板の積層棒状部に、薄膜技術による
端部電極膜を施し、その積層基板を切断しチップ化して
いるので、材料費と製造工程の削減とともに、製品寸法
のばらつきを小さくでき、さらに小型化や薄形化にも十
分対応できる。
Further, the laminated rod-shaped portion of the laminated substrate is provided with an end electrode film by a thin film technique, and the laminated substrate is cut into chips, so that it is possible to reduce the material cost and the manufacturing process and reduce the variation in product dimensions. Furthermore, it can be made smaller and thinner.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例の製造工程を示す工程図、第2
図は未焼成フェライト・シート基板を示す斜視図、第3
図は導体膜パターン印刷工程を示す部分斜視図、第4図
は積層工程を示す部分分解斜視図、第5図はスリット形
成工程を示す斜視図、第6図は端部電極成膜工程を示す
部分斜視図、第7図は端部電極めっき工程を示す部分斜
視図、第8図は切断後のチップインダクタとしてのマイ
クロチップビーズの構成を示す分解斜視図、第9図はマ
イクロチップビーズの完成品を示す斜視図、第10図は本
発明の他の実施例における積層工程を示す部分分解斜視
図、第11図は切断後のワイドバンドチョークの構成を示
す同分解斜視図、第12図は従来のチップインダクタの構
成の1例を示す斜視図、第13図は他の従来例の構成を示
す斜視図である。 1……未焼成フェライト・シート基板、2……導体膜パ
ターン印刷工程、3……積層工程、4……スタック工
程、5……スリット形成工程、6……焼成工程、7……
端部電極成膜工程、8……端部電極めっき工程、9……
切断工程、10……外観選別工程、11,32A,32B,32C……誘
導性導体膜パターン、12……スリット穴、13……棒状
部、14……穴あき積層基板、15……穴あきフェライト基
板、16A,16B……金属薄膜、17A,17B……金属めっき膜、
18A,18B,35A,35B……端部電極、22……フェライトチッ
プ、33……スルーホール。
FIG. 1 is a process diagram showing a manufacturing process of an embodiment of the present invention, and FIG.
The figure shows a perspective view of an unfired ferrite sheet substrate, the third
FIG. 4 is a partial perspective view showing a conductive film pattern printing process, FIG. 4 is a partially exploded perspective view showing a laminating process, FIG. 5 is a perspective view showing a slit forming process, and FIG. 6 is an end electrode film forming process. Partial perspective view, FIG. 7 is a partial perspective view showing the end electrode plating step, FIG. 8 is an exploded perspective view showing the structure of the microchip beads as the chip inductor after cutting, and FIG. 9 is the completion of the microchip beads. FIG. 10 is a perspective view showing the product, FIG. 10 is a partially exploded perspective view showing a laminating step in another embodiment of the present invention, FIG. 11 is an exploded perspective view showing the structure of the wide band choke after cutting, and FIG. FIG. 13 is a perspective view showing an example of the configuration of a conventional chip inductor, and FIG. 13 is a perspective view showing the configuration of another conventional example. 1 ... Unfired ferrite sheet substrate, 2 ... Conductor film pattern printing process, 3 ... Laminating process, 4 ... Stacking process, 5 ... Slit forming process, 6 ... Firing process, 7 ...
Edge electrode deposition process, 8 ... Edge electrode plating process, 9 ...
Cutting process, 10 ... Appearance selection process, 11,32A, 32B, 32C ... Inductive conductor film pattern, 12 ... Slit hole, 13 ... Rod portion, 14 ... Perforated laminated substrate, 15 ... Perforated Ferrite substrate, 16A, 16B …… Metal thin film, 17A, 17B …… Metal plating film,
18A, 18B, 35A, 35B …… End electrode, 22 …… Ferrite chip, 33 …… Through hole.

フロントページの続き (56)参考文献 特開 昭59−103321(JP,A) 特開 昭55−145333(JP,A) 実開 平1−179412(JP,U) 実開 昭58−116204(JP,U)Continuation of the front page (56) Reference JP-A-59-103321 (JP, A) JP-A-55-145333 (JP, A) Actually open 1-17912 (JP, U) Actually open 58-116204 (JP , U)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】複数枚の未焼成フェライト・シート基板を
積層しかつ外面となる面を除く前記未焼成フェライト・
シート基板のいずれかの基板面に誘導性導体膜パターン
を設けるとともに棒状部が一体に形成されるようにスリ
ット穴を形成してなる未焼成積層基板を焼成し、焼成後
の積層基板の前記棒上部の端部を略コ字状に囲むように
薄膜技術による金属薄膜を形成し、該金属薄膜上に金属
めっき膜を設けて端部電極を形成した後、前記棒状部を
複数個に切断分離することを特徴とするチップインダク
タの製造方法。
1. An unsintered ferrite sheet, which is obtained by laminating a plurality of unsintered ferrite sheet substrates and excluding an outer surface.
The unfired laminated substrate formed by forming an inductive conductor film pattern on one of the substrate surfaces of the sheet substrate and forming slit holes so that the rod-shaped portions are integrally formed is fired, and the rod of the laminated substrate after firing is fired. After forming a metal thin film by thin film technology so as to surround the upper end in a substantially U-shape, forming a metal plating film on the metal thin film to form an end electrode, cutting the rod-shaped portion into a plurality of pieces A method of manufacturing a chip inductor, comprising:
【請求項2】前記誘導性導体膜パターンが複数の基板面
に形成され、相互にスルーホールで接続されている請求
項1記載のチップインダクタの製造方法。
2. The method for manufacturing a chip inductor according to claim 1, wherein the inductive conductor film patterns are formed on a plurality of substrate surfaces and are connected to each other by through holes.
JP2209287A 1990-08-09 1990-08-09 Chip inductor manufacturing method Expired - Fee Related JPH07105302B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2209287A JPH07105302B2 (en) 1990-08-09 1990-08-09 Chip inductor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2209287A JPH07105302B2 (en) 1990-08-09 1990-08-09 Chip inductor manufacturing method

Publications (2)

Publication Number Publication Date
JPH0493005A JPH0493005A (en) 1992-03-25
JPH07105302B2 true JPH07105302B2 (en) 1995-11-13

Family

ID=16570449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2209287A Expired - Fee Related JPH07105302B2 (en) 1990-08-09 1990-08-09 Chip inductor manufacturing method

Country Status (1)

Country Link
JP (1) JPH07105302B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005287A (en) * 1995-11-24 1999-12-21 Nec Corporation Semiconductor device, and lead frame used therefor
JP3097569B2 (en) 1996-09-17 2000-10-10 株式会社村田製作所 Manufacturing method of multilayer chip inductor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59103321A (en) * 1982-12-03 1984-06-14 Murata Mfg Co Ltd Manufacture of coil
JPH01179412U (en) * 1988-06-07 1989-12-22

Also Published As

Publication number Publication date
JPH0493005A (en) 1992-03-25

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