JPH07105503B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device of high speed and low power consumption, and particularly to an arbitrary portion of a sidewall surface of a U-shaped groove cut from a semiconductor substrate. The present invention relates to a processing technique related to a process of forming a diffusion region having a size of 1 to form a contact hole.

[Technical background]

The recent development of semiconductor devices is remarkable,
With the goal of speed, low power consumption, efficiency, and integration density,
One after another, new concept, structure of transistor, thyristor,
ICs, memories, etc. have been proposed. Since the dimension control in the thickness direction is easier than in the planar direction and the three-dimensional structure cannot be avoided in order to meet the demand for super-density such as 64 Mbit dynamic RAM, it is perpendicular to the substrate surface. Various semiconductor devices have been proposed that require a processing technique for the directional surface. Especially electrostatic induction transistor (hereinafter referred to as SIT)
Static induction type semiconductor devices such as
It is known that by forming a gate in a vertically cut side wall part, its basically excellent characteristics become more suitable for a frequency operation. FIG. 1 is an example of a sectional view of a notched gate type SIT. The n ⁺ region 1 is the drain, the n ⁻ region 2 is the channel, the p ⁺ region 3 is the gate, the n ⁺ region 4 is the source, and on the insulator 5. Since the gate electrode 6 is formed in the structure, the capacitance between the source and gate, the capacitance between the gate and drain can be reduced, and the conversion conductance g _m can be increased. It is suitable for efficient operation.

However, in a semiconductor device having a notch from the semiconductor surface, it is almost impossible to form a diffusion window, a contact hole, or the like on the side wall surface of the notch by the photolithographic technique which is the basis of the conventional flattening technique. It was

[Problems to be Solved by Prior Art and Invention]

As a technique for forming a diffusion window and a contact window on the side wall surface of the cut portion of a semiconductor device having the above-mentioned cut portion (U groove), Japanese Patent Publication No. 62-32632 "Method for manufacturing semiconductor device" and Japanese Patent Publication No. Techniques disclosed in No. 031309 “Semiconductor Device Manufacturing Method” and the like have been proposed. 2 (a) to 2 (j) show the manufacturing process of the N-channel SIT disclosed in the above Japanese Patent Publication No. 62-32632.

(1) As shown in Fig. 2 (a), n ⁺ Si becomes the drain
On the substrate (impurity density 10 ¹⁸ / cm ³ ) 1, an n ⁻ layer (impurity density 10 ¹³ to 10 ¹⁴ / cm ³ ) 2 operating layer is grown to a thickness of about 10 μ by epitaxial growth, and then oxidized by thermal oxidation or the like. Membrane 5
About 1 μm is formed. Then by photolithographic technology OMR8
A resist film 8 such as 3 is selectively formed in a portion other than the cut region.

(2) As shown in FIG. 2B, the oxide film 5 is removed using the resist 8 as a mask to cut the n ⁻ layer 2 to a depth of about 3 μ. In this case, it is desirable that the side surface of the cut portion be substantially perpendicular to the surface of the n ⁻ layer 2 and that the bottom surface be close to a flat surface. Examples include plasma etching and sputter etching that flatten the bottom surface. For example, to perform plasma etching, the crystal plane of the n ⁺ substrate 1 should be (11
1) Select the surface and align the direction of the mask with the <110> direction. First, plasma etch the oxide film 5 with a C ₃ F ₈ gas of 0.1 Torr and then change the gas to a PCl ₃ gas of 0.05 to 0.1 Torr and n ^−. If the layer 2 is plasma-etched, it can be cut into a shape having a side surface (wall surface) perpendicular to the surface of the n ⁻ layer 2 and a flat bottom surface. Then, the resist 8 is removed by O ₂ gas plasma.

(3) As shown in FIG. 2 (c), an oxide film 5 is formed in a portion cut by thermal oxidation or the like to a thickness of about 5000Å. At this time, the oxide film 5 on the surface of the n ⁻ layer 2 formed in (1) is 1.1 μm.
Increase to a degree.

(4) As shown in FIG. 2D, the oxide film 5 on the bottom surface cut by directional plasma etching, sputter etching or the like is etched. In this case, the oxide film 5 on the side surface (wall surface) remains due to the directivity, and the oxide film 5 on the surface of the n ⁻ layer 2 is reduced to about 6000Å. Then, cut the bottom n ^- layer 2 by about 1.5
Plasma etch about μ. For example, for plasma etching, the oxide film 5 is etched with C ₃ F ₈ 0.1 Torr and the n ⁻ layer 2 is P.
It can be formed by etching with Cl ₃ 0.05 to 0.1 Torr.

(5) As shown in FIG. 2 (e), a Si ₃ N ₄ film 9 is formed to a thickness of about 1000 Å by CVD or the like.

(6) As shown in FIG. 2 (f), the bottom surface cut by directional plasma etching, sputter etching, or the like.
The Si ₃ N ₄ film 9 and the Si ₃ N ₄ film 9 on the surface of the n ⁻ layer 2 are etched. Si
_{The 3} N ₄ film 9 remains only on the cut side surface (wall surface). For example, C ₃ F ₈ 0.02 ~
It can be formed by etching at 0.05 Torr.

(7) As shown in FIG. 2 (g), an oxide film 5'is formed on the cut bottom surface by thermal oxidation or the like to have a thickness of about 5000Å. When this, Si ₃ N ₄ in the film 9 is cut the sides (walls) oxide film 5 'is not formed. The oxide film 5 on the surface of the n ⁻ layer 2 increases to about 8000Å.

(8) As shown in FIG. 2 (h), the oxide film 5 is formed on the surface of the n ⁻ layer 2 by the photolithographic technique in the upper region of the source.
Of the n ⁺ region 10 (impurity density of ~ 10 ²¹
/ cm ³ ) to a depth of about 0.5μ. In this case, Si ₃ N ₄ uses As having no masking property as an impurity source.

(9) As shown in FIG. 2 (i), if the Si ₃ N ₄ film 9 on the side surface (wall surface) cut by non-directional plasma etching, hot phosphoric acid etching or the like is etched, the oxide film 5 is opened. Division 1.0
The gate of the p ⁺ region 11 is formed at a depth of 0.5 μ from the side surface (wall surface) in this opening by diffusion or the like. The impurity density of this gate is lower than the impurity density of the n ⁺ region 10 and is about 10 ²⁰ to 10 ¹⁹ . Therefore, the n ⁺ region 10 does not need to be masked, and the formation of the p ⁺ region 11 has little influence.

(10) As shown in FIG. 2 (j), the normal vapor deposition in which a metal film of Al or the like is formed to a thickness of about 1.5 μm by vapor deposition and the like and is formed on the gate electrode 12 and the source electrode 13 by the photolithographic technique has directivity. Because it exists, it is vapor-deposited only on the surface of the n ^- layer 2 and the bottom surface that is cut, and only the scattered portion adheres to the side surface (wall surface), so it is easy to use a method such as full surface etching without the need for photolithographic technology. Alternatively, the gate electrode 12 and the source electrode 13 can be separated. A metal film 14 is also vapor-deposited on the lower surface to serve as a drain electrode.

However, according to the method shown in FIG. 2, the width of the opening portion as the gate diffusion window in the direction perpendicular to the substrate surface is 1.0 μm.
In the case of a relatively large size of about m or more, it is easy to form the p ⁺ region 11 on the side wall surface by diffusion or the like as shown in FIG. 2 (i), but the width of the opening portion as the gate diffusion window is large. Is 1.0μ
When the size is smaller than m, there is a problem that the p ⁺ region 11 is not sufficiently formed or only partially formed. As a result, the effect of the gate is poor and the exchange conductance g _m is lowered. In addition, there is a drawback that it does not operate unless a voltage is applied to the gate. Figure 3 shows the drain current-drain voltage characteristics of SIT when the gate diffusion window width on the side wall is 0.7 μm.
It was found that the gate does not work without applying the voltage above and does not work effectively as a SIT. Therefore, according to the manufacturing method shown in FIG. 2, the power-saving operating at a power supply voltage 1.5V (low power consumption), and the efficiency of joining SIT, cutoff frequency 10GH _Z
Required for the above-mentioned junction SIT for frequencies. 1.0 μm
There is a drawback that it is extremely difficult to open a diffusion window having the following fine dimensions and a contact hole.

In order to form the p ⁺ diffusion region more reliably, the process shown in FIG. 4 can be considered. 2 (a) to 2 (c) are the same. Next, as shown in FIG. 4 (a), the oxide film 5 only on the bottom surface of the cut portion is removed by directional etching to obtain a relatively large opening area. A diffusion window is opened, and ap ⁺ diffusion region 11 'is formed on the bottom surface and a part of the side wall surface adjacent to the bottom surface. Next, as shown in FIG. 4 (b), a second incision is made deeper so that only the p ⁺ diffusion region 11 ″ on the side wall surface is left and the diffusion region on the bottom surface is removed. Oxide 51 is removed by directional vacuum deposition method of oxide (SiO ₂ ).
It is formed on the bottom surface of the cut portion for the first time. Next, as shown in FIG. 4C, the gate electrode 12 is formed by the vacuum evaporation method.
However, in the method shown in FIG. 4, the oxide 51 formed by vacuum deposition actually forms an overhang portion on the upper surface of the protrusion not cut as shown in FIG. 4B.
Since the part behind the overhang part is not vapor-deposited, it is deposited with a trapezoidal cross-sectional shape on the bottom of the notch,
Therefore, the gate electrode 12 comes into direct contact with the n ⁻ layer 2 below the p ⁺ diffusion region 11 ″ as shown in FIG. 4 (c), which causes a leak current of the gate and causes a leak current between the gate and the source. There was a drawback that it also became a poor pressure resistance.

[Object of the Invention]

The object of the present invention has been made in view of the above-mentioned drawbacks of the conventional processing technique in the direction perpendicular to the substrate surface, and a minute diffusion region having a dimension of 1.0 μm or less is formed on the sidewall surface of the cut portion such as the U groove. Low power consumption, which ensures a high yield
An object of the present invention is to provide a method of manufacturing a semiconductor device that operates at high efficiency and frequency.

Another object of the present invention is to provide a novel method for forming a favorable selective diffusion layer on the side wall surface of a notch such as a U-groove and forming a pn junction electrode having a small leak current and a high breakdown voltage on the side wall portion. To do.

[Outline of Invention]

In order to achieve this object, the method according to the invention is
Forming a U-shaped groove, and selectively diffusing into the bottom surface of this U-shaped groove and a part of the side wall surface adjacent to this bottom surface; and using the mask used for the selective diffusion to form the second notch. A step of forming a groove that is shallower than the depth of selective diffusion and continuous with the U-shaped groove; and a step of forming a non-oxidizing film on the sidewall surfaces of the first cut portion and the second cut portion, In the third cut, only the diffusion region of the U-shaped sidewall is left, the diffusion region of the U-shaped groove bottom is completely removed, and a deeper groove is formed, and the selective oxidation using the non-oxidizing film is performed. At least, a step of forming an oxide film on the bottom surface of the groove and a step of removing the non-oxidizing film to open a contact hole for the diffusion region of the side wall surface.

〔Example〕

Hereinafter, a method of manufacturing the cut gate type SIT according to the first embodiment of the present invention will be described with reference to the drawings.

(1) As shown in Fig. 5 (a), n ⁺ Si becomes the drain.
On the substrate (impurity density 10 ¹⁸ / cm ³ ) 1, an n ⁻ layer (impurity density 10 ¹³ to 10 ¹⁴ / cm ³ ) 2 operating layer was grown to a thickness of about 5 μm by epitaxial growth, and then oxidized by thermal oxidation or the like. Membrane 5
About 1 μm is formed. Then by photolithographic technology OMR8
A resist film 8 such as 3 is selectively formed in a portion other than the cut region.

(2) As shown in FIG. 5B, the oxide film 5 is removed using the resist 8 as a mask to cut the n ⁻ layer 2 to a depth of about 0.7 μ (first cutting step). In this case, it is desirable that the side surface of the cut portion be substantially perpendicular to the surface of the n ⁻ layer 2 and that the bottom surface be close to a flat surface. Examples include plasma etching and sputter etching that flatten the bottom surface. For example, to use plasma etching
n ⁺ Select the crystal plane of substrate 1 as the (111) plane and set the mask direction to <1
First, the oxide film 5 is 0.1 Torr of C ₃ F ₈ gas according to the 10> direction.
Plasma etching is performed at r, and then the gas is PCl ₃ gas 0.05 to 0.1To
If the n ⁻ layer 2 is plasma-etched instead of rr, it can be cut into a shape having a side surface (wall surface) perpendicular to the surface of the n ⁻ layer 2 and a flat bottom surface. Then, the resist 8 is removed by O ₂ gas plasma.

(3) As shown in FIG. 5 (c), an oxide film 5 is formed in a portion cut by thermal oxidation or the like to about 5000 Å. At this time, the oxide film 5 on the surface of the n ⁻ layer 2 formed in 1 increases to about 1.1 μ.

(4) As shown in FIG. 5D, the bottom oxide film 5 is etched by directional plasma etching, sputter etching or the like. In this case, the oxide film 5 on the side surface (wall surface) remains due to the directivity, and the oxide film 5 on the surface of the n ⁻ layer 2 is reduced to about 6000Å. Using the oxide film 5 as a mask, boron or the like is diffused to form ap ⁺ region 11 with a diffusion depth of 0.3 μm. The impurity density of the p ⁺ region 11 is about 3 × 10 ¹⁸ to 10 ²⁰ cm ^-3 . If the p ⁺ region 11 is formed by ion implantation of ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ and subsequent annealing in a non-oxidizing atmosphere such as N ₂ gas, a BSG film is not formed on the p ⁺ region 11, which is preferable. is there.

(5) As shown in FIG. 5 (e), the n ⁻ layer 2 on the bottom surface of the U-shaped groove formed in the first cutting step is formed by the directional plasma etching so that the diffusion depth of the p ⁺ region is 0.3 μm. deeply,
Cut to a depth of 0.2 μm (second cutting step).
Of course, before the second cutting step, if necessary, the BSG film formed on the p ⁺ region 11 is removed by directional plasma etching using C ₃ F ₈ .

(6) As shown in FIG. 5 (f), a non-oxidizing film 9 such as a Si ₃ N ₄ film is formed by CVD or the like to a thickness of about 1000 to 1300Å. Si ₃ N
₄ A thin pad oxide film of about 300 to 500 Å may be formed before CVD.

(7) As shown in FIG. 5 (g), Si on the bottom surface cut by directional plasma etching, sputter etching, etc.
₃ N ₄ film 9 and the convex portion to remove the Si ₃ N ₄ film 9 on the surface, the sidewall surface Si ₃ N
Leave only ₄ membranes. For example, the Si ₃ N ₄ film is etched by reactive ion etching (RIE) with C ₃ F ₈ 0.02 to 0.05 Torr. Furthermore, the bottom n ⁻ layer is cut by about 1.0 μm by directional plasma etching or the like (third cutting step).

(8) As shown in FIG. 5 (h), an oxide film 5'is selectively formed on the cut bottom surface by about 3000 Å. That is, Si
_No oxide film is formed on the side wall surface where the ₃ N ₄ film 9 is present.

(9) As shown in FIG. 5 (i), a diffusion window is opened in the central portion of the surface of the convex portion of the n ⁻ layer 2 by the photolithographic technique, and the n ⁺ region 10 to be the source is 0.3 to 0.4 μm. The impurity density is formed at a depth of about 10 ²⁰ to 10 ²¹ cm ^-3 . It is preferable to use ion implantation of ⁷⁵ As ⁺ . After ion implantation, annealing is also performed for thermal oxidation, and oxide film 5'on the bottom surface of the cut portion
The thickness of 5000 ~ 6000Å. By this thermal oxidation, an oxide film of about 3000 Å is formed also on the source region.

(10) As shown in FIG. 5 (j), the source contact hole is opened by photolithographic technique. Also,
By etching the Si ₃ N ₄ film on the side wall cut by non-directional plasma etching, hot phosphoric acid etching, etc., the opening of the oxide film 5, that is, the gate contact hole is opened to a size of about 0.2 μm. Make a hole. After that, the gate electrode 12, the source electrode 13, and the drain electrode 14 are formed by a normal metallization technique.

〔The invention's effect〕

According to the present invention, it is possible to easily and reliably provide a region of an arbitrary conductivity type at an arbitrary position on the side wall surface of the cut portion of the semiconductor substrate. According to the present invention, since a minute diffusion region can be surely provided on the side wall surface, if applied to the formation of the gate region of the static induction transistor, a semiconductor device which operates at a very low power supply voltage and can be manufactured at high speed is manufactured. This is particularly effective for miniaturization of a semiconductor device having a three-dimensional structure. Further, according to the present invention, the contact hole for the diffusion region of the side wall surface can be formed without a defect such that the pn junction surface is exposed, so that a diode with a small withstand voltage with a leak current can be formed on the side wall of the cut portion.

[Brief description of drawings]

1 to 4 are prior arts, and FIG. 5 is an explanatory view of a method for manufacturing a cut gate type SIT according to an embodiment of the present invention. 1 ...... n ⁺ drain substrate, 2 ...... n ^- channel and channel-drain region of the epitaxial growth layer, 3 ...
... gate, 4 ... source, 5 and 5 '... 5 insulator such as oxide film, 6 ... gate electrode, 7 ... source electrode, 8 ... photoresist film, 9 ... Si ₃ N ₄ film, 10 ...... n ⁺ diffusion region, 1
1, 11 ′, 11 ″ …… p ⁺ diffusion region, 12, 13, 14 …… Metal electrode

Claims (1)

[Claims] 1. A notch having a side wall surface which is substantially vertical to the surface of a semiconductor substrate and having a bottom surface substantially parallel to the surface of the semiconductor substrate is formed by a first notch, and an insulating film is formed on the entire surface of the notch. The first step, the second step of removing the insulating film on the bottom surface of the cut portion by directional etching, and the selective diffusion of a high impurity density region on the bottom surface of the cut portion; A third step of forming a second notch that is shallower than the depth, and a fourth step of forming a non-oxidizing film only on the side wall surface of the notch formed by the first and second notches.
And a fifth step of a third notch in which the bottom surface of the second notch is continuously subjected to directional etching to further etch a predetermined depth deeper than the depth of the selective diffusion, Using the non-oxidizing film as a mask,
A sixth step of selectively oxidizing the entire surface of the notch formed by the third notch, and a seventh step of removing the non-oxidizing film to open a contact hole for the high impurity density region. A method for manufacturing a semiconductor device, comprising at least: