JPH0821720B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device of high speed and low power consumption, and particularly to an arbitrary portion of a sidewall surface of a U-shaped groove cut from a semiconductor substrate. The present invention relates to a processing technique related to a process of forming a diffusion region having a size of 1 to form a contact hole.

[Prior Art] Recent developments in semiconductor devices are remarkable, and aiming at high speed, low power consumption, high efficiency, and high integration density,
One after another, new concept, structure of transistor, thyristor,
ICs, memories, etc. have been proposed. Since the dimension control in the thickness direction is easier than in the planar direction and the three-dimensional structure cannot be avoided in order to meet the demand for ultra-high density such as 64 Mbit dynamic RAM, Various semiconductor devices have been proposed that require processing techniques for vertical surfaces. Especially electrostatic induction transistor (hereinafter referred to as SIT)
Static induction type semiconductor devices such as
It is known that by forming a gate on a vertically cut side wall part, its basically excellent characteristics become suitable for high frequency and high speed operation. FIG. 2 is an example of a sectional view of a notched gate type SIT. The n ⁺ Si substrate 1 is a drain, the n ⁻ layer 2 is a channel, the p ⁺ region 3 is a gate, the n ⁺ region 4 is a source, and it is on the oxide film 5. It has a structure in which the gate electrode 6 is formed to reduce the source-gate capacitance and the gate-drain capacitance, and to improve the conversion conductance.
Since g _m can be increased, it is suitable for high-efficiency operation in the microwave to submillimeter wave band. Reference numeral 7 is a source electrode.

However, in a semiconductor device having a notch from the semiconductor surface, it is almost impossible to form a diffusion window, a contact hole, or the like on the side wall surface of the notch by the photolithographic technique which is the basis of the conventional flattening technique. It was

[Problems to be Solved by the Invention] As a technique for forming a diffusion window and a contact window on the side wall surface of the cut portion of the semiconductor device having the cut portion (U-shaped groove) described above, Japanese Patent Publication No. Sho 62-32632 and The technique disclosed in Japanese Patent Publication No. 01-031309 is proposed. FIGS. 3 (a) to 3 (j) show the manufacturing process of the N-channel SIT disclosed in Japanese Patent Publication No. 62-32632.

(1) As shown in FIG. 3 (a), an n ^- layer (impurity density of 10 ¹³ to 10 ¹⁴ / cm ³ ) was formed by epitaxial growth on an n ⁺ Si substrate (impurity density of 10 ¹⁸ / cm ³ ) 1 to be a drain. The second operating layer is grown to a thickness of about 10 μm, and then the oxide film 5 is formed by thermal oxidation or the like.
Of about 1 μm. Next, using photolithographic technology, OM
A resist film 8 of R83 or the like is selectively formed in a portion other than the region to be cut.

(2) As shown in FIG. 3 (b), the oxide film 5 is removed using the resist 8 as a mask, and the n ⁻ layer 2 is cut to a depth of about 3 μm. In this case, it is desirable that the side surface of the cut portion be substantially perpendicular to the surface of the n ⁻ layer 2, and further that the bottom surface be close to a flat surface. Examples include plasma etching and sputter etching that flatten the bottom surface. For example, to perform plasma etching, the crystal plane of the n ⁺ substrate 1 should be (11
1) Select the surface and align the direction of the mask with the <110> direction. First, plasma etch the oxide film 5 with a C ₃ F ₈ gas of 0.1 Torr and then change the gas to a PCl ₃ gas of 0.05 to 0.1 Torr and n ^−. If the layer 2 is plasma-etched, it can be cut into a shape having a side surface (wall surface) perpendicular to the surface of the n ⁻ layer 2 and a flat bottom surface. Then, the resist 8 is removed by O ₂ gas plasma.

(3) As shown in FIG. 3 (c), an oxide film 5 is formed in a portion cut by thermal oxidation or the like to about 5000 Å. At this time, the oxide film 5 on the surface of the n ⁻ layer 2 formed in 1 increases to about 1.1 μm.

(4) As shown in FIG. 3D, the bottom oxide film 5 is etched by directional plasma etching, sputter etching or the like. In this case, the oxide film 5 on the side surface (wall surface) remains due to the directivity, and the oxide film 5 on the surface of the n ⁻ layer 2 is reduced to about 6000Å. Then, cut the bottom n ^- layer 2 by about 1.5
Plasma etch about μm. For example, for plasma etching, the oxide film 5 is etched with C ₃ F ₈ 0.1 Torr and n ⁻ layer 2 is used.
Can be formed by etching with PCl ₃ 0.05 to 0.1 Torr.

(5) As shown in FIG. 3 (e), a Si ₃ N ₄ film 9 is formed by CVD or the like.
To form about 1000Å.

(6) As shown in FIG. 3 (f), the bottom surface cut by directional plasma etching, sputter etching, etc.
The Si ₃ N ₄ film 9 and the Si ₃ N ₄ film 9 on the surface of the n ⁻ layer 2 are etched. Si
_{The 3} N ₄ film 9 remains only on the cut side surface (wall surface). For example, C ₃ F ₈ 0.02 ~
It can be formed by etching at 0.05 Torr.

(7) As shown in FIG. 3 (g), an oxide film 59 is formed on the cut bottom surface by thermal oxidation or the like to have a thickness of about 5000Å. At this time, the oxide film 59 is not formed on the side surface (wall surface) where the Si ₃ N ₄ film 9 is cut. The oxide film 5 on the surface of the n ^- layer 2 is about 80
Increase to 00Å.

(8) As shown in FIG. 3 (h), the oxide film 5 above the source region is removed on the surface of the n ⁻ layer 2 by photolithography, and the n ⁺ region 10 (impurity density ~ 10 ²¹ / c
m ³ is formed to a depth of about 0.5 μm. In this case, Si ₃ N ₄ uses As having a high masking property as an impurity source.

(9) As shown in FIG. 3 (i), if the Si ₃ N ₄ film 9 is etched on the side surface (wall surface) cut by non-directional plasma etching, hot phosphoric acid etching, etc., the oxide film 5 is opened. Division 1.0
It is possible to make about μm, and p ⁺
The gate of the region 11 is formed to a depth of 0.5 μm from the side surface (end surface). The impurity density of this gate is lower than the impurity density of the n ⁺ region 10 and is about 10 ²⁰ to 10 ¹⁹ / cm ³ . Therefore, the n ⁺ region 10 does not need to be masked, and the formation of the p ⁺ region 11 has little influence.

(10) As shown in FIG. 3 (j), a metal film of Al or the like is formed to a thickness of about 1.5 μm by vapor deposition or the like, and is formed on the gate electrode 12 and the source electrode 13 by the photolithographic technique. Since normal vapor deposition has directivity, it is vapor-deposited only on the surface of the n ⁻ layer 2 and the cut bottom surface, and only the scattered portion adheres to the side surface (wall surface), so photolithographic technology is not required. Gate electrode 12 and source electrode 13 can be easily
Can also be separated. A metal film is vapor-deposited on the lower surface to form the drain electrode 14.

[Problems to be Solved by the Invention] However, according to the method shown in FIG. 3, the width of the opening portion as the gate diffusion window in the direction perpendicular to the substrate surface is 1.0.
In the case of a relatively large value of about μm or more, it is easy to form the p ⁺ region 11 on the side wall surface by diffusion or the like as shown in FIG. 3, but the width of the opening as the gate diffusion window is 1.0. μm
With the following fine dimensions, there is a problem that the p ⁺ region 11 is not sufficiently formed, or a problem that the p ⁺ region 11 is only partially formed. As a result, the gate effect is poor, the conversion conductance g _m is lowered, and It has a drawback that it does not operate unless a high voltage is applied to the gate. Figure 4 shows the drain current Id-drain voltage Vd characteristics of the SIT when the gate diffusion window width on the side wall is 0.7 μm.
It was found that the gate does not work unless 3 V or more is applied, and it does not work effectively as a SIT. Therefore, according to the manufacturing method shown in FIG. 3, a power-saving (low power consumption), high-efficiency junction type SIT that operates at a power supply voltage of 1.5 V and a cut-off frequency of 10 G
1.0 μm required for high-frequency junction type SIT of Hz or higher
There is a drawback that it is extremely difficult to open a diffusion window having the following fine dimensions and a contact hole.

When the gate diffusion window width is 1.0 μm or less, it is difficult to open the window because the cross-sectional shape of the second plasma etching in FIG. 3 (d) shows the bottom and side walls as shown in FIG. 5 (a). Since the boundary is rounded, the bird's beak portion in the so-called planar type LOCOS (LOCOS: Local Oxidation of Silicon) process becomes large when selective oxidation is performed, and it becomes larger than necessary. It was found that the oxide film 59 penetrates into the lower part of the Si ₃ N ₄ 9, which causes the problem that the opening becomes small.

Further, it is important to reduce the capacitance between the gate and the drain in order to increase the frequency of the junction type SIT, and for this purpose, it is preferable that the oxide film 59 is as thick as possible. In order to thicken the oxide film 59, it is desirable that the plasma etching in FIG. 3 (d) be as deep as possible, and if possible reach the substrate. However, plasma etching with high directivity for forming vertical side walls is better as the pressure of the etching gas is lower, but when the pressure is lower, the sputtering action becomes stronger and the etching selectivity between the oxide film and Si becomes smaller. Therefore, when deep Si etching is performed under the condition that the directivity is high, the oxide film 5 is lost.

The object of the present invention has been made in view of the above-described drawbacks of the conventional processing technique in the direction perpendicular to the substrate surface, and the side wall surface of the cut portion such as the U-shaped groove has a size of 1.0 μm or less. It is an object of the present invention to provide a method for manufacturing a semiconductor device which operates with high efficiency and high frequency, with low power consumption for surely forming a diffusion region with high yield.

Another object of the present invention is to provide a novel method for surely forming a diffusion window or a contact hole in a side wall portion of a cut portion such as a U-shaped groove even if the directivity of plasma etching is relatively poor. is there.

Still another object of the present invention is not limited to the directivity in plasma etching and the relationship in which the selection ratio (Si: oxide film) is in a trade-off relationship with each other. It is to provide a method for manufacturing a semiconductor device. Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of high frequency operation by thickening an oxide film under a gate electrode.

[Means and Actions for Solving the Problem] In order to achieve this object, in the method according to the present invention, a U-shaped groove is formed by the first cut, the U-shaped groove is entirely oxidized, and then the U-shaped groove is formed. A step of leaving only the oxide film on the bottom while leaving the oxide film on the side wall, a step of further cutting by a second notch to a depth corresponding to the dimension of the diffusion window, and a step of cutting the side wall of the groove formed by the second notch 300 to Forming a thin oxide film having a thickness of about 1000 Å, making a third cut continuously to the groove formed by the second cut, and the first to third
The step of forming a non-oxidizing film such as a nitride film on the side wall surface of the groove portion formed by the notch and selectively oxidizing the bottom surface of the groove portion, and removing the non-oxidizing mask, a predetermined place on the side wall surface is formed. It is characterized in that it is less involved with the step of exposing only one.

[Embodiment] Hereinafter, a method of manufacturing a cut gate type SIT according to a first embodiment of the present invention will be described with reference to the drawings.

(1) As shown in FIG. 1 (a), an n ^- layer (impurity density 10 ¹³ to 10 ¹⁴ / cm ³ ) is formed by epitaxial growth on an n ⁺ Si substrate (impurity density 10 ¹⁸ / cm ³ ) 1 which will be a drain. No. 2 operating layer is grown to a thickness of about 5 μm, and then an oxide film 5 is formed by thermal oxidation or the like.
Of about 1 μm. Next, using photolithographic technology, OM
A resist film 8 such as R83 is selectively formed in a portion other than the cut area.

(2) As shown in FIG. 1 (b), the oxide film 5 is removed using the resist 8 as a mask to cut the n ⁻ layer 2 to a depth of about 0.7 μm (first cutting step). In this case, it is desirable that the side surface of the cut portion be substantially perpendicular to the surface of the n ⁻ layer 2 and that the bottom surface be close to a flat surface. Examples include plasma etching and sputter etching that flatten the bottom surface. For example, to use plasma etching
n ⁺ Select the crystal plane of substrate 1 as the (111) plane and set the mask direction to <1
10> direction, first press the oxide film 5 with C ₃ F ₈ gas.
Plasma etching is performed at 0.1 Torr, then the gas is changed to PCl ₃ gas, and the plasma is applied to the n ⁻ layer 2 at a pressure of 0.05 to 0.1 Torr, the side surface (wall surface) perpendicular to the surface of the n ⁻ layer 2 and the flat bottom surface. Can be cut into a shape having. Then, the resist 8 is removed by O ₂ gas plasma.

(3) As shown in FIG. 1 (c), an oxide film 5 is formed in a portion cut by thermal oxidation or the like to a thickness of about 5000Å. At this time, the oxide film 5 on the surface of the n ⁻ layer 2 formed in 1 increases to about 1.1 μm.

(4) As shown in FIG. 1 (d), the oxide film 5 on the bottom surface cut by directional plasma etching, sputter etching or the like is etched. In this case, the oxide film 5 on the side surface (wall surface) remains due to the directivity, and the oxide film 5 on the surface of the n ⁻ layer 2 is reduced to about 6000Å.

Then, the n ⁻ layer 2 on the bottom surface that has been cut is further plasma-etched by about 0.5 μm (second cutting). In this second cut, since the requirement for the directivity of etching is relaxed, relatively isotropic etching is sufficient as shown in FIG. 1 (d). Therefore, the pressure of the PCl ₃ gas may be a value on the high pressure side of 0.1 to 0.2 Torr, and the selection ratio (Si / SiO ₂ ) at this time is extremely high, so that the oxide film 5 is hardly thinned in the second cut.

(5) As shown in FIG. 1 (e), the entire surface is subjected to thermal oxidation or the like.
A thin oxide film 52 of 300 to 1000Å is formed, and this thin oxide film 52 is formed only on the side wall surface of the cut portion by directional plasma etching.
Leave.

(6) As shown in FIG. 1 (f), a 0.5 μm incision depth is added by the third incision. In order to increase the frequency of SIT, the third notch is about 5μ until it reaches the substrate.
m is desirable. In this case, as shown in FIG. 1 h (f), the directivity of etching is somewhat poor, and isotropic etching may be used. Therefore, the selection ratio with respect to the oxide film is increased, and deep etching can be performed. In plasma etching of PCl ₃ , if the directivity is sacrificed and etching is performed on the high pressure side, a selection ratio of 30 to 50 can be easily realized. LOCOS on the side wall
Considering the bird's beak in, the plasma etching of the third cut is made into two stages and the high pressure of 0.1 ~
Etching at 0.2 Torr, 0.0 when reaching the target depth
If the etching is switched to 3 to 0.05 Torr, the bottom surface of the cut portion and the side wall surface have a nearly vertical cross-sectional shape. As described above, when the third notch is about 0.5 μm or less, the gas pressure may be 0.03 to 0.05 Torr from the beginning.

(7) As shown in FIG. 1 (g), a Si ₃ N ₄ film 9 is formed by CVD or the like.
To form 1000 to 1300Å.

(8) As shown in FIG. 1 (h), the Si ₃ N ₄ film 9 is left only on the side wall surface by directional plasma etching, sputter etching, etc., and the others are removed by etching. Next, using the Si ₃ N ₄ film 9 as a mask, a thermal oxide film 59 of 3000 to 4000 Å is formed on the bottom surface of the cut portion by a selective oxidation method. 5μ in Fig. 1 (f)
When forming a notch deeply about m, before thermal oxidation,
An oxide is previously deposited to a thickness of 4 to 4.5 μm by directional electron beam evaporation of SiO ₂ or SiO. Usually, when an oxide is deposited in the recess by the vapor deposition method, the oxide is trapezoidally deposited in the recess, and a gap is formed between the sidewall of the recess and the trapezoidal oxide, and this may be filled with thermal oxidation.

(9) As shown in FIG. 1 (i), a source n ⁺ region 10 having a depth of about 0.3 to 0.5 μm is formed on the surface of the convex portion of the n ⁻ layer 2 near the center by a photolithographic technique. To form. ⁷⁵
If As ⁺ ion implantation is used, a source region with an impurity density of about 10 ²¹ cm ^-3 can be easily formed. After the ion implantation, a 3000-3500Å oxide film is formed on the upper part of the source diffusion window by thermal oxidation. As a result, the oxide film 59 on the bottom of the notch is 5000
It will be ~ 6000Å thick.

(10) As shown in FIG. 1 (j), if the Si ₃ N ₄ film 9 on the side wall is removed by non-directional plasma etching, hot phosphoric acid etching, etc., the gate diffusion window has a width of 0.4 to 0.5 μm. It is opened by. Impurity density of 5 × 10 ¹⁸ to 10 ²⁰ cm ^{-3 in} this hole,
Boron is diffused to a depth of about 0.5 μm from the side wall surface. After the diffusion, if BSG is formed on the surface of the opening, it is removed by etching to open the gate contact hole. Next, the oxide film above the source diffusion region 10 is removed by photolithography, the source contact hole is opened, and the gate electrode 12 and the source electrode are formed by the usual metallization technique.
13 and the drain electrode 14 are formed.

EFFECTS OF THE INVENTION According to the present invention, it is possible to selectively provide a region of an arbitrary conductivity type at an arbitrary position on the side wall surface of the cut portion of the semiconductor substrate. Further, according to the present invention, in the selective oxidation of the side wall portion, so-called bird's beak, which is the biting of the oxide film under the Si ₃ N ₄ film as a mask, becomes extremely small, so that a diffusion window opening of a minute dimension can be achieved. It can be realized with good controllability and reproducibility. Further according to the invention, a total of 3
Since the U-shaped groove is formed in the number of cutting steps, even if the directivity of the plasma etching in each cutting step is poor, a sidewall close to vertical can be obtained as a result.
That is, the plasma etching directivity and selectivity (Si vs.
It is known to have a trade-off relationship with SiO ₂ ), but it is possible to increase the selection ratio at the expense of directivity, and this enables deep etching. Further, according to the present invention, the performance requirements for the plasma etching apparatus are relaxed, so that the apparatus can be simple, and as a result, a semiconductor device can be manufactured at low cost and with high yield.

[Brief description of drawings]

FIG. 1 is a cut gate type SIT according to an embodiment of the present invention.
2 is a cross-sectional view for explaining a method for manufacturing the same, FIG. 2 is a cross-sectional view for showing a conventional cut gate type SIT, FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing an N-channel SIT, and FIG.
FIG. 5 is a characteristic diagram showing an example of the drain current Id-Vd characteristic of the conventional SIT, and FIG. 5 is a sectional view showing an enlarged part of FIG. 1 …… n ⁺ Si substrate, 2 …… n ^- layer, 5 …… oxide film, 59 …… thermal oxide film, 8 …… resist film, 9 …… Si ₃ N ₄ film, 10 …… n ⁺
Area, 52 ... oxide film.

Claims (2)

[Claims] 1. A semiconductor substrate is first formed by a first cut.
The first step of digging the first groove and forming the first oxide film on the side wall of the first groove, and the second notch continuing to the bottom of the first groove and further the second groove. By a second step of forming a second oxide film on the side wall of the second groove, and a third notch to form a third groove continuously with the bottom of the second groove. A third step of digging, and a non-oxidizing film is selectively formed on the side walls of the first to third grooves, and the non-oxidizing film is used as a mask to form the third film.
A fourth step of forming a third oxide film that is thicker than the first and second oxide films on the bottom of the groove, and removing the non-oxidizing film near the sidewall of the second groove. A semiconductor device, characterized in that the semiconductor substrate is exposed to serve as a diffusion window, and a fifth step of diffusing the impurities constituting the gate control region into the semiconductor substrate through the diffusion window is performed at least. Method. 2. The cutting in the third step uses plasma etching, wherein the plasma etching is performed in two steps, first etching at high pressure and then at low pressure with good directivity. 1. The method for manufacturing a semiconductor device according to 1.