JPH07105894B2 - Vertical deflection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a vertical deflection circuit such as a CRT display monitor and a television receiver.

2. Description of the Related Art In recent years, there has been a strong demand for high-density display in CRT display devices as information is expanded. The vertical deflection circuit handles the display density in the horizontal direction, but the vertical deflection circuit takes charge of the display density in the vertical direction. Only the field of vertical deflection circuits will be mentioned here.

An interlace method is one of the means for increasing the display density. In this method, the vertical display area density can be twice as high as that of the non-interlace method under the same horizontal deflection frequency. In order to take advantage of this advantage, many interlace systems have begun to be adopted.

The conventional example as described above will be described below with reference to the drawings.

FIG. 4 shows an example of a general multi-vibrator type vertical deflection circuit, in which (a) is an input terminal to which a negative polarity vertical synchronizing signal S is inputted. Reference numeral 1 is a base resistance, 2 is a transistor, and 3 is a collector resistance. The base resistance 1, the transistor 2, and the collector resistance 3 constitute an inverter circuit 20 for a vertical synchronizing signal. Reference numeral 16 is a coupling capacitor, and 4 is a coupling capacitor that controls the time constant, and determines the oscillation frequency together with the oscillation circuit 9. 9a is a switching transistor, 9b is a vertical amplitude adjusting resistor, 9d is a sawtooth wave generating capacitor, and 9e is a resistor that plays a part in the vertical oscillation time constant. Upon receiving the sawtooth wave voltage from the oscillator circuit 9, the vertical drive circuit 10 performs vertical drive, and supplies the sawtooth wave current to the vertical deflection coil 13 via the vertical output circuit 11. Reference numeral 14 is a vertical output coupling capacitor, and 15 is a negative feedback resistor. (B) is voltage
B ₁ is the power source supplied, and (c) is the power source supplied with the voltage B ₂ . The voltages B ₁ and B _{2 for} both need not be separate power supplies. Reference numeral 12 is a coupling capacitor, and resistors 7 and 8 forming an impedance network of 19 appropriately reduce the output sawtooth wave voltage, and positively feed back the output sawtooth wave voltage to the input of the oscillation circuit 9 via the resistor 6. This constitutes a multivibrator. In particular, no special compensation circuit for the interlace system is provided.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above circuit, the horizontal signal component is not mixed into the ground circuit, or the arrangement of the elements of the oscillation circuit configured on the printed circuit board does not pick up noise, etc.
Needed due consideration. Also, depending on the setting value of the vertical synchronization or vertical amplitude adjustment resistor, the trigger phase between the vertical output pulse as the positive feedback pulse and the synchronization signal may slightly differ, and the interfering phase of the horizontal signal component changes, so There is a tendency to cause a bearing phenomenon, that is, a place where there is no contact, and the interlace quality is generally low. In particular, as a factor that adversely affects the interlace operation, there has been interference with the trigger point of the oscillation circuit by the horizontal signal component mixed in the positive feedback circuit of the vertical output pulse.

In view of the above problems, it is an object of the present invention to provide a vertical deflection circuit that creates a high-quality interlaced state regardless of vertical synchronization and oscillation settings.

In order to achieve this object, the vertical deflection circuit of the present invention comprises:
An input terminal to which a vertical synchronizing signal is input, an inverter circuit connected to the input terminal and connected to a first power source, an output terminal of the inverter circuit connected to the input terminal and connected to a second current An oscillator circuit, a vertical drive circuit connected to the output terminal of the oscillator circuit, a vertical output circuit connected to the output terminal of the vertical drive circuit, and an output terminal of the vertical output circuit connected to one end. And a deflection coil grounded via a negative feedback resistor and a vertical output coupling capacitor whose other end is connected in series, and an output terminal of the vertical output circuit connected to one end and an output of the vertical output circuit An impedance network for reducing the voltage, and a diode having the other end of the impedance network connected to the cathode and the anode connected to the input terminal of the oscillator circuit. When the vertical synchronization signal is input, the oscillation operation is maintained in synchronization with the vertical synchronization signal, and when the vertical synchronization signal is not input, the oscillation operation is performed by repeating the on / off operation of the diode. Is configured to maintain.

With this configuration, when the vertical synchronizing signal is input, the vertical output pulse is not positively fed back by the diode or the switching element, and the switching transistor is directly driven only by the synchronizing signal.

On the other hand, when the vertical sync signal is not input, the transistor is off, and the current supplied to the switching transistor by the power supply of the inverter circuit and the vertical output pulse voltage positively fed back to the cathode of the diode or switching element are While reverse biasing the device, turn on the switching transistor,
Further, while the diode or the switching element is forward biased, the switching transistor is turned off and the oscillation action is connected.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of a vertical deflection circuit according to an embodiment of the present invention. In FIG. 1, 2
Is a transistor, the base of which is connected to the input terminal (a) through the base resistor 1. 3 is the collector resistance,
(B) is a first power supply for supplying the voltage + B ₁ (V) to the inverter circuit 20. Reference numeral 4 is a first coupling capacitor that plays a role in the oscillation time constant, 9 is an oscillation circuit connected to the output terminal of the inverter circuit 20, and in the oscillation circuit 9, 9a is a switching transistor, 9b is a vertical amplitude adjustment resistor, and 9c is A resistor, which plays a role in the vertical oscillation time constant, 9d is a sawtooth wave generating capacitor, the output of which is amplified by the vertical drive circuit 10 and the vertical output circuit 11 to drive the deflection coil 13. In the output circuit 21, 13 is a deflection coil, 14 is a vertical output coupling capacitor, and 15 is a negative feedback resistor. Reference numeral 12 is a second coupling capacitor, and reference numerals 7 and 8 are voltage dividing resistors, which drop the output pulse voltage. Reference numeral 5 is a diode and 6 is a current control resistor. The anode side of the diode is a and the cathode side is b.

The operation of the vertical deflection circuit configured as described above will be described below. In the description, the presence or absence of the vertical sync signal will be described separately.

First, when the vertical synchronizing signal is input, the transistor 2 is turned on. The negative polarity signal input to the base of the transistor 2 becomes a positive polarity pulse and triggers the switching transistor 9a via the coupling capacitor 4. The sawtooth wave output generated by the oscillator circuit 9 is amplified by the drive circuit 10, and the vertical output circuit 11 generates a vertical output pulse P. This pulse is the second coupling capacitor 12
The voltage is divided by the first and second voltage dividing resistors 7 and 8 via the resistor, and the stepped down vertical output pulse voltage appears between the resistors 7.
Since the diode connected in series with is reverse biased, the switching transistor 9a cannot be triggered. The anode voltage of the diode 5 is as shown in FIG. 2 (a), the cathode voltage is as shown in FIG. 2 (b), and the voltage dividing resistors 7 and 8 are set so that E ₁ <E _2. Set. Therefore, as the operation of the vertical deflection circuit, there is no positive feedback pulse, and the inverter circuit 20 is directly driven.

On the other hand, when the vertical synchronizing signal is not input, the transistor 2 is off. In this case, during the vertical scanning period, current is supplied from the voltage B ₁ of the power source (b) through the collector resistor 3, the diode 5, the resistor 6, and the voltage dividing resistor 7, and the first coupling The discharge current of the capacitor 4 is also discharged via the diode 5.

On the other hand, during the vertical blanking period, the diode 5 is reverse biased by the positive output vertical output pulse, and the voltage of the power supply (b)
The switching transistor 9a is turned off by supplying a trigger pulse to the switching transistor 9a while charging the coupling capacitor 4 via the resistor 3 from B ₁ .
The oscillation operation is maintained by repeating the on-off operation of the diode 5 as described above. The anode voltage E _a of the diode 5 in this case of FIG. 3 (a), the cathode voltage E _b
Is shown in FIG. 3 (b). Set so that E ₁ ′ <E ₂ ′.

As described above, according to this embodiment, it is possible to switch between self-excited oscillation and other-excited oscillation only by adding one switching diode. In the case of a CRT display monitor, the inverter circuit in the preceding stage of the switching transistor of the oscillation circuit may be equivalently configured on the computer side.

Further, although the diode is used as the switching element in the present embodiment, other semiconductor switching elements may be triggered by the vertical output pulse. A schematic diagram is shown in FIG.
Reference numeral 18 is a semiconductor switching element, and 17 is a series resistance.

As described above, according to the present invention, by simply connecting the switching diode in series to the positive feedback circuit, the vertical signal in which the horizontal signal component of the positive feedback circuit, which is harmful to the interlacing action at the time of inputting the vertical synchronization signal, is mixed. The output pulse can be blocked, the separately excited oscillation operation can be performed, and the interlace quality can be significantly improved.

Further, since the separately excited oscillation is used, the synchronous adjustment resistor is replaced with a fixed resistor, and the parts cost and the adjustment cost can be reduced.

On the other hand, since there is no self-oscillation when there is no signal, there is no problem in vertical deflection operation. Therefore, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a vertical deflection circuit according to an embodiment of the present invention, and FIG. 2 is a voltage waveform diagram of a main part of the embodiment when a synchronizing signal is input,
FIG. 3 is a voltage waveform diagram of a main part of the embodiment when there is no signal, and FIG.
FIG. 5 is a circuit diagram of a conventional vertical deflection circuit, and FIG. 5 is a circuit diagram of a vertical deflection circuit of another embodiment of the present invention. 1 ... Base resistance, 2 ... Transistor, 3 ... Collector resistance, 4 ... First coupling capacitor, 5 ... Diode, 6 ... Current limiting resistance, 7 ... First voltage division resistance, 8 ...... Second voltage division resistance, 9 ... Oscillation circuit, 9a ...
… Switching transistor, 9b… Vertical amplitude adjustment resistor, 9c… Resistor, 9d… Sawtooth wave generating capacitor,
10 …… vertical drive circuit, 11 …… vertical output circuit, 12 ……
Second coupling capacitor, 13 ... Deflection coil, 14 ... Vertical output coupling capacitor, 15 ... Negative feedback resistor, 19 ... Impedance network, 20 ... Inverter circuit.

Claims (1)

[Claims] 1. An input terminal to which a vertical synchronizing signal is input, an inverter circuit connected to the input terminal and connected to a first power supply, and a second power supply connected to an output terminal of the inverter circuit. An oscillation circuit connected, a vertical drive circuit connected to the output terminal of the oscillation circuit, a vertical output circuit connected to the output terminal of the vertical drive circuit, and an output terminal of the vertical output circuit at one end. A vertical output coupling capacitor connected to the other end in series and a deflection coil grounded via a negative feedback resistor, and an output terminal of the vertical output circuit connected to one end and the vertical output circuit Impedance network for reducing the output voltage of the die, and a die in which the other end of the impedance network is connected to the cathode and the anode is connected to the input terminal of the oscillator circuit. When the vertical synchronization signal is input, the oscillation operation is maintained in synchronization with the vertical synchronization signal, and when the vertical synchronization signal is not input, oscillation is performed by repeating the on / off operation of the diode. Vertical deflection circuit configured to maintain operation.