JPH07105904B2 - Digital equalizer circuit - Google Patents

Description

Description: [Object of the invention] (Field of industrial application) The present invention relates to a ghost removing device for automatically removing television ghosts, and more particularly to a digital apparatus for digitally performing ghost removal. With regard to the digitized circuit.

(Prior Art) An apparatus for automatically and digitally removing a television ghost by using a digital equalization circuit is conventionally known. An example is shown in FIG.

For details of this configuration and operation, refer to Reference 1 (Murakami et al., "Digitalized Ghost Automatic Elimination Device" Technical Report of IEICE.
EMCJ78-37, November 1978), but its outline is shown below. This device is all digital,
Digital video signal including ghost is input terminal 1
And is input to the digital equalization circuit 2. As shown in FIG. 14, the digital equalization circuit 2 includes N + M unit delay elements 201 (delay time T [sec]) and N + M + 1.
It is composed of a tap coefficient unit 202 (digital multiplier), an adder 203 for adding the outputs of the tap coefficient units, and a tap gain memory 204. Tap coefficients of the tap coefficient unit (C _-M ~C _N) is set to an appropriate value by the control circuit 3, the ghost digital video signal removal is outputted to the output terminal 5.

The reference signal for removing the ghost is the differential waveform (b) of the trailing edge portion (a) of the vertical synchronizing signal shown in FIG. 3, and the ghost detection circuit 32 performs this differential operation (the difference operation can be substituted).
The peak corresponding to the trailing edge of the trailing edge of the vertical synchronizing signal is set to time reference 0, and each peak d _i after this time reference is detected.

The sign of this differential value d _i corresponds to the positive / negative residual ghost having the delay time iT. Therefore, the tap gain correction circuit 31
Uses this differential value d _i to successively correct each tap gain according to the following equation.

C _i.new = C _i.old −Δsgn (d _i ) ... (2) (i = −M to N, i ≠ 0) where C _i.old is the tap gain before correction and C _i.new is The corrected tap gain, Δ is a small positive correction coefficient, and equation (2) is the Zero Forcing method.
Widely known. The center tap coefficient C ₀ is fixed to C ₀ = 1 (3). Every time the vertical sync signal arrives (1/60
(Seconds), the ghost is removed by performing this sequential correction. The sequence controller 4 controls the sequence of the control circuit 3 described above, and for example, RO
It can be configured using M.

There is also known a device for eliminating a ghost by using a combination of a fixed delay circuit and a transversal filter (JP-A-56-158579).

(Problems to be Solved by the Invention) However, in the conventional digital equalization circuit as described above, a large number of coefficient multipliers (multipliers) are required to perform sufficient ghost removal. Since a general-purpose digital multiplier used for is expensive and its scale is large (one multiplier is one IC), a practical ghost removing device could not be obtained. On the other hand, although an analog equalizer circuit using a CCD has been put to practical use as a ghost elimination device, it has a problem in that it remains unerased and S / N.

To describe the above-mentioned problem a little more concretely, even if the digital IC technology which has made rapid progress in recent years is used, at most about 10 multipliers can be integrated in one IC. This is because a coefficient multiplier for the ghost elimination transversal filter requires an 8-bit × 8-bit multiplier, and at the latest technology level, a 16-bit × 16-bit CMOS multiplier is 3.5 mm ×
5.0 mm (Reference 2: Yoshio Kaji “A45ns 16 × 16 CMOS Mu
ltiplier "ISSCC84 WPM8.1), so a practical chip size of 7mm x 7mm on an IC chip, 8bit x 8bit CMOS
The multiplier is This is because about 9 can be integrated.

The delay range of the ghost that can be removed by the N-tap transversal filter is NT (T is the sampling period, T = 1 / 3fs
c, 1 / 4fsc, (fsc (color subcarrier frequency = 3.58MH
z)), therefore, if N = 10 and T = 70 to 100 ns, then NT = 0.7 to 1 μs (5), which is insufficient as a ghost elimination transversal filter. Therefore, the equalization circuit used in the ghost elimination device that has already been put into practical use is as described in Reference 3 (Murakami et al., “Ghost Clean System”, Toshiba Review No. 1.38 No. 7, June 1983).
It used a CD (Charge Coupled Device) transversal filter. However, since this is an analog signal processing device, the linearity of the coefficient multiplier (multiplier) and the total S / N were insufficient. This defect has led to an increase in the amount of ghosts remaining on the screen and a decrease in S / N when viewed as a ghost elimination device.

Further, the technique of the above-mentioned Japanese Patent Laid-Open No. 56-158579 also has a problem that the grandchild ghost remains even if the ghost is removed at the primary ghost removal stage.

The present invention has been made in view of such problems,
It is an object of the present invention to provide a digitized ghost elimination device that does not require a large number of coefficient units and can therefore be practically used in terms of cost and hardware, and has sufficient ghost elimination performance.

[Configuration of the Invention] (Means for Solving the Problems) A digital equalization circuit according to a first aspect of the invention includes a first input terminal to which a first signal is input, and a delay time that can be changed. Of the variable delay circuit, a plurality of tap coefficient units to which the output of the variable delay circuit is applied and whose input terminals are commonly connected, and a plurality of first additions for adding the outputs of the plurality of tap coefficient units And a plurality of unit time delay elements for delaying the output of the tap coefficient unit by a unit time and sequentially inputting to the first adder of the next stage, and the time of the signal input to the first input terminal. An input weighted digital transversal filter that outputs a signal for equalizing the first signal within an equalization range based on the delay amount by the variable delay circuit with reference to the position on the axis, and is set from the outside. , The digital tiger A memory for storing a tap gain coefficient of the tap coefficient unit of the Sversal filter and a delay time in the variable delay circuit, and a device for deriving an output of the variable delay circuit, which is input to the first input terminal. A first output terminal capable of giving a signal delayed by a predetermined time with respect to the first signal to the outside, and an output from the first output terminal is different from the equalization range of the digital transversal filter. A second signal capable of inputting a second signal whose waveform is equalized in a predetermined equalization range that does not overlap
Output terminal of the digital transversal filter, a second adder for taking the sum of the second signal input to the second input terminal, and an output of the second adder The digital equalization circuit according to the second aspect of the present invention includes the first input terminal to which the first signal is input and the delay time that can be changed. A variable delay circuit that delays the first signal, a plurality of tap coefficient units to which the first signal is applied and whose input terminals are commonly connected, and a plurality of first tap coefficient units that add the outputs of the plurality of tap coefficient units. An adder, which has a plurality of unit time delay elements for delaying the output of the tap coefficient unit by a unit time and sequentially inputting to the first adder of the next stage, of a signal input to the first input terminal Within the specified equalization range based on the position on the time axis, 1. An input weighted digital transversal filter for outputting a signal for equalizing the signal No. 1, a tap gain coefficient of the tap coefficient unit of the digital transversal filter and a delay in the variable delay circuit, which are set from the outside. A memory for storing time, and for deriving an output of the variable delay circuit,
A first output terminal capable of giving a signal delayed by a predetermined time to the first signal input to the first input terminal to the outside, and an output from the first output terminal being the digital transformer. A second waveform equalized in a predetermined equalization range that is different from the equalization range of the Versal filter and does not overlap.
A second input terminal capable of receiving the second signal, a second adder that sums the output of the digital transversal filter and the second signal input to the second input terminal, and And a second output terminal for deriving the output of the second adder.

(Operation) In the present invention, the variable delay circuit adjusts the time difference between the television signal and the ghost signal input from the first input terminal. The input weighted digital transversal filter receives a signal delayed by a predetermined time from a variable delay circuit, for example, and removes a ghost having a predetermined delay time. For example, the output of the transversal filter of another digital equalization circuit is input through the second input terminal,
The second adder adds the output of the digital transversal filter and the signal from the second input terminal and outputs the result from the second output terminal. As a result, a signal for removing a plurality of ghosts having a predetermined delay time is generated.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital equalizing circuit according to the present invention, and FIG. 2 is a block diagram showing a digitized ghost removing device constructed by using the embodiment of FIG.

In FIG. 2, the digital video signal containing the ghost is input to one of the subtractors 29 in the equalization circuit. The output of the subtractor 29 is input to the output terminal 5 and the differentiating circuit 33 in the control circuit 3, and at the same time, the digital equalizing circuit (hereinafter,
The first output terminal O ₁ of the equalization unit 2i (i = 1, 2, 3) is input to the first input terminal I ₁ of the equalization unit) 21.
Is connected to the _first input terminal I ₁ of the equalization unit 2j (j = i + 1, i = 1, 2, 3). The second input terminal I ₂ of the equalization unit 24 is grounded and 0 is input. The second output terminal O ₂ of the equalization unit 2i (i4,3,2) is the second input terminal I of the equalization unit 2j (j = i−1, i = 4,3,2).
₂ and the second output terminal O ₂ of the equalization unit 21 is
It is input to the other input terminal of the subtractor 29.

The equalization units 21 to 24 have the same configuration, and the configuration is shown in FIG. The first input terminal I ₁ of the equalization unit 21 is input to the variable delay circuit 211 and connected to one input terminal of the switch S1 and the other input terminal of the switch S1 via the delay element D1 having the delay amount T. To be done. The output terminal of the switch S1 is connected to the other input terminal of the switch S2 via the input terminal of the switch S2 and the delay element D2 having the delay amount 2T. Hereafter, with the same repetition as this, S2, D3, S
3, D4, S4, D5, S5 are connected. Where each delay element Di is
It is composed of a shift register or latches connected in series i.

Therefore, the switch Si (i = 1, ..., 5) is set by the value of the delay amount memory DL of the equalization unit memory 214, thereby giving a variable delay circuit (T step) of 0 to 31T. Is configured. The output of the switch S5 is input to the delay circuit 216. The purpose of the delay circuit 216 is to align the delay times of the signals given by the switches S1 to S5 with the clock time T.

The output of the delay circuit 216 is the output of the variable delay circuit 211,
Weighting circuit 2 in digital transversal filter 212
Digital multiplier 21 which is each tap coefficient multiplier of 20
22 and the other input of the digital multiplier 2122 is connected to the tap gain memories C _{1 to} C ₅ of the equalization unit memory 214. The output of the multiplier 2122 is input to the adder of each tap of the delay circuit with tap 221, and each input signal is delayed and added repeatedly and output to the adder 213. That is, the output of the final stage is the variable delay circuit 211.
It has an amount of delay given by (4) as an offset and is the output of a digital filter with a variable tap number of 5 given by the transversal filter 212.

The output of this transversal filter 212 is the adder 213.
In, the output signal of the equalization unit 22 obtained from the second input terminal I ₂ of the equalization unit 21 is added to the signal delayed by the delay circuit 218 and input to the delay circuit 215. The purpose of these two delay circuits 215 and 218 is to align the delay time of the input signal from the input terminal and the output signal from the transversal filter 212 with the clock time T.

The output from the delay circuit 215 is connected to the _second output terminal O ₂ of the equalization unit 21. That is, this equalization unit 2
The second output terminal the output signal obtained from the O ₂ of 1 becomes a ghost canceling signal generated at each equalizing units 24,23,22,21 is connected to the other input terminal of the subtracter 29.

The output of the variable delay circuit 211 of the equalization unit 21 becomes the input of the delay circuit 217, is delayed by 2T, and is output to the _first output terminal O ₁ . The first output terminal O ₁ of the equalization unit 21 is connected to the _first input terminal I ₁ of the equalization unit 22, and the first output terminal O ₁ of the equalization unit 21 is connected.
Of the variable delay circuit 211 by delaying the output of the variable delay circuit 211 from the output of the variable delay circuit 211 for 2T time.
The delay circuit 216 and the delay circuit 215 can compensate the time delay by the delay circuit 218 of the equalization unit 21 and the maximum time delay (5T time) by the digital transversal filter 212 of the equalization unit 21, and connect one or more equalization units. In this case, the minimum tap interval at the connection point can be T.

That is, from the output of the subtracter 29, the delay time of the ghost elimination signal from each tap of the equalization unit of the I-th stage is RT ~ (R
+4) · T, and the minimum interval between the I-th and (I + 1) -th stage equalization units, the delay time of the ghost elimination signal at each tap of the (I + 1) -th stage is (R + 3) · T to (R +
7) It becomes T. By the way, delay circuits 218 and 2 are provided between the second input terminal I ₂ and the second output terminal O ₂ of the equalization unit.
15 is included, and the ghost elimination signal of the equalization unit of the I-th stage is (2I−1) · T before being input to the subtractor 29.
The ghost elimination signal of the (I + 1) th stage equalization unit is delayed by (2I + 1) · T time. As a result, the delay time of the ghost elimination signal from each tap of the I-th stage equalization unit input to the subtractor 29 is (R + 2I−
1) · T ~ (R + 2I + 3) · T, the delay time of the ghost elimination signal from each tap of the equalization unit of the (I + 1) th stage becomes (R + 2I + 4) · T ~ (R + 2I + 8) T, the ghost is equal, etc. It can also be continuously removed at the connection point of the chemical conversion unit. Further, the delay circuit 217 may be omitted and adjustment may be performed by the variable delay circuit 211 in the subsequent stage.

In the embodiment, the minimum delay amount of the variable delay circuit 211 of the equalization units 24 to 21 is T, but the minimum delay amount of the variable delay circuit 211 is not limited to T due to the switch or the like. next,
In the equalization unit 21, In the case of, if the relationship of N = S + M + Q (7) is satisfied, and the delay amount of the variable delay circuit of each equalization unit is minimized, the range of the ghost elimination signal from each equalization unit is , Therefore, the minimum delay between equalization units is T, and ghosts can be continuously removed. Note that the relationship of N> S + M + Q (9) may be used instead of the expression (7), and in this case, it can be adjusted by the variable delay circuit.

Here, in the first embodiment, FIG. FIG. 4 shows the delay circuit 218 in FIG.
Replaces the delay circuit 230 and replaces the delay circuit 217 with the same operation as in FIG. Is the case. FIG. 5 shows a delay circuit 217 in FIG.
, The input signal from the input terminal I2 is
After being delayed by T at 18, the signal is supplied to the digital transversal filter 212, and is added by the adder 231 in the transversal filter. Is the case. FIG. 6 shows the delay circuit 21 in FIG.
7, the number of taps of the transversal filter 212 becomes 8 and the minimum delay amount of the variable delay circuit is 6 · T.
Except that the same operation as in Fig. 1 is performed, Is the case.

Next, the control of each equalization unit in FIG. 1 will be described.
Since it controls the equalization unit memory 214 of the equalization units 21, 22, 23, 24, it is the control circuit 3 and the output d of the differentiation circuit 33.
An output waveform memory 34 that inputs _k , a microprocessor 37 that performs judgment and calculation, a ROM 36 that holds the program thereof, a RAM 35 that holds various data under control, and equalization units 21, 22, 23 , 24 are connected by an address bus 61 and a data bus 62, respectively. Microprocessor
By the control signal from 37 via the address bus 62, the chip selector 38 sends the chip select signal bus 63 to the output waveform memory 34, RAM 35, ROM 36 and the equalization units 21, 22, 23, 24. give. It is shown in the above-mentioned document 3 that the general transversal filter shown in FIG. 14 can be controlled by such a control circuit to remove the ghost. Therefore, the equalization units 21 and 22 according to the present invention will be described below. The control of 23, 24 is shown according to the flow chart shown in FIG.

As for a normal ghost, a larger ghost exists as the delay time becomes shorter. Therefore, a simple control for sequentially finding the maximum ghost and allocating an equalization unit will be described here. However, when the ghosts of large and small sizes are independent of the delay time, the equalization units may be allocated in order from the ghost with the shortest delay time after detecting the number of equalization units in order from the large ghost. Such control can be easily realized by using a microprocessor.

That is, the equalization unit register value i, which indicates controlling the equalization unit 21, is set to 1 (block 70).
1). Next, the output signal y _k of the leading edge portion of the vertical synchronizing signal shown in FIG. 3 is taken into the output waveform memory 34 as the differential value d _k through the differentiating circuit 33 (block 702). Next, the maximum peak of the differential value d _k shown in FIGS. 3B and 3D is detected, and its sample timing is set as the time reference Tφ (block 703). Next, in order to allocate the maximum ghost to the equalization unit 21, the maximum peak value dTφ + K _i (i = 1,2,3, ...) Of the differential value d _k after the sample timing Tφ + 5 is detected (block 704). Then, it sets the delay of the variable delay circuit 211 of the equalization unit 21 to the (K ₁ -4) T (block 705). When i ≧ 2, (K _i −K _i−1 −4) · T
Set to. Specifically, the chip selector 38 outputs a chip select signal to the equalization unit 21, the microprocessor 37 outputs address information indicating the delay amount memory of the equalization unit memory 214, and the microprocessor converts it into a binary number. K ₁ -5 value of the data bus 62
To put out. In this way is set to K ₁ -4 delay amount memory (DL) value is binarized in the equalizing unit memory 214 in the equalization unit 21, based on its value, the variable delay circuit 211 as the delay amount becomes (K ₁ -4) T, the switch S1~S5 are set.

The tap gain modification count register (m) is then set to 1 (block 706). Then, just like block 702,
Taking a differential value d _k of the output signal y _k in the output waveform memory 34 (block 707). Since the acquisition start timings at this time are the same, the maximum peak (time reference) is the sample timing Tφ, as shown in FIG. Next, according to the following equation to correct the each tap gain C ₁ -C ₅ equalization unit 21 (block 708).

C _{j, new} = C _{j, old} + Δsgn dTφ + K ₁ -3 + j (j = 1,2,3,4,5) (14) Here, C _{j, new} is the j-th tap gain after correction, C
_{j, old} is the j-th tap gain before correction, Δ is a small positive correction coefficient, sgn dTφ + K ₁ -3 + j is the sign of the sample value of the differential value d of the output signal y corresponding to the sample timing Tφ + K ₁ -3 + j It is a unique thing. In particular,
The tap gain C _{j, old} read from the equalization unit memory 214 to the microprocessor 37 and the differential value dTφ + K ₁ read from the output waveform memory 34 to the microprocessor 37.
-3 + j and the microprocessor 37 according to the equation (14).
The calculation result C _{j, new} may be written in the equalization unit memory 214.

The tap gain modification count register (m) is then incremented by 1 to 2 in this case (block 709). Next, it is determined whether the correction has been performed a predetermined number of times (N _TAP ) (block 7).
01) If not performed a predetermined number of times, return to block 707 to repeatedly correct the tap gain. If the predetermined number of times has been performed, the equalization unit register (i) is increased by 1 in order to move to the control of the next equalization unit 22, and in this case, 2
Yes (block 711). Next, it is determined whether or not control has been performed for a predetermined number of equalization units (4 in this case) (block 712), and if not, the process returns to block 702 and the next equalization unit (equalization in this case) is performed. Unit 22)
Control. If yes, all controls are stopped (block 713). In this way, the maximum waste of the delay time K ₁ T shown in FIG. 3, g ₁ is removed by the equalization unit 21, and the second magnitude ghost g ₂ of the delay time K ₂ T is It is removed by the equalization unit 22.

The range of the delay time that the equalization units 21 and 22 handle is A ₁ [K ₁ T-2T, K ₁ T + 2 shown in FIG. 3 (c).
T], A ₂ [K ₂ T−2T, K ₂ T + 2T]. Further, when there are two ghosts, the equalization units 23 and 24 are essentially unnecessary, but even if they exist, the maximum peak of the differential value d of the output signal y (in this case, the peak of noise) is generated. Since equalization is performed in each of the centers, no problem occurs in the ghost removal performance.

The length of the variable delay line may be the maximum length of the delay time between the adjacent ghosts, and in this embodiment, the maximum length of 143.T = (34 × 3 + 31 + 3 + 4 + 3) T ghosts can be removed. it can.

The present invention is effective even if a RAM as shown in FIG. 8 is used as the variable delay circuit. Although it is well known that RAM is used as a variable delay circuit,
The 2112 is repeatedly counted by the amount corresponding to the delay amount, the first half time of each counter output is assigned to the read of RAM2112, the second half time is assigned to the write, and the output data of RAM2111 is assigned before the end of the read time. Since the first latch circuit 2114 latches and synchronizes with the clock, the latch circuit 2115 may subsequently latch in synchronization with the clock. The control generation circuit 2113 generates the read / write pulse of the RAM 2111 and the clock of the second latch circuit 2115. The respective timings in FIG. 8 are shown in FIG.

The ghost elimination can be effectively performed by the digitized ghost elimination device in which a plurality of digital equalization circuits (equalization units) having the same circuit configuration as described above are connected.

FIG. 10 shows another embodiment of the digital equalization circuit. This only reverses the connection between the digital transversal filter and the variable delay circuit in FIG. 1, except that the variable delay circuit is used to delay the transversal filter of the equalization unit connected to the rear side. The operation and effect are similar to those of the embodiment shown in FIG.

FIG. 11 shows another embodiment of the digital equalization circuit, which has variable delay circuits on both sides of the digital transversal filter. This also has the same operation and effect as the embodiment of FIG. 1 except that the first variable delay circuit is used for delaying the transversal filter of the equalization unit connected to the rear side.

Further, it is clear that one of the two delay circuits may be a fixed delay circuit.

Further, the number of taps of the digital transversal filter in each unit of the digital equalization circuit according to each embodiment of the present invention, the delay amount of the variable delay circuit, and the delay range thereof are not particularly limited.

Further, the present invention does not limit the connection method of each equalization unit, and for example, digital equalization circuits may be connected in parallel as shown in FIG.

That is, the equalization units 21, 22, 23, 24 are commonly connected to the _first input terminal I ₁ . Each equalization unit 24,23,22,21
The output of the subtractor 29 is input to the first input terminal I ₁ of the. The outputs from the _second output terminals O ₂ of the equalization units 21, 22, 23 are the second input terminals I ₂ of the equalization units 22, 23, 24, respectively.
And the output of the second output terminal O ₂ of the equalization unit 24 is input to one terminal of the subtractor 29.

In this case, the delay amount of each variable delay circuit of each equalization unit 21, 22, 23, 24 is set according to the ghost delay time. As a result, in each equalization unit 21, 22, 23, 24, an output for removing a ghost of a delay time based on the delay amount of each variable delay circuit is created. This output is added in each equalization unit and given from the equalization unit 24 to the subtractor 29. Thus, the subtractor 29 subtracts the output of the equalization unit 24 from the video signal input via the input terminal 1 to output the ghost-removed output to the output terminal 5.

Further, in the digitized ghost elimination device, as shown in FIG.
As shown in FIG. 12, the equalization unit is feedback-connected as a whole, but the present invention is effective even if it is a feedforward connection.

2 and 12, the present invention is effective even in a waveform equalization mode in which the main signal also passes through the equalization unit.

[Effects of the Invention] As described above, according to the present invention, the number of taps is low as a whole, the cost is low, the hardware is not so complicated, and there is little remaining data, and a television with good S / N is provided. A sufficiently practical digitized ghost elimination device that can obtain a signal is obtained. Since an input weighted digital transversal filter is used, each first adder can be configured as two inputs and one output, which is advantageous in that the configuration is easy. Furthermore, by adding a digital equalization circuit, it is possible to obtain a device with high ghost removal performance that can also remove grandchild ghosts.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital equalization circuit according to the present invention, and FIG. 2 is a block diagram showing a digitized ghost elimination device constructed by using the digital equalization circuit of the embodiment of FIG. FIG. 3 is a diagram for explaining a ghost removing operation, FIG. 4 is a block diagram showing a digital equalization circuit according to another embodiment of the present invention, and FIG. 5 is another embodiment of the present invention. Block diagram showing a digital equalization circuit,
FIG. 6 is a block diagram showing a digital equalization circuit according to another embodiment of the present invention, FIG. 7 is an operation flow chart for explaining the operation of the embodiment, and FIG. 8 is a variable delay circuit of the digital equalization circuit. FIG. 9 is a circuit diagram showing another example, FIG. 9 is a timing diagram for explaining the operation of FIG. 8, and FIG. 10 is a block diagram showing a digital equalization circuit according to another embodiment of the present invention.
FIG. 12 is a block diagram showing a digital equalization circuit according to another embodiment of the present invention, FIG. 12 is a block diagram showing another digitized ghost elimination device, and FIG. 13 is a block diagram of a conventional ghost elimination device. FIG. 14 is a circuit diagram of a conventional digital equalization circuit. I ₁ ...... First input terminal, I ₂ ...... Second input terminal, O ₁
...... First output terminal, O ₂ ...... Second output terminal, 29 ......
Subtractors, 21, 22, 23, 24 ... Digital equalization circuit (equalization unit).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-56-147572 (JP, A) JP-A-59-214387 (JP, A) Practical application Sho-55-5604 (JP, U)

Claims (3)

[Claims] 1. A first input terminal to which a first signal is input, a variable delay circuit that delays the first signal so that the delay time can be changed, and an input terminal to which an output of the variable delay circuit is applied. A plurality of tap coefficient units connected in common, a plurality of first adders that add the outputs of the plurality of tap coefficient units, and the output of the tap coefficient units is delayed by a unit time, and the first stage of the next stage is sequentially arranged. A plurality of unit time delay elements input to the adder of
An input weighted digital signal that outputs a signal for equalizing the first signal within an equalization range based on the delay amount of the variable delay circuit with reference to the position on the time axis of the signal input to the input terminal of A transversal filter, a memory that stores an externally set tap gain coefficient of the tap coefficient unit of the digital transversal filter and a delay time in the variable delay circuit, and derives an output of the variable delay circuit. A first output terminal capable of providing a signal delayed by a predetermined time with respect to the first signal input to the first input terminal to the outside, and an output from the first output terminal. A second input capable of inputting a second signal whose waveform is equalized in a predetermined equalization range which is different from the equalization range of the digital transversal filter and which does not overlap. A second adder for taking a sum of an output of the digital transversal filter and the second signal input to the second input terminal; and a second adder for deriving an output of the second adder. A digital equalization circuit having two output terminals. 2. A first input terminal to which a first signal is input, a variable delay circuit which delays the first signal so that the delay time can be changed, and an input terminal to which the first signal is applied. A plurality of tap coefficient units connected in common, a plurality of first adders for adding the outputs of the plurality of tap coefficient units, an output of the tap coefficient units with a unit time delay, and the first unit of the next stage in sequence. A plurality of unit time delay elements input to the adder are provided, and the first signal is equalized within a predetermined equalization range based on the position on the time axis of the signal input to the first input terminal. Input-weighted digital transversal filter for outputting a signal for outputting, and a memory for storing a tap gain coefficient of the tap coefficient unit of the digital transversal filter and a delay time in the variable delay circuit, which are set from the outside. A first output terminal for deriving an output of the variable delay circuit, the first output terminal being capable of giving a signal delayed by a predetermined time with respect to the first signal input to the first input terminal to the outside. And a second input capable of inputting a second signal whose waveform output is equalized in a predetermined equalization range which is different from the equalization range of the digital transversal filter and does not overlap the output from the first output terminal. A terminal, a second adder that sums the output of the digital transversal filter and the second signal input to the second input terminal, and a second adder that derives the output of the second adder A digital equalization circuit having two output terminals. 3. The digital device according to claim 1 or 2, wherein the second adder is also used as one of the first adders. Circuit.