JPH0795820B2 - Digitized ghost elimination device - Google Patents

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ghost eliminating device for automatically eliminating television ghosts, and more particularly to a digitizing ghost eliminating device for digitally performing ghost eliminating.

[0003]

2. Description of the Related Art Apparatuses for automatically and digitally removing television ghosts using a digital equalization circuit are known in the prior art. An example thereof is shown in FIG.

For details of this configuration and operation, refer to Document 1 (Murakami et al., "Digitalized Ghost Automatic Erasing Device", Technical Report of IEICE, EMCJ78-37, November 1978).
However, the outline is shown below. This device is all digitized, and a digital video signal containing a ghost is input to a digital equalization circuit 2 via an input terminal 1. This digital equalization circuit 2 is shown in FIG.
4, the N + M unit delay elements 201
(Delay time T [sec]), N + M + 1 tap coefficient units 202 (digital multipliers), and an adder 203 and a tap gain memory 204 for adding the outputs of the respective tap coefficient units.
It consists of and. The tap coefficient (C-M to CN) of this tap coefficient unit is set to an appropriate value by the control circuit 3 so that the ghost-removed digital video signal is
It is output to the output terminal 5.

The reference signal for removing the ghost is the differential waveform (b) of the trailing edge portion (a) of the vertical synchronizing signal shown in FIG. 3, and the ghost detection circuit 32 uses this differential operation (differential operation can be substituted. ) Is performed and the peak corresponding to the trailing edge of the trailing edge of the vertical synchronizing signal is set to time reference 0, and each peak di after this time reference is detected.

[0006] The sign of the differential value di corresponds to the positive / negative of the residual ghost having the delay time iT. Therefore, the tap gain correction circuit 31 uses this differential value di to sequentially correct each tap gain according to the following equation.

Ci, new = Ci, old −Δsgn (di) (2) (i = −M to N, i ≠ 0) where Ci, old is the tap gain before correction and Ci, new is after correction. Is a tap gain, Δ is a small positive correction coefficient,
Equation (2) is widely known as the Zero Forcing method.
The center tap coefficient C0 is fixed to C0 = 1 ... (3). Every time the vertical sync signal arrives (1/60
(Seconds), the ghost is removed by performing this sequential correction. The sequence controller 4 controls the sequence of the control circuit 3 described above, and for example, R
It can be configured using OM.

There is also known a device for eliminating a ghost by a combination of a fixed delay circuit and a transversal filter (Japanese Patent Laid-Open No. 56-158579).

[0009]

However, in the conventional digitized ghost elimination device as described above, a large number of coefficient multipliers (multipliers) are required to perform sufficient ghost elimination, and those coefficients are required. Since a general-purpose digital multiplier used as a container is expensive and its scale is large (one multiplier is one IC), a practical ghost removing device could not be obtained. On the other hand, although the analog equalizing circuit using the CCD has been put to practical use as a ghost removing device, it has a problem in terms of remaining unerased and S / N.

To describe the above problem in a little more detail, even if the digital IC technology, which has made rapid progress in recent years, is used, one IC can integrate only at most about 10 multipliers. This is because a coefficient multiplier for the ghost elimination transversal filter requires an 8-bit × 8-bit multiplier, and at the latest technology level, a 16-bit × 16-bit CMOS multiplier is 3.5 mm × 5.0 mm (Reference 2: Yosh
io Kaji "A45ns 16x16 CMOS Multiplier" ISSCC
84 WPM8.1), which means a practical chip size of 7 mm x 7
On the mm IC chip, the 8bit × 8bit CMOS multiplier is This is because about 9 can be integrated.

The ghost delay range that can be removed by the N-tap transversal filter is NT (T is a sampling period, T = 1/3 fsc, 1/4 fsc, (fsc (color subcarrier frequency = 3.58 MHz)). , N
= 10 and T = 70 to 100 ns, NT = 0.7 to 1 μs (5), which is insufficient as a ghost removing transversal filter. Therefore, the equalization circuit used in the ghost elimination device that has already been put into practical use is as described in Reference 3 (Murakami et al. “Ghost Clean System” Toshiba Review No. 1.38 No. 7 June 1983). Charge Coupled Device) A transversal filter was used. However, since this is an analog signal processing device, the linearity of the coefficient unit (multiplier) and the total S / N were particularly insufficient. When viewed as a ghost removing device, this drawback has led to an increase in the amount of ghost remaining on the screen and a decrease in S / N.

Further, the technique disclosed in Japanese Patent Laid-Open No. 158579/56 has a problem that a grandchild ghost remains even if the ghost is removed in the primary ghost removal stage.

The present invention has been made in view of the above problems, and does not require a large number of coefficient units or the like, and therefore can be practically used in terms of cost and hardware. It is an object to provide a ghost removing device.

[Constitution of Invention]

[0015]

According to a first aspect of the present invention, there is provided a digitized ghost elimination device having a first input terminal to which a first signal is inputted and a delay time which can be changed.
Of the variable delay circuit, a plurality of tap coefficient units to which the output of the variable delay circuit is applied and whose input terminals are commonly connected, and a plurality of first additions for adding the outputs of the plurality of tap coefficient units And a plurality of unit time delay elements for delaying the output of the tap coefficient unit by a unit time and sequentially inputting to the first adder of the next stage, and the time of the signal input to the first input terminal. Input-weighted digital transversal filter for outputting a signal for equalizing the first signal in an equalization range based on the delay amount by the variable delay circuit with reference to the position on the axis, and this digital transversal filter A memory for storing a tap gain coefficient of the tap coefficient unit and a delay time in the variable delay circuit, and an output of the variable delay circuit, the first input A first output terminal capable of giving a signal delayed by a predetermined time to the first signal input to the child, and an output from the first output terminal to equalize the digital transversal filter. A second input terminal capable of inputting a second signal for waveform equalization in a predetermined equalization range different from the range; an output of the digital transversal filter and the second input terminal; An equalization unit comprising a second adder for summing with a second signal and a second output terminal for deriving the output of the second adder; and at least one equalization unit Using an input signal as the first signal to the first input terminal of the equalization unit in the first stage, the output from the first output terminal of the equalization unit in each stage is used as the equalization unit in the next stage. To the first input terminal of And the output from the second output terminal of the equalization unit of each stage is supplied as the second signal to the second input terminal of the equalization unit of the previous stage, and the equalization of the first stage is performed. The unit further comprises connecting means for obtaining an equalized output signal from the second output terminal of the unit, and computing means for obtaining the tap gain coefficient and the delay time to be stored in each memory of the equalizing unit of each stage. According to a second aspect of the present invention, there is provided a digitized ghost elimination device having a first input terminal to which a first signal is input and a variable delay for delaying the first signal such that the delay time can be changed. A circuit, and a plurality of tap coefficient units to which the first signal is applied and whose input terminals are commonly connected,
A plurality of first adders for adding the outputs of the plurality of tap coefficient units, and a plurality of unit time delay elements for delaying the outputs of the tap coefficient units by a unit time and sequentially inputting them to the first adder of the next stage Of the input weighted type that outputs a signal for equalizing the first signal within a predetermined equalization range with reference to the position on the time axis of the signal input to the first input terminal. A digital transversal filter, a memory for storing a tap gain coefficient of the tap coefficient unit of the digital transversal filter and a delay time in the variable delay circuit, and a device for deriving an output of the variable delay circuit, A first output terminal capable of giving a signal delayed by a predetermined time to the first signal input to the first input terminal; and an output from the first output terminal as the digital signal. Second to waveform equalization in different predetermined equalization range equalization range of the transversal filter
A second input terminal capable of receiving the second signal, a second adder that sums the output of the digital transversal filter and the second signal input to the second input terminal, and An equalization unit having a second output terminal for deriving the output of the second adder; and at least two equalization units, wherein the first input terminal of the equalization unit at the first stage is the first input terminal. An input signal is supplied as a signal of, and the output from the first output terminal of the equalization unit of each stage is supplied to the first input terminal of the equalization unit of the next stage as the first signal, The output from the second output terminal of the equalization unit is supplied to the second input terminal of the equalization unit of the preceding stage as the second signal, and from the second output terminal of the equalization unit of the first stage. Connection means for obtaining an equalized output signal; And calculating means for calculating said tap gain coefficient and the delay time is stored in the memory of the equalization unit is obtained by including a.

[0016]

In the present invention, the variable delay circuit of the digital equalization circuit adjusts the time difference between the ghost-containing television signal and the ghost signal. A plurality of ghosts having different delay times are removed by an input weighted digital transversal filter of each digital equalization circuit. Second
The adder of 1 adds the output of the digital transversal filter and the second output of the other digital equalization circuit and outputs the result. Thus, from the first stage digital equalization circuit,
A ghost cancellation signal is generated for removing a plurality of ghosts having a predetermined delay time. The subtractor subtracts the ghost cancellation signal from the input television signal to output the ghost-removed output.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digitized ghost removing apparatus according to the present invention.

In FIG. 1, the digital video signal containing the ghost is input to one of the subtractors 29 in the equalization circuit. The output of the subtracter 29 is input to the output terminal 5 and the differentiating circuit 33 in the control circuit 3 and also to the first input terminal I1 of the digital equalizing circuit (hereinafter referred to as the equalizing unit) 21, Equalization unit 2i (i = 1,
The first output terminal O1 of 2, 3) is connected to the equalization unit 2j.
(J = i + 1, i = 1, 2, 3) first input terminal I1
Connect to. The second input terminal I2 of the equalization unit 24
Is grounded and 0 is input. The second output terminal O2 of the equalization unit 2i (i = 4, 3, 2) is
The second input terminal I2 of the equalization unit 2j (j = i-1, i = 4, 3, 2) is connected to the second input terminal I2 of the equalization unit 21.
The output from the output terminal O2 of the above is input to the other input terminal of the subtractor 29 as a ghost canceling signal.

The equalizing units 21 to 24 have the same structure, and the structure is shown in FIG. Equalization unit 2
The first first input terminal I1 is input to the variable delay circuit 211, and is connected to one input terminal of the switch S1 and the other input terminal of the switch S1 via the delay element D1 having the delay amount T. The output terminal of switch S1 is switch S2
Via the input terminal of and the delay element D2 having a delay amount of 2T,
It is connected to the other input terminal of the switch S2. Hereafter, with the same repetition as this, S2, D3, S3, D4, S4, D
5 and S5 are connected. Here, each delay element Di is composed of a shift register or a latch in which i pieces are connected in series.

Therefore, the switch Si (i = 1, ..., 5)
Is set by the value of the delay amount memory DL of the equalization unit memory 214, thereby forming a variable delay circuit that gives an arbitrary delay (T step) of 0 to 31T.
The output of the switch S5 is input to the delay circuit 216.
The purpose of the delay circuit 216 is to align the delay times of the signals given by the switches S1 to S5 with the clock time T.

The output of the delay circuit 216 is the variable delay circuit 2
11 is connected to one input of a digital multiplier 2122 which is each tap coefficient unit of the weighting circuit 220 in the digital transversal filter 212, and the other input of the digital multiplier 2122 is connected to the equalization unit memory 214. Of tap gain memories C1 to C5. The output of the multiplier 2122 is input to the adder of each tap of the delay circuit with tap 221, and each input signal is delayed and added repeatedly and output to the adder 213. That is, the output of the final stage is the output of the digital filter having the variable tap number of 5 and having the delay amount given by the variable delay circuit 211 as an offset and given by the transversal filter 212.

The output of the transversal filter 212 is added by the adder 213 with the output signal of the equalization unit 22 obtained from the second input terminal I2 of the equalization unit 21 and the signal delayed by the delay circuit 218, It is input to the delay circuit 215. These two delay circuits 215, 2
The purpose of 18 is to align the delay time of the input signal from the input terminal and the output signal from the transversal filter 212 with the clock time T.

The output from the delay circuit 215 is connected to the second output terminal O2 of the equalization unit 21. That is,
The output signal obtained from the second output terminal O2 of the equalization unit 21 is equal to each equalization unit 24, 23, 22, 21.
And becomes a ghost elimination signal generated in
9 to the other input terminals.

Also, the variable delay circuit 2 of the equalization unit 21.
The output of 11 becomes the input of the delay circuit 217, is delayed for 2T time, and is output to the first output terminal O1. The first output terminal O1 of the equalization unit 21 is connected to the first input terminal I1 of the equalization unit 22, and the output of the first output terminal O1 of the equalization unit 21 is connected to the output of the variable delay circuit 211. By delaying the output by 2T time, the delay circuit 216 and the delay circuit 215 of the variable delay circuit of the equalization unit 22 are delayed by the delay circuit 218 of the equalization unit 21 and the digital transversal filter 212 of the equalization unit 21. The maximum time delay (5T time) can be compensated, and when one or more equalization units are connected, the minimum tap interval at the connection point can be T.

That is, from the output of the subtractor 29, the delay time of the ghost elimination signal from each tap of the equalization unit at the I-th stage is RT to (R + 4) · T, and the delay time at the I-th stage is (I + 1).
If the minimum interval between equalization units in the second stage is (I + 1)
The delay time of the ghost removal signal of each tap in the stage is (R +
3) · T to (R + 7) T. By the way, delay circuits 218 and 215 are provided between the second input terminal I2 and the second output terminal O2 of the equalization unit, and the ghost elimination signal of the I-th equalization unit is sent to the subtracter 29. It is delayed by (2I-1) · T time until it is input (I +
1) The ghost elimination signal of the equalization unit at the second stage is (2I
+1) · T time is delayed. As a result, the delay time of the ghost removal signal from each tap of the I-th stage equalization unit input to the subtractor 29 is (R + 2I−1) · T to (R
+ 2I + 3) · T, and the delay time of the ghost elimination signal from each tap of the (I + 1) th stage equalization unit is
(R + 2I + 4) · T to (R + 2I + 8) T, and the ghost can be continuously removed even at the connection point of the equalization unit. Alternatively, the delay circuit 217 may be omitted and adjustment may be performed by the variable delay circuit 211 in the subsequent stage.

In the embodiment, the minimum delay amount of the variable delay circuit 211 of the equalization units 24 to 21 is T, but the minimum delay amount of the variable delay circuit 211 is T by a switch or the like.
Not necessarily. Next, in the equalization unit 21, the maximum delay amount of the transversal filter: N · T, the minimum delay amount of the variable delay circuit: S · T, the delay amount between the input terminal I2 and the output terminal O2: M · T (6) Delay amount between variable delay circuit and output terminal O1: Q · T Delay amount between adder 213 and output terminal O2: In case of U · T, each equalization unit is satisfied if the relation of N = S + M + Q (7) is satisfied. When the delay amount of the variable delay circuit is minimized, the range of the ghost elimination signal from each equalization unit is calculated by the subtractor 29 in the first equalization unit: (S + U + 1) · T to (S + U + N) · T second. Equalization unit: (S + U + N + 1) · T to (S + U + 2N) · T (8) kth equalization unit: {S + U + (k−1) N + 1} · T to (S + U + kN) · T, which is the minimum between equalization units The delay is T, and the ghost is continuously removed. It can be. Note that the relationship of N> S + M + Q (9) may be used instead of the expression (7), and in this case, it can be adjusted by the variable delay circuit.

2 shows the case of N = 5 S = 1 M = 2 (10) Q = 2 U = 1 in the first embodiment, and FIG. 4 shows the delay circuit 218 in FIG. 2 replaces the delay circuit 230 and operates in the same manner as in FIG. 2 except that the delay circuit 217 is eliminated, and N = 5 S = 1 M = 4 (11) Q = 0 U = 1. In FIG. 5, the delay circuit 217 in FIG. 2 is eliminated, and the input signal from the input terminal I2 is
After being delayed by T at 18, the signal is supplied to the digital transversal filter 212 and is added by the adder 231 in the transversal filter, and the same operation as in FIG. 2 is performed, and N = 5 S = 1 M = 4 (12) In the case of Q = 0 U = 0. 6 is a circuit diagram of the delay circuit 217 in FIG.
Is eliminated, the number of taps of the transversal filter 212 becomes eight, and the minimum delay amount of the variable delay circuit is 6.
The same operation as that of FIG. 2 is performed except that T is set, and N = 8 S = 6 M = 2 (13) Q = 0 U = 1.

Next, the control of each equalization unit in FIG. 2 will be described. It is the control circuit 3 that controls the equalization unit memory 214 of the equalization units 21, 22, 23 and 24, and the output waveform memory 34 that receives the output dk of the differentiating circuit 33 as input and the determination and calculation. Microprocessor 37
And a ROM 36 holding the program, a RAM 35 holding various data under control, and the equalization unit 2
1, 22, 23, and 24 are address buses 61, respectively.
And the data bus 62. In response to a control signal from the microprocessor 37 via the address bus 62, the chip selector 38 causes the output waveform memory 34, R
AM35, ROM36 and equalization units 21, 22, 2
A chip select signal is applied to the chips 3 and 24 by the chip select signal bus 63. The fact that the control circuit as described above can remove the ghost by controlling the general transversal filter shown in FIG. 14 is described in the above-mentioned Document 3. Therefore, the equalization units 21, 22, 22 according to the present invention will be described below. The control of 23 and 24 is shown according to the flow chart shown in FIG.

Since a normal ghost has a larger ghost as the delay time becomes shorter, a simple control for sequentially finding the maximum ghost and allocating an equalization unit will be described. However, when the ghosts of large and small sizes are independent of the delay time, the equalization units may be allocated in order from the ghost with the shortest delay time after detecting the number of equalization units in order from the large ghost. Such control can be easily realized by using a microprocessor.

That is, the equalization unit register value i indicating that the equalization unit 21 is controlled is set to 1 (block 701). Next, the output signal yk at the leading edge of the vertical synchronizing signal shown in FIG.
It is loaded into the output waveform memory 34 as k (block 7
02). Next, the maximum peak of the differential value dk shown in FIGS. 3B and 3D is detected, and its sample timing is set as the time reference Tφ (block 703). Next, in order to allocate the maximum ghost to the equalization unit 21, the maximum peak value dTφ + of the differential value dk after the sample timing Tφ + 5.
Ki (i = 1, 2, 3, ...) Is detected (block 70).
4). Next, the delay amount of the variable delay circuit 211 of the equalization unit 21 is set to (K1-4) T (block 70).
5). When i ≧ 2, set to (Ki −Ki−1 −4) · T. Specifically, the chip selector 38 outputs a chip select signal to the equalization unit 21, the microprocessor 37 outputs address information instructing the delay amount memory of the equalization unit memory 214, and the microprocessor converts it into a binary number. The value of K1-5 is output to the data bus 62. In this way, the delay amount memory (DL) value in the equalization unit memory 214 in the equalization unit 21 is set to the binary digitized K1-4, and the delay of the variable delay circuit 211 is set based on the value. The switches S1 to S5 are set so that the amount becomes (K1-4) T.

Next, the tap gain modification count register (m) is set to 1 (block 706). Next, block 7
Just like 02, the differential value dk of the output signal yk is loaded into the output waveform memory 34 (block 707). Since the capture start timings at this time are the same, the maximum peak (time reference) is the sample timing Tφ, as shown in FIG. Next, each tap gain C of the equalization unit 21
Correction of 1 to C5 is performed according to the following equation (block 70).
8).

Cj, new = Cj, old + Δsgn dTφ + K1-3 + j (j = 1, 2, 3, 4, 5) (14) where Cj, new is the j-th tap gain after correction, Cj,
old is the j-th tap gain before correction, Δ is a small positive correction coefficient, and sgn dTφ + K1-3 + j is the sign of the sample value of the differential value d of the output signal y corresponding to the sample timing Tφ + K1-3 + j. Is. Specifically, the tap gain Cj, old read from the equalization unit memory 214 to the microprocessor 37 and the differential value dTφ + K1-3 + j read from the output waveform memory 34 to the microprocessor 37 are calculated according to the equation (14). , The calculation result Cj,
It suffices to write new in the equalization unit memory 214.

Next, the tap gain correction frequency register (m)
Is incremented by 1 to 2 in this case (block 70
9). Next, it is determined whether the correction has been performed a predetermined number of times (NTAP) (block 701). If the correction has not been performed the predetermined number of times, the process returns to the block 707 to repeatedly correct the tap gain. If the predetermined number of times has been performed, the equalization unit register (i) is moved to control the next equalization unit 22.
Is increased by 1 to 2 in this case (block 71
1). Next, it is judged whether or not control has been performed for a predetermined number of equalization units (4 in this case) (block 712). If not, the process returns to block 702 and the next equalization unit (equalization in this case) is performed. The unit 22) is controlled.
If yes, all controls are stopped (block 713). In this way, the delay time K1 T shown in FIG.
The maximum ghost g1 of is removed by the equalization unit 21,
The second magnitude ghost g2 of the delay time K2 T is removed by the equalization unit 22.

The range of the delay time which the equalization units 21 and 22 are responsible for is A1 [K1 T shown in FIG. 3 (c).
-2T, K1 T + 2T], A2 [K2 T-2T, K2 T
+ 2T]. Further, in the case of such two ghosts, the equalization units 23 and 24 are essentially unnecessary,
Even if they exist, since equalization is performed around the maximum peak of the differential value d of the output signal y (in this case, the peak of noise), no problem occurs in the ghost removal performance.

The length of the variable delay line may be the maximum length of the delay time between adjacent ghosts, and in this embodiment, the maximum length is 143 · T = (34 × 3 + 31 + 3 + 4).
+3) Ghosts up to T can be removed.

The present invention is also effective when a RAM as shown in FIG. 8 is used as the variable delay circuit. In addition, R
Although it is known to use AM as a variable delay circuit, the address counter 2112 is repeatedly counted by an amount corresponding to the delay amount, the first half time of each counter output is assigned to the read of the RAM 2112, and the second half time is written. Assigned to the RA before the end of that lead time
The output data of M2111 is latched by the first latch circuit 2114 and synchronized with the clock; therefore, the latch circuit 2115 may be subsequently latched in synchronization with the clock. R
The control generation circuit 2113 generates the read / write pulse of AM2111 and the clock of the second latch circuit 2115. Each timing of FIG. 8 is shown in FIG.

The ghost elimination can be effectively performed by the digitized ghost elimination device in which a plurality of digital equalization circuits (equalization units) having the same circuit configuration as described above are connected.

FIG. 10 shows another example of the digital equalization circuit. This is because the connection between the digital transversal filter and the variable delay circuit in FIG. 2 is simply reversed, and the operation other than the case where the variable delay circuit is used to delay the transversal filter of the equalization unit connected to the rear side is performed. And the effect is similar.

FIG. 11 shows another example of the digital equalization circuit, which has variable delay circuits on both sides of the digital transversal filter. This also has the same operation and effect except that the first variable delay circuit is used for delaying the transversal filter of the equalization unit connected to the rear side.

It is also clear that one of the two delay circuits may be a fixed delay circuit.

Further, the number of taps of the digital transversal filter in each unit of the digital equalization circuit in FIG. 1, the delay amount of the variable delay circuit and the delay range thereof are not particularly limited.

FIG. 12 is a block diagram showing a digitized ghost removing apparatus according to another embodiment of the present invention. Figure 1
2, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The present invention does not limit the connection method of each equalization unit, and digital equalization circuits may be connected in parallel.

That is, as shown in FIG. 12, the equalization units 21, 22, 23 and 24 are commonly connected to the first input terminal I1. Each equalization unit 24, 23, 22,
The output of the subtractor 29 is input to the first input terminal I1 of the input terminal 21. The outputs from the second output terminals O2 of the equalization units 21, 22, 23 are respectively equalization units 22, 23, 24.
Is input to the second input terminal I2 of the equalizer unit 24 and the output of the second output terminal O2 of the equalization unit 24 is input to one terminal of the subtractor 29. In the embodiment configured in this way, the delay amount of each variable delay circuit of each equalization unit 21, 22, 23, 24 is set according to the ghost delay time. As a result, each equalization unit 21, 22, 23, 2
In 4, the output for removing the ghost of the delay time based on the delay amount of each variable delay circuit is created. This output is added in each equalization unit and given from the equalization unit 24 to the subtractor 29. In this way, the subtractor 29 subtracts the output of the equalization unit 24 from the video signal input via the input terminal 1 to output the output from which the ghost is removed to the output terminal 5.

As described above, also in this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained.

Further, in the digitized ghost elimination device of the present invention, as shown in FIGS. 1 and 12, the equalization unit is feedback-connected as a whole, but the present invention is effective even if it is a feed-forward connection. is there.

1 and 12, even in the waveform equalization mode in which the main signal also passes through the equalization unit,
The present invention is effective.

[0047]

As described above, according to the present invention, the number of taps as a whole is small, the cost is low, the hardware is not so complicated, and the television with less remaining unerased and good S / N is provided. A sufficiently practical digitized ghost elimination device that can obtain a signal is obtained. It uses an input weighted digital transversal filter,
Each of the first adders can be configured as two inputs and one output, which is advantageous in that the configuration is easy. Furthermore, by adding a digital equalization circuit, it is possible to obtain a device with high ghost removal performance that can also remove grandchild ghosts.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digitized ghost removing apparatus according to the present invention.

2 is a block diagram showing a specific configuration of a digital equalization circuit in FIG.

FIG. 3 is a diagram for explaining an operation of removing a ghost.

FIG. 4 is a block diagram showing another digital equalization circuit.

FIG. 5 is a block diagram showing another digital equalization circuit.

FIG. 6 is a block diagram showing another digital equalization circuit.

FIG. 7 is an operational flowchart for explaining the operation of the embodiment of FIG.

FIG. 8 is a circuit diagram showing another example of the variable delay circuit of the digital equalization circuit.

9 is a timing diagram for explaining the operation of FIG.

FIG. 10 is a block diagram showing another digital equalization circuit.

FIG. 11 is a block diagram showing another digital equalization circuit.

FIG. 12 is a block diagram showing another embodiment of the digitized ghost elimination device of the present invention.

FIG. 13 is a block diagram of a conventional ghost removing device.

FIG. 14 is a circuit diagram of a conventional digital equalization circuit.

[Explanation of symbols]

I1 ... 1st input terminal I2 ... 2nd input terminal O1 ... 1st output terminal O2 ... 2nd output terminal 29 ... Subtractor 21, 22, 23, 24 ... Digital equalization circuit (equalization unit)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-59-214387 (JP, A) JP-A-56-147572 (JP, A) JP-A-56-158579 (JP, A)

Claims (2)

[Claims] 1. A first input terminal to which a first signal is input
And a variable that delays the first signal so that the delay time can be changed.
The delay circuit and the output of the variable delay circuit are given and the input terminals are connected in common
A plurality of tap coefficient units,
A plurality of first adders for adding outputs, the tap coefficient device
Delays the output of the unit by a unit time and sequentially adds the first addition in the next stage.
A plurality of unit time delay elements for input to the
Based on the position on the time axis of the signal input to the input terminal of
Then, in the equalization range based on the delay amount by the variable delay circuit
An input input that outputs a signal for equalizing the first signal.
Double-type digital transversal filter and the tap of the digital transversal filter
In the tap gain coefficient of the coefficient unit and the variable delay circuit
A memory for storing a delay time, and a means for deriving an output of the variable delay circuit,
At a predetermined time with respect to the first signal input to the first input terminal
First output that can give a signal delayed for a period of time to the outside
Terminal and the output from the first output terminal
A predetermined equalization range different from the equalization range of the Sversal filter
A second signal that can be input with a second signal for waveform equalization
An input terminal, an output of the digital transversal filter and the
The sum with the second signal input to the second input terminal is calculated.
And an equalization unit having a second output terminal for deriving the output of the second adder, and at least two equalization units ,
The first signal is applied to the first input terminal of the equalization unit.
To provide an input signal to the first equalizer unit of each stage.
The output from the output terminal is connected to the first of the equalization unit of the next stage.
It is supplied to the input terminal as the first signal,
The output from the second output terminal of the digitization unit
To the second input terminal of the digitalization unit as the second signal.
Feeding, and the like from the second output terminal of the equalization unit of the first stage
Connection means for obtaining the converted output signal, and the memory for storing in each memory of the equalization unit of each stage.
Digitized ghost elimination of the-up gain factor and calculating means for calculating said delay time, and characterized by including a
apparatus. 2. A first input terminal to which a first signal is input
And a variable that delays the first signal so that the delay time can be changed.
A delay circuit and a duplication circuit to which the first signal is applied and whose input terminals are commonly connected.
Number of tap coefficient multipliers, adding the outputs of the tap coefficient multipliers
A plurality of first adders for calculating the output of the tap coefficient unit
Input to the first adder of the next stage sequentially with a unit time delay
A plurality of unit time delay elements, and the first input terminal
Predetermined based on the position on the time axis of the signal input to the child
Signal for equalizing the first signal in the equalization range of
Input weighted digital transversal fill
And the taps of this digital transversal filter
In the tap gain coefficient of the coefficient unit and the variable delay circuit
A memory for storing a delay time, and a means for deriving an output of the variable delay circuit,
At a predetermined time with respect to the first signal input to the first input terminal
First output that can give a signal delayed for a period of time to the outside
Terminal and the output from the first output terminal
A predetermined equalization range different from the equalization range of the Sversal filter
A second signal that can be input with a second signal for waveform equalization
An input terminal, an output of the digital transversal filter and the
The sum with the second signal input to the second input terminal is calculated.
And an equalization unit having a second output terminal for deriving the output of the second adder, and at least two equalization units ,
The first signal is applied to the first input terminal of the equalization unit.
To provide an input signal to the first equalizer unit of each stage.
The output from the output terminal is connected to the first of the equalization unit of the next stage.
It is supplied to the input terminal as the first signal,
Said equal the output from the second output terminal preceding the reduction unit
To the second input terminal of the digitalization unit as the second signal.
From the second output terminal of the equalization unit in the first stage
Connection means for obtaining the converted output signal, and the memory for storing in each memory of the equalization unit of each stage.
Digitized ghost elimination of the-up gain factor and calculating means for calculating said delay time, and characterized by including a
apparatus.