JPH07107911B2 - Semiconductor device inspection method - Google Patents
Semiconductor device inspection methodInfo
- Publication number
- JPH07107911B2 JPH07107911B2 JP63043853A JP4385388A JPH07107911B2 JP H07107911 B2 JPH07107911 B2 JP H07107911B2 JP 63043853 A JP63043853 A JP 63043853A JP 4385388 A JP4385388 A JP 4385388A JP H07107911 B2 JPH07107911 B2 JP H07107911B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- semi
- finished
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の検査方法に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method for inspecting a semiconductor device.
(従来の技術) 一般に、半導体装置は、以下のような工程により製造さ
れる。(Prior Art) Generally, a semiconductor device is manufactured by the following steps.
すなわち、まず半導体ウエハ上に精密写真転写技術等に
より多数の半導体チップを形成し、この後、個々の半導
体チップに切断する。そして、この半導体チップをリー
ドを有する基体、例えばリードフレームに配置し、半導
体チップの電極パッドとリードフレームのリードとを例
えばワイヤボンディング等によって接続する。しかる
後、例えばモールド等により半導体チップの保護体を形
成し、半導体装置を得る。なお、例えばTAB(tape auto
mated bonding)等により基板上に半導体チップを実装
した半導体装置もある。That is, first, a large number of semiconductor chips are formed on a semiconductor wafer by a precision photo transfer technique or the like, and then cut into individual semiconductor chips. Then, this semiconductor chip is arranged on a substrate having leads, for example, a lead frame, and the electrode pads of the semiconductor chip and the leads of the lead frame are connected by, for example, wire bonding. Then, a semiconductor chip protector is formed by, for example, a mold to obtain a semiconductor device. For example, TAB (tape auto
There is also a semiconductor device in which a semiconductor chip is mounted on the substrate by mated bonding, etc.
そして、一般に上述のような半導体装置の製造工程で
は、半導体ウエハの状態でのプローブ装置を用いた検査
と、ハンドラあるいは基板検査装置等を用いた完成品の
半導体装置の検査が行われている。In general, in the above-described semiconductor device manufacturing process, an inspection using a probe device in a semiconductor wafer state and an inspection of a completed semiconductor device using a handler or a substrate inspection device are performed.
また、本発明者等は、完成品の半導体装置を、トレイ上
に配置して検査する方法を、特願昭61−299646、特願昭
62−156924等で提案している。Further, the inventors of the present invention have disclosed a method of arranging a finished semiconductor device on a tray and inspecting it, in Japanese Patent Application Nos. 61-299646 and 61-299646.
62-156924 and so on.
(発明が解決しようとする課題) 上述のように従来は、半導体ウエハの状態および完成品
の半導体装置の検査を行っている。したがって、例えば
ワイヤボンディングの不良等、半導体ウエハの状態での
検査後に生じた不良は、完成後でなければ発見すること
ができず、生産性の低下を招くという問題があった。(Problems to be Solved by the Invention) As described above, conventionally, the state of the semiconductor wafer and the finished semiconductor device are inspected. Therefore, for example, a defect such as a defect in wire bonding that occurs after the inspection in the state of the semiconductor wafer cannot be detected until after the completion, and there is a problem that productivity is lowered.
また、完成品の状態での検査では、完成品のリード部分
が曲ってしまうために、モールドによる製品不良の割合
が少ない割に、連続的に検査するハンドラにおいて生産
がとどこおる問題があった。In addition, in the inspection of the finished product, since the lead portion of the finished product is bent, the proportion of product defects due to the mold is small, but there is a problem in that the handler that continuously inspects the product has some production problems.
本発明は、かかる従来の事情に対処してなされたもの
で、半導体チップの電極パッドと基体のリードとを接続
した状態の半完成品の半導体装置を、効率良く検査する
ことができ、従来に較べて生産性の向上を図ることので
きる半導体装置の検査方法を提供しようとするものであ
る。The present invention has been made in response to such conventional circumstances, and it is possible to efficiently inspect a semi-finished semiconductor device in a state where the electrode pads of the semiconductor chip and the leads of the base are connected, An object of the present invention is to provide a method for inspecting a semiconductor device, which can improve productivity in comparison.
[発明の構成] (課題を解決するための手段) すなわち本発明は、少なくとも半導体チップと、この半
導体チップの電極パッドが電気的に接続されるリードを
有する基体とを具備した半導体装置を検査するに際し、
前記半導体チップの電極パッドと前記基体のリードとを
接続した状態の半完成品の半導体装置を位置決め機構を
有するトレイ上に複数配置し、この後前記トレイを搬
送、位置決めし、しかる後前記リードに探針を接触させ
て前記半完成品の半導体装置の電気適な検査を行うこと
を特徴とする。[Structure of the Invention] (Means for Solving the Problems) That is, the present invention tests a semiconductor device including at least a semiconductor chip and a substrate having a lead to which an electrode pad of the semiconductor chip is electrically connected. On the occasion of
A plurality of semi-finished semiconductor devices in which the electrode pads of the semiconductor chip and the leads of the base are connected are arranged on a tray having a positioning mechanism, and then the trays are conveyed and positioned, and then the leads are mounted on the leads. The semi-finished semiconductor device is electrically inspected by bringing the probe into contact with the probe.
(作 用) 上記構成の本発明の半導体装置の検査方法では、半導体
チップの電極パッドと基体のリードとを接続した状態の
半完成品の半導体装置、例えばモールド前のリードフレ
ーム状態の半導体装置を、位置決め機構を有するトレイ
上に複数配置し、このトレイを搬送、位置決めし、リー
ドに探針を接触させて、半完成品の半導体装置の電気的
な検査を行う。(Operation) In the method for inspecting a semiconductor device of the present invention having the above-described structure, a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the substrate are connected, for example, a semiconductor device in a lead frame state before molding is used. A plurality of trays having a positioning mechanism are arranged, the trays are transported and positioned, and the leads are brought into contact with the probe to electrically inspect the semi-finished semiconductor device.
したがって、例えばワイヤボンディングの不良等、半導
体ウエハの状態での検査後に生じた不良をモールド前に
発見することができ、従来に較べて生産性の向上を図る
ことができる。また、トレイ上に半完成品の半導体装置
を複数配置するので、例えば大型基板用プローブ装置等
を用いて効率良く検査することができる。Therefore, it is possible to detect a defect such as a defect in wire bonding which occurs after the inspection in the state of the semiconductor wafer before the molding, and it is possible to improve the productivity as compared with the conventional case. Further, since a plurality of semi-finished semiconductor devices are arranged on the tray, it is possible to efficiently perform the inspection using, for example, a large substrate probe device.
さらに、リード曲りのための検査の停止を防ぐことがで
き、生産性の向上が得られる。Further, it is possible to prevent the inspection from being stopped due to bending of the lead, and the productivity can be improved.
(実施例) 以下本発明の半導体装置の検査方法の実施例を図面を参
照して説明する。(Embodiment) An embodiment of a semiconductor device inspection method of the present invention will be described below with reference to the drawings.
例えば矩形の板状に形成されたトレイ1は、絶縁材料か
らなり、所定サイズ例えば大型基板用プローブ装置によ
って検査可能な基板と同等なサイズとされており、この
トレイ1には、複数の凹部2が列設されている。For example, the tray 1 formed in the shape of a rectangular plate is made of an insulating material and has a predetermined size, for example, a size equivalent to a substrate that can be inspected by a probe device for a large substrate. Are lined up.
これらの凹部2は、半導体チップの電極パッドと基体の
リードとを接続した状態の半完成品の半導体装置、例え
ばリードフレーム3aのリードと半導体チップ3bの電極パ
ッドとをワイヤー3cによってボンディングした状態の半
完成品の半導体装置3を収容するとともに、このリード
フレーム状態の半導体装置3を所定精度、例えば大型基
板用プローブ装置でリードに探針を接触可能な精度に位
置決めすることができるよう構成されている。These recesses 2 are semi-finished semiconductor devices in which the electrode pads of the semiconductor chip and the leads of the base are connected, for example, the leads of the lead frame 3a and the electrode pads of the semiconductor chip 3b are bonded by the wires 3c. The semiconductor device 3 is a semi-finished product, and the semiconductor device 3 in the lead frame state can be positioned with a predetermined accuracy, for example, with a large substrate probe device so that the probe can be brought into contact with the lead. There is.
そして、上記トレイ1の各凹部2に、半完成品の半導体
装置3を配置し、例えば大型基板用プローブ装置を用い
て、搬送、位置決めし、第2図に示すように、リードフ
レーム3aのリードに探針4を接触させて、半完成品の半
導体装置3の電気的な検査を行う。Then, the semi-finished semiconductor device 3 is placed in each recess 2 of the tray 1, and is transported and positioned by using, for example, a probe device for a large substrate, and as shown in FIG. The semi-finished semiconductor device 3 is electrically inspected by bringing the probe 4 into contact with.
したがって、例えばワイヤボンディングの不良等、半導
体ウエハの状態での検査後に生じた不良をモールド前に
発見することができ、従来に較べて生産性の向上を図る
ことができる。また、トレイ1上に半完成品の半導体装
置3を複数配置し、大型基板用プローブ装置を用いて検
査を行うので、特別な検査装置を必要とすることなく、
効率良く検査することができる。Therefore, it is possible to detect a defect such as a defect in wire bonding which occurs after the inspection in the state of the semiconductor wafer before the molding, and it is possible to improve the productivity as compared with the conventional case. In addition, since a plurality of semi-finished semiconductor devices 3 are arranged on the tray 1 and the inspection is performed using the probe device for a large substrate, there is no need for a special inspection device.
It can be inspected efficiently.
なお、上記実施例では、リードフレーム3aのリードと半
導体チップ3bの電極パッドとをワイヤー3cによってボン
ディングした状態の半完成品の半導体装置3について説
明したが、その他の半完成品の半導体装置、例えばTAB
によってボンディングを行い、テープを切断した後の半
完成品の半導体装置、あるいは基板上に直接半導体チッ
プを搭載したCOB(chip on board)の半完成品の半導体
装置等でも同様にして検査することができる。また、CO
Bの半完成品の半導体装置の検査を行う場合、基板の大
きさによっては、トレイ1を使用せずに検査することも
可能である。In the above embodiment, the semi-finished semiconductor device 3 in which the leads of the lead frame 3a and the electrode pads of the semiconductor chip 3b are bonded by the wires 3c has been described, but other semi-finished semiconductor devices, for example, TAB
It is also possible to inspect in the same way for semi-finished semiconductor devices after bonding and cutting the tape, or semi-finished semiconductor devices of COB (chip on board) with semiconductor chips directly mounted on the substrate. it can. Also, CO
When the semi-finished semiconductor device B is inspected, it is possible to inspect it without using the tray 1 depending on the size of the substrate.
さらに、トレイ内にモールドされた完成品を設置して完
成品検査も行うことができる。In addition, a finished product molded in the tray can be installed to perform a finished product inspection.
[発明の効果] 上述のように、本発明の半導体装置の検査方法では、半
導体チップの電極パッドと基体のリードとを接続した状
態の半完成品の半導体装置を、効率良く検査することが
でき、従来に較べて生産性の向上を図ることができる。[Effects of the Invention] As described above, according to the semiconductor device inspection method of the present invention, a semi-finished semiconductor device in which the electrode pads of the semiconductor chip and the leads of the substrate are connected can be efficiently inspected. The productivity can be improved as compared with the conventional one.
第1図は本発明の一実施例の半導体装置の検査方法を説
明するためのトレイの平面図、第2図は第1図のトレイ
上に半完成品の半導体装置を配置して探針を接触させた
状態を示す側面図である。 1……トレイ、2……凹部、3……半完成品の半導体装
置。FIG. 1 is a plan view of a tray for explaining a semiconductor device inspection method according to an embodiment of the present invention, and FIG. 2 is a semi-finished semiconductor device arranged on the tray of FIG. It is a side view which shows the state which was made to contact. 1 ... Tray, 2 ... recessed part, 3 ... semi-finished semiconductor device.
Claims (1)
ップの電極パッドが電気的に接続されるリードを有する
基体とを具備した半導体装置を検査するに際し、 前記半導体チップの電極パッドと前記基体のリードとを
接続した状態の半完成品の半導体装置を位置決め機構を
有するトレイ上に複数配置し、この後前記トレイを搬
送、位置決めし、しかる後前記リードに深針を接触させ
て前記半完成品の半導体装置の電気的な検査を行うこと
を特徴とする半導体装置の検査方法。1. When inspecting a semiconductor device comprising at least a semiconductor chip and a base having leads to which electrode pads of the semiconductor chip are electrically connected, the electrode pads of the semiconductor chip and the leads of the base are provided. A plurality of semi-finished semiconductor devices connected to each other are arranged on a tray having a positioning mechanism, and then the trays are transported and positioned, and then a deep needle is brought into contact with the lead to complete the semi-finished semiconductor. A method of inspecting a semiconductor device, which comprises electrically inspecting the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63043853A JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63043853A JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01218035A JPH01218035A (en) | 1989-08-31 |
| JPH07107911B2 true JPH07107911B2 (en) | 1995-11-15 |
Family
ID=12675270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63043853A Expired - Lifetime JPH07107911B2 (en) | 1988-02-26 | 1988-02-26 | Semiconductor device inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07107911B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5335407U (en) * | 1976-09-01 | 1978-03-28 | ||
| JPH0740580B2 (en) * | 1985-12-20 | 1995-05-01 | 日本電気株式会社 | Substrate for selecting semiconductor element and method for selecting semiconductor element |
-
1988
- 1988-02-26 JP JP63043853A patent/JPH07107911B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01218035A (en) | 1989-08-31 |
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