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JPH07109849B2 - Semiconductor crystal evaluation method and apparatus - Google Patents
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JPH07109849B2 - Semiconductor crystal evaluation method and apparatus - Google Patents

Semiconductor crystal evaluation method and apparatus

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Publication number
JPH07109849B2
JPH07109849B2 JP1024270A JP2427089A JPH07109849B2 JP H07109849 B2 JPH07109849 B2 JP H07109849B2 JP 1024270 A JP1024270 A JP 1024270A JP 2427089 A JP2427089 A JP 2427089A JP H07109849 B2 JPH07109849 B2 JP H07109849B2
Authority
JP
Japan
Prior art keywords
sample
wafer
crystal
gaas
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1024270A
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Japanese (ja)
Other versions
JPH02205045A (en
Inventor
文明 日向
山崎  肇
暁 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
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Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1024270A priority Critical patent/JPH07109849B2/en
Publication of JPH02205045A publication Critical patent/JPH02205045A/en
Publication of JPH07109849B2 publication Critical patent/JPH07109849B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
  • Investigating Or Analysing Materials By Optical Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 (1) 発明の属する分野 本発明は、GaAs結晶基板上にイオン注入法によって集積
回路の基本素子である電界効果トランジスタ(FET)を
形成する際に、基板として用いるGaAs結晶の特性を非破
壊で効率的に再現性良く評価する方法および装置に関す
るものである。
Description: (1) Field of the Invention The present invention relates to GaAs used as a substrate when forming a field effect transistor (FET) which is a basic element of an integrated circuit on a GaAs crystal substrate by an ion implantation method. The present invention relates to a method and a device for nondestructively and efficiently evaluating crystals with good reproducibility.

(2) 従来の技術とその問題点 GaAs結晶を基板として利用したFETは、基板表面に直接
ドナー元素をイオン注入してn形活性層を形成し作製す
るのが一般的である。従って、集積回路の性能は基板結
晶の特性に大きく依存する。
(2) Conventional Technology and Its Problems In general, an FET using a GaAs crystal as a substrate is manufactured by directly implanting a donor element into the surface of the substrate to form an n-type active layer. Therefore, the performance of the integrated circuit largely depends on the characteristics of the substrate crystal.

現在GaAs−FETのn形活性層形成には、注入元素としてS
iが最も一般的に用いられている。SiはIV族元素である
ため、III−V族化合物半導体であるGaAs結晶中では両
性元素として作用する。すなわち、注入されたSiはIII
族元素であるGaの格子位置に置換されてドナーとなるだ
けでなく、V族元素であるAsの格子位置にも置換されて
アクセプターとなる。一方、V族元素は蒸気圧が高く揮
発性である。このため、V族元素であるAsは結晶育成、
基板作製の過程でGaAs結晶から蒸発し、結晶基板内には
As空孔が様々な濃度で導入されている。これらより、一
般に同一濃度のSiをGaAs基板に注入しても、基板ごとに
SiがGa格子位置とAs格子位置に置換される割合が変動
し、基板間でn形活性層の特性不均一がもたらされる。
Currently, S is used as an implantation element for forming the n-type active layer of GaAs-FET.
i is the most commonly used. Since Si is a group IV element, it acts as an amphoteric element in the GaAs crystal which is a group III-V compound semiconductor. That is, the injected Si is III
Not only is it substituted into the lattice position of Ga, which is a group element, to become a donor, but it is also substituted into the lattice position of As, which is a group V element, to become an acceptor. On the other hand, the group V element has a high vapor pressure and is volatile. For this reason, As, which is a group V element, crystal growth,
During the process of manufacturing the substrate, it was evaporated from the GaAs crystal and
As vacancies are introduced at various concentrations. As a result, even if Si of the same concentration is injected into a GaAs substrate,
The ratio of substitution of Si at the Ga lattice position and that at the As lattice position varies, resulting in non-uniform characteristics of the n-type active layer between the substrates.

上記の特性不均一を克服する方法として、従来は、実際
に素子製作を行う基板と結晶インゴット内で近接した位
置から切り出した基板に予めイオン注入によってn形活
性層を形成して、ドナー濃度からアクセプタ濃度を引い
たキャリア濃度を求め、これを基に素子製作の際のSi注
入量を決定する方法が採用されて来た。しかし、この方
法は、破壊検査であるため実際の素子作製に用いる基
板を直接評価できず信頼性に乏しいこと、n形活性層
を形成しなければならないため、煩雑でかつ評価終了ま
での1サイクルに長時間を要することという欠点があっ
た。
As a method of overcoming the non-uniformity of characteristics described above, conventionally, an n-type active layer is formed by ion implantation in advance on a substrate cut out from a position close to a substrate in which a device is actually manufactured and a crystal ingot, and the concentration of the donor is changed. A method has been adopted in which the carrier concentration is calculated by subtracting the acceptor concentration and the Si implantation amount is determined based on the carrier concentration. However, since this method is a destructive inspection, the substrate used for actual device fabrication cannot be directly evaluated, resulting in poor reliability, and since an n-type active layer must be formed, it is complicated and one cycle until the end of evaluation. There was a drawback that it took a long time.

(3) 発明の目的 本発明は、上記欠点を克服するため、光学測定装置を用
いて素子製作に用いる結晶基板を室温で直接、非破壊か
つ効率的に評価、即ち、所定のSi注入量で実現されるキ
ャリア濃度を予測できるようにした半導体結晶評価方法
および装置を提供するものである。
(3) Object of the invention In order to overcome the above-mentioned drawbacks, the present invention directly, non-destructively and efficiently evaluates a crystal substrate used for element fabrication using an optical measuring device at room temperature, that is, with a predetermined Si implantation amount. Provided is a semiconductor crystal evaluation method and device capable of predicting the carrier concentration to be realized.

(4) 発明の構成及び作用 以下に本発明によるGaAs結晶基板の評価方法および装置
について述べる。測定は第1図に示す構成の光学測定装
置を用いて行う。即ち、被測定結晶基板は未測定試料収
納カセット1からオリフラ合わせ台2に運ばれて、所定
の方向、位置に合わされた後、試料台3に運ばれる。こ
の状態でのレーザ光源4より励起光5を試料に照射し、
この時試料から放射されるルミネッセンス6を分光器7
によって分交し、その強度を検出器8により測定する。
測定終了後、基板は測定終了試料収納カセット9に運ば
れて、一連の測定動作が終了する。試料を自動的にセッ
ト・リセットする機構は、一連の測定動作中に試料上に
ほこりが堆積されたり、きずがついたりすることを防
ぎ、本装置が実際の集積回路製作工程内に組み込んで使
えるようにするため付加している。
(4) Structure and Action of the Invention A method and apparatus for evaluating a GaAs crystal substrate according to the present invention will be described below. The measurement is performed using an optical measuring device having the configuration shown in FIG. That is, the crystal substrate to be measured is carried from the unmeasured sample storage cassette 1 to the orientation flat alignment table 2, aligned with a predetermined direction and position, and then transported to the sample table 3. The sample is irradiated with excitation light 5 from the laser light source 4 in this state,
At this time, the luminescence 6 emitted from the sample is analyzed by the spectroscope 7
And the intensity is measured by the detector 8.
After the measurement is completed, the substrate is carried to the measurement-completed sample storage cassette 9 and a series of measurement operations is completed. The mechanism that automatically sets and resets the sample prevents dust accumulation and scratches on the sample during a series of measurement operations, and this device can be used by incorporating it in the actual integrated circuit manufacturing process It is added in order to do so.

第2図は、室温下で測定したGaAs結晶基板からのルミネ
ッセンス・スペクトルを示す。通常、測定波長域1.0〜
2.5μm近辺にのみ発光が観測される。この発光はGa格
子位置に置換されたAsに関与する発光で、この発光が強
い結晶はAsがGa格子位置を占め易い、すなわち、Ga空孔
が過剰な状態となっていることを示す。すでに述べたよ
うに、n形活性層のキャリア濃度はイオン注入したSiが
Ga格子位置とAs格子位置を占める割合に依存する。この
割合は、結晶中のGa空孔とAs空孔の濃度比に比例する。
従って、n形活性層のキャリア濃度は、上記光学測定装
置で得られる1.75μm近辺の発光の強度により予測可能
となる。実際にこれらの相関を種々のGaAs結晶基板を用
いて調べた結果を第3図に示す。ここで、n形活性層は
Siを60keVに加速して面積密度を5×1012/cm2でイオン
注入して形成した。両者の間には明確な直線関係が存在
している。即ち、本発明の原理を用いれば、GaAs集積回
路基板の特性、即ち、所定のSi注入量で実現されるキャ
リア濃度を、非破壊で直接予測できることになる。これ
をもとに、一定のSi注入量で所定のキャリア濃度を実現
できるGaAs集積回路用基板の選別、あるいは、受け入れ
基板を用いて所望のキャリア濃度を実現するのに必要な
Si注入量の決定が可能となる。
FIG. 2 shows a luminescence spectrum from a GaAs crystal substrate measured at room temperature. Normally, the measurement wavelength range 1.0 to
Luminescence is observed only around 2.5 μm. This luminescence is the luminescence related to As substituting at the Ga lattice position, and crystals with strong luminescence indicate that As easily occupies the Ga lattice position, that is, Ga vacancies are in an excessive state. As already mentioned, the carrier concentration of the n-type active layer is
Depends on the proportion of Ga and As lattice positions. This ratio is proportional to the concentration ratio of Ga vacancies and As vacancies in the crystal.
Therefore, the carrier concentration of the n-type active layer can be predicted by the intensity of light emission in the vicinity of 1.75 μm obtained by the above optical measuring device. FIG. 3 shows the results of actually examining these correlations using various GaAs crystal substrates. Here, the n-type active layer is
It was formed by accelerating Si to 60 keV and implanting ions at an area density of 5 × 10 12 / cm 2 . There is a clear linear relationship between the two. That is, by using the principle of the present invention, the characteristics of the GaAs integrated circuit substrate, that is, the carrier concentration realized by a predetermined Si implantation amount, can be directly predicted nondestructively. Based on this, it is necessary to select a GaAs integrated circuit substrate that can achieve a predetermined carrier concentration with a fixed Si injection amount, or to achieve a desired carrier concentration using a receiving substrate.
It is possible to determine the Si implantation amount.

第2図及び第3図は、測定波長域1.0〜2.5μmで一般的
に用いられるPbS検出器を用いて得た結果である。この
検出器、GaAs結晶について室温下で測定を行って十分は
ルミネッセンス出力を得るには、励起光であるレーザ光
出力を100mW以上にする必要がある。この場合、レーザ
照射によってGaAs基板表面で酸化が進行し、第4図に示
すようにルミネッセンス出力は時間と共に変化する。即
ち、ルミネッセンス出力はレーザ光照射時間と共に低下
し、約30分で一定値となる。これをともに、上記測定は
レーザ光照射後30分以上を経過した後に行っている。一
方、Ge検出器は測定波長が1.65μmを超えると感度が急
激に低下するが、測定波長範囲1.2〜1.65μmではPbS検
出器より3〜4桁高感度となる。すでに第2図で述べた
ように、GaAs結晶基板の室温下測定で得られる発光は1.
0〜2.5μmの波長範囲では1.75μm近辺のもののみであ
る。また、この発光は1.5〜2.0μmと広い波長範囲で発
光する。従って、1.75μm近辺の発光の発光強度はGe検
出器を用いて、1.65μm近辺の発光強度を測定すること
により、類推できる。この場合、Ge検出器はPbS検出器
より3〜4桁高感度であるため、励起用レーザ光の出力
を低くしても十分な測定出力が得られる。従って、レー
ザ光源の代りに分光された白色光を出力する光源を用い
ることもできる。第5図は第3図で用いた試料につい
て、0.9mWのレーザ光を照射して波長1.65μmでのルミ
ネッセンス出力をGe検出器を用いて測定し、これとキャ
リア濃度の相関を調べたものである。結果はPbS検出器
を用いた第3図の場合と全く一致している。また、レー
ザ光出力を2桁下げたため、試料表面での酸化は無く、
第4図に示した様なルミネッセンス出力の時間変化は全
く起こらなかった。これをもとに、第5図に示したルミ
ネッセンス測定はレーザ光照射後0.1秒経過後に行って
いる。すなわち、Ge検出器を用いた場合は測定時間を大
幅に短縮でき、また、試料表面の酸化を回避できるため
完全な非破壊検査が実現できる。第1図に示す半導体結
晶評価装置におけるカセット1からカセット9への移動
機構についてさらに説明する。
2 and 3 show the results obtained using a PbS detector generally used in the measurement wavelength range of 1.0 to 2.5 μm. In order to obtain sufficient luminescence output by performing measurements at room temperature on this detector and GaAs crystal, it is necessary to set the laser light output which is the excitation light to 100 mW or more. In this case, the laser irradiation causes oxidation to proceed on the surface of the GaAs substrate, and the luminescence output changes with time as shown in FIG. That is, the luminescence output decreases with the laser light irradiation time and becomes a constant value in about 30 minutes. In both of these, the above-mentioned measurement is performed after 30 minutes or more have passed after laser light irradiation. On the other hand, the sensitivity of the Ge detector sharply decreases when the measurement wavelength exceeds 1.65 μm, but it becomes 3 to 4 orders of magnitude higher than that of the PbS detector in the measurement wavelength range of 1.2 to 1.65 μm. As already mentioned in Fig. 2, the luminescence obtained by measuring the GaAs crystal substrate at room temperature is 1.
In the wavelength range of 0 to 2.5 μm, it is only around 1.75 μm. Further, this light emission is in a wide wavelength range of 1.5 to 2.0 μm. Therefore, the emission intensity of the emission in the vicinity of 1.75 μm can be inferred by measuring the emission intensity in the vicinity of 1.65 μm using a Ge detector. In this case, the Ge detector is 3 to 4 orders of magnitude more sensitive than the PbS detector, and therefore a sufficient measurement output can be obtained even if the output of the excitation laser light is lowered. Therefore, instead of the laser light source, it is possible to use a light source that outputs spectral white light. FIG. 5 shows the correlation between the luminescence output at 0.95 Wm of the sample used in FIG. 3 and the luminescence output at a wavelength of 1.65 μm using a Ge detector, and the correlation with the carrier concentration. is there. The results are completely in agreement with the case of Fig. 3 using the PbS detector. Also, because the laser light output is reduced by two digits, there is no oxidation on the sample surface,
The luminescence output did not change with time as shown in FIG. Based on this, the luminescence measurement shown in FIG. 5 is performed 0.1 seconds after the laser light irradiation. That is, when the Ge detector is used, the measurement time can be significantly shortened, and since oxidation of the sample surface can be avoided, complete nondestructive inspection can be realized. The moving mechanism from the cassette 1 to the cassette 9 in the semiconductor crystal evaluation apparatus shown in FIG. 1 will be further described.

この機構は、測定用試料台(第1図では3)に試料例え
ば3インチ径ウェハを、全く汚したり傷つけたりしない
で、再現性良く(いつも同じ場所、同じ方向)設置・除
去することを目的としている。これを実現するため、汚
れに対しては、以下の2項で対処することができる。
The purpose of this mechanism is to install / remove a sample, such as a 3-inch diameter wafer, on the sample stage for measurement (3 in FIG. 1) with good reproducibility (always at the same place and in the same direction) without any contamination or damage. I am trying. To realize this, dirt can be dealt with in the following item 2.

装置をクリンルーム内で使用する ステージ上でのウェハの吸着等に必要な真空は、従
来の真空ポンプ油,ベルトを用いた真空ポンプではな
く、ダイアフラムを用いたベルトレスの真空ポンプで実
現する。
The vacuum required for wafer adsorption on the stage when the equipment is used in a clean room is realized by a beltless vacuum pump that uses a diaphragm instead of the conventional vacuum pump oil and vacuum pump that uses a belt.

また、傷については、そのほとんどが従来のピンセット
によりウェハ表裏への機械的な傷であることに着目し、
ウェハの移動は真空ピンセットでウェハの裏面を吸着し
て行うことで対処することができる。
Also, with regard to scratches, paying attention to that most of them are mechanical scratches on the front and back of the wafer with conventional tweezers,
The movement of the wafer can be dealt with by suctioning the back surface of the wafer with vacuum tweezers.

また、ウェハ設置位置・方向の再現性向上には、第1図
に示す装置構成と第6図に示すオリフラ合わせ機構を用
いて以下の手順で実現することができる。
Further, the improvement of the reproducibility of the wafer installation position / direction can be realized by the following procedure using the apparatus configuration shown in FIG. 1 and the orientation flat alignment mechanism shown in FIG.

ウェハ移動手順 未測定試料収納カセット1中のウェハを真空ピンセ
ットを用いて(ウェハ裏面に吸着)オリフラ合わせ機構
(第1図では2)に移動する。
Wafer Moving Procedure The wafer in the unmeasured sample storage cassette 1 is moved to the orientation flat aligning mechanism (2 in FIG. 1) by using vacuum tweezers (suction on the back surface of the wafer).

オリフラ合わせ機構上で、ウェハの方向・位置を一
定の状態に設定する。
The orientation and position of the wafer are set to a fixed state on the orientation flat alignment mechanism.

ウェハをオリフラ合わせ機構から真空ピンセットを
用いて試料台3に移動する。
The wafer is moved from the orientation flat alignment mechanism to the sample table 3 using vacuum tweezers.

試料台3に真空吸着を利用してウェハを固定して測
定する。
The wafer is fixed to the sample table 3 by vacuum suction and measurement is performed.

真空ピンセットを用いて、ウェハを試料台3から測
定終了試料収納カセット9に移動する。
The wafer is moved from the sample table 3 to the measurement-completed sample storage cassette 9 using the vacuum tweezers.

オリフラ合わせ機構によるウェハの方向・位置合わせ方
法 通常、ウェハには方向を明示するため第7図に示すよう
な主オリフラ15aと副オリフラ15bが付加されている。オ
リフラ合わせ機構は、第6図に示すように、これを検出
する発光素子11,受光素子12からなる検出部,回転台13,
テーパー状の溝を持つ試料保持台14から構成され、以下
の手順で動作させる。
Wafer Direction / Position Alignment Method Using Orientation Alignment Mechanism Usually, a wafer is provided with a main orientation flat 15a and a sub orientation flat 15b as shown in FIG. 7 in order to clearly indicate the orientation. As shown in FIG. 6, the orientation flat aligning mechanism includes a detecting portion including a light emitting element 11 and a light receiving element 12 for detecting this, a rotary base 13,
It is composed of a sample holder 14 having a tapered groove, and is operated by the following procedure.

回転台13を上昇させて、カセットより送られて来た
ウェハ10を回転台13上で受け取る。
The turntable 13 is raised and the wafer 10 sent from the cassette is received on the turntable 13.

ウェハ10を吸着し、回転台13を回転してオリフラ15
a,15bを検出し、その後回転台13を停止する。
The wafer 10 is attracted and the rotary table 13 is rotated to rotate the orientation flat 15
After detecting a and 15b, the turntable 13 is stopped.

ウェハ10を吸着を解除し、回転台13を下降させ、ウ
ェハ10を試料保持台14上に設置する。
The adsorption of the wafer 10 is released, the rotary table 13 is lowered, and the wafer 10 is set on the sample holding table 14.

再び回転台13を上昇する。 Raise the turntable 13 again.

ウェハ10を吸着し、再度項と同様にオリフラ15a,
15bを検出する。
Adsorb the wafer 10, and again, the orientation flat 15a,
Detects 15b.

上記項に従ってウェハ10を試料保持台14上に設置
する。
The wafer 10 is set on the sample holder 14 according to the above item.

上記項でウェハ10の方向がおおまかに決定され、で
ウェハ10の位置がほぼ正確に決定される。でウェハ10
の方向が正確に決定され、で動作が完了する。ウェハ
10を取り出す場合は、試料保持台14から真空ピンセット
で次の場所(試料台3)に運ぶ。オリフラ合わせ機構と
試料台3の位置関係を一定にしておけば、ウェハ10は試
料台3の決まった方向・位置に設置される。
The orientation of the wafer 10 is roughly determined in the above section, and the position of the wafer 10 is determined almost accurately in. In wafer 10
The direction of is accurately determined, and the operation is completed. Wafer
When the sample 10 is taken out, it is carried from the sample holder 14 to the next place (sample table 3) with vacuum tweezers. If the positional relationship between the orientation flat aligning mechanism and the sample table 3 is kept constant, the wafer 10 is set in the fixed direction and position of the sample table 3.

(5) 発明の効果 以上詳細に説明したように、本発明によれば室温で直接
非破壊かつ効率的にGaAs結晶の評価をすることができる
ので、特に基板性能の評価に適用して有効であり、集積
回路の性能向上の効果は極めて大である。
(5) Effects of the Invention As described in detail above, according to the present invention, it is possible to directly and non-destructively and efficiently evaluate a GaAs crystal at room temperature, which is particularly effective when applied to the evaluation of substrate performance. Therefore, the effect of improving the performance of the integrated circuit is extremely large.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明で用いる光学測定装置の構成図、第2図
はこの光学測定装置を用いて室温下で測定したGaAs結晶
基板の代表的なフォトルミネッセンススペクトル特性
図、第3図はGaAs結晶基板について求めた波長1.75μm
での発光の強度とn活性層のキャリア濃度の相関を示す
図、第4図は励起レーザ光出力100mWで室温下測定を行
った場合のルミネッセンス出力の時間変化特性図、第5
図はレーザ光出力0.9mWでGe検出器を用いてGaAs結晶基
板について求めた波長1.65μmでの発光の強度とn形活
性層のキャリア濃度との相関を示す図、第6図(a)
(b)は本発明に用いるオリフラ合せ台の構成例を示す
平面図及び正面図、第7図は本発明に用いる試料の形状
の例を示す平面図である。 1……未測定試料収納カセット、2……オリフラ合わせ
台、3……試料台、4……レーザ光源、5……励起光、
6……ルミネッセンス、7……分光器、 8……検出器、9……測定終了試料収納カセット、10…
…ウェハ、11……発光素子、12……受光素子、 13……回転台、14……試料保持台、15a……主オリフ
ラ、15b……副オリフラ。
FIG. 1 is a block diagram of an optical measuring device used in the present invention, FIG. 2 is a typical photoluminescence spectrum characteristic diagram of a GaAs crystal substrate measured at room temperature using this optical measuring device, and FIG. 3 is a GaAs crystal. Wavelength calculated for the substrate 1.75 μm
FIG. 4 is a diagram showing the correlation between the emission intensity and the carrier concentration of the n-active layer in FIG. 4, and FIG. 4 is a time change characteristic diagram of luminescence output when measured at room temperature with a pump laser light output of 100 mW.
The figure shows the correlation between the emission intensity at a wavelength of 1.65 μm and the carrier concentration in the n-type active layer, which was obtained by using a Ge detector with a laser light output of 0.9 mW and a Ge detector, and FIG. 6 (a).
(B) is a plan view and a front view showing a configuration example of an orientation flat matching table used in the present invention, and FIG. 7 is a plan view showing an example of the shape of a sample used in the present invention. 1 ... unmeasured sample storage cassette, 2 ... orientation flat alignment table, 3 ... sample table, 4 ... laser light source, 5 ... excitation light,
6 ... Luminescence, 7 ... Spectrometer, 8 ... Detector, 9 ... Measurement end sample storage cassette, 10 ...
... Wafer, 11 ... Light emitting element, 12 ... Light receiving element, 13 ... Rotary table, 14 ... Sample holder, 15a ... Main orientation flat, 15b ... Sub orientation flat.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】GaAs結晶試料に分光された白色光あるいは
レーザ光を照射した後、該GaAs試料から放射される波長
1.65μm近辺の発光の強度をGe検出器を用いて分光測定
することにより該試料の結晶特性を評価することを特徴
とする半導体結晶評価方法。
1. A wavelength emitted from a GaAs sample after irradiating a GaAs crystal sample with spectral white light or laser light.
1. A semiconductor crystal evaluation method, characterized in that the crystal characteristics of the sample are evaluated by spectroscopically measuring the intensity of light emission in the vicinity of 1.65 μm using a Ge detector.
【請求項2】GaAs結晶試料を測定のために載置する試料
台と、 該試料台に載置された前記GaAs結晶試料に分光された白
色光またはレーザ光を照射する光源と、 該レーザ光の照射後に前記GaAs結晶試料から放射される
波長1.65μm近辺の発光の強度を該試料の結晶特性の評
価のためにGe検出器を用いて分光測定する分光検知器と を備えた半導体結晶評価装置。
2. A sample table on which a GaAs crystal sample is mounted for measurement, a light source for irradiating the GaAs crystal sample mounted on the sample table with white light or laser light dispersed, and the laser beam. And a semiconductor crystal evaluation device for spectroscopically measuring the intensity of the light emitted from the GaAs crystal sample near the wavelength of 1.65 μm after the irradiation with a Ge detector for the evaluation of the crystal characteristics of the sample. .
JP1024270A 1989-02-02 1989-02-02 Semiconductor crystal evaluation method and apparatus Expired - Fee Related JPH07109849B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1024270A JPH07109849B2 (en) 1989-02-02 1989-02-02 Semiconductor crystal evaluation method and apparatus

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Application Number Priority Date Filing Date Title
JP1024270A JPH07109849B2 (en) 1989-02-02 1989-02-02 Semiconductor crystal evaluation method and apparatus

Publications (2)

Publication Number Publication Date
JPH02205045A JPH02205045A (en) 1990-08-14
JPH07109849B2 true JPH07109849B2 (en) 1995-11-22

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Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115346A (en) * 1985-11-14 1987-05-27 Fujitsu Ltd Method and instrument for measuring impurity concentration in semiconductor crystal

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