JPH07109890B2 - Driver circuit using complementary transistors - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit using complementary transistors, and more particularly to a complementary transistor structure using thin film transistors.

[0002]

2. Description of the Related Art In recent years, for example, in a lead-out portion of a solid-state image sensor, a contact type sensor has been proposed which is brought into close contact with an object to be read in order to simplify an optical system. A thin film imaging device as disclosed in Japanese Laid-Open Patent Publication No. 57-114292 is known. These thin film transistors are used as cell selection switches of the photoelectric conversion unit, and are applied to either N-type or P-type conductivity type transistors. If a driver circuit (peripheral circuit) such as a scan circuit that supplies a selection pulse to the cell selection transistor of the photoelectric conversion unit is formed on the same substrate, the image sensor can be made compact and the cost can be reduced. Can be achieved.

[0003]

However, when the drive circuit (driver circuit) is formed of the above-mentioned thin film transistors, the following problems are brought about.

Since the voltage amplification factor of the thin film transistor is smaller than that of the bulk transistor, it is difficult to obtain a sufficient drive output voltage amplitude, and the noise margin becomes small. This is because even if there is a slight defect on the formed integrated circuit pattern, the circuit operation is likely to be disabled,
The yield is poor.

Further, since the voltage amplification factor of the thin film transistor is small, variations in voltage amplitude are also noticeable, and in the photoelectric conversion device, variations occur in the peak value of the selection pulse. Such variation in the peak value of the selection pulse causes fixed pattern noise even if the variation in the parasitic capacitance of the cell selection thin film transistor is small.

When the thin film transistor is turned on, direct current consumption flows, power consumption is large, and temperature rise is large due to heat generation. In particular, when the semiconductor thin film used for the thin film transistor is amorphous, the electrical characteristics of the transistor change due to temperature change due to uneven crystallinity, and the drive circuit becomes inoperable. There is a possibility that it will be reached, and the reliability is poor.

Therefore, the present invention solves the above-mentioned problems, and an object thereof is to realize a suitable thin film transistor structure when the driver circuit is formed of thin film transistors.

[0008]

Means for Solving the Problems In order to solve the above problems, the means taken by the present invention uses a polycrystalline silicon thin film having a complementary structure of a thin film transistor and an intrinsic semiconductor channel region. There is a point.
That is, the present invention provides a driver circuit using a complementary transistor including a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor, in which P
Type insulated gate field effect transistor and N type insulated gate field effect transistor are both thin film transistors including source, drain and channel regions formed in a polycrystalline silicon thin film on an insulator. The drain region is a P-type impurity doped region, the source and drain regions of the N-type thin film transistor are N-type impurity doped regions, and the P-type thin film transistor and the N-type thin film transistor channel regions are not doped with impurities. Is characterized in that.

[0009]

Although the voltage amplification factor of the thin film transistor is generally small, since the driver circuit according to the present invention has a CMOS structure including a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor, the driver output The voltage amplitude can be always swung to the power supply voltage range, and the fluctuation of the voltage amplitude can be eliminated. Therefore, a large noise margin can be secured. As a result, the circuit operation can be assured even if a small defect occurs in the integrated circuit pattern in the manufacturing process, and the yield can be improved. In other words, the driver circuit can be made into a thin film transistor and the integration can be enhanced only when the thin film transistor has a CMOS structure. Further, since the variation in voltage amplitude can be eliminated, the occurrence of fixed pattern noise can be suppressed even when applied to a scanning circuit of a solid-state image sensor, for example.

Since the source, drain, and channel regions are formed of a polycrystalline silicon thin film, their crystallinity is slightly incomplete, but there is no crystal irregularity as compared with the case of amorphous, and there is no electrical change due to temperature change. However, since the drive circuit is composed of a ratioless circuit in which a through current does not flow, direct current consumption does not flow and power consumption is very small. Therefore, the above temperature change can be suppressed.

Particularly, since the channel region is an intrinsic region which is not doped with impurities, the off current is set to the minimum. As a result, even when the thin film transistor is formed on an insulator having poor thermal conductivity, temperature rise is unlikely to occur, so the electrical characteristics do not change to a defect, and the circuit does not become inoperable. The reliability can be increased.

Furthermore, since the channel regions of the N-type and P-type thin film transistors are both intrinsic semiconductor regions which are not doped with impurities, the number of manufacturing steps can be reduced due to the simplification of the manufacturing process, and the load device and the driving device can be reduced. Since no electrical isolation from the element is required and only a selective mask for performing selective ion implantation once is required, the layout is free and the integration density can be increased.

[0013]

Reference Example First, before describing the embodiments of the present invention, a line sensor using a thin film transistor will be described as a reference example.

FIG. 1 is a block diagram showing the overall configuration of a line sensor to which a driver circuit is applied in the reference example. The line sensor is formed by arranging N bits of elements 8 in a line, and one element 8 includes a scan circuit 1, a switching circuit 2, and a photosensitive cell section 3. The scan circuit 1 is a shift register as shown in FIG. 2, and its outputs (Q _{1 to} Q _N ) are applied to the gate 5 of the switching transistor 4 in the switching circuit 2 to control the switching transistor 4 to be turned on / off. The amount of charge stored in the photosensitive cell unit 3 according to the amount of light is read out to the output line V _O when the switching transistor 4 is turned on. N-bit cells are sequentially read by the scan circuit 1 and appear on the output line V _O as serial data of each cell. As a result, it is converted into an amount of electricity proportional to the amount of light applied to each cell.

FIG. 2 is a specific circuit diagram of FIG. The scan circuit 1 is basically a shift register, for example, D
The flip-flops 12 are cascaded in N bits.
The scan data input terminal 11 is supplied with the scan data input signal D _IN , and the scan clock input terminal 10 is supplied with the scan clock input signal CL _IN . The switching circuit 2 is composed of a switching transistor 4 (13), and this transistor 13 is provided with thin film transistors for N bits. The photosensitive cell section 3 is composed of a parallel circuit of a photoelectric conversion element 14 and a capacitor 15.

FIG. 3 shows the operation waveform of each part of the line sensor. When the outputs Q _{1 to} Q _{N of} the shift register train are sequentially output, the switching transistor 4 (1
The charging current appears on the output line V _O in response to 3) being sequentially selected. Since this peak value corresponds to the light quantity of each cell, a signal level proportional to the light quantity can be obtained by passing it through a low-pass filter or a peak hold circuit.

FIG. 4 shows a semiconductor structure of the switching circuit and the photosensitive cell portion in the above line sensor, (B) is a plan view, and (A) is a sectional view showing a state cut along the line AB of (B). Is. First, a polycrystalline silicon thin film is deposited and patterned on a substrate 31 made of a material such as glass or ceramic to form a semiconductor thin film region of a source 34, a channel 33 and a drain 32.
After that, a gate insulating film 35 is formed by thermal oxidation or a CVD method, and a gate electrode material such as polycrystalline silicon is deposited and patterned to form a gate electrode 36. Then, P-type or N-type regions are formed as the source / drain electrodes 32 and 34 by self-alignment by the ion implantation method. After that, an interlayer insulating film, for example, a silicon oxide film 41 is formed by a CVD method, and then contact holes 37 and 43 are opened to form an Al wiring layer 38 to be an output line V _O and an Al layer 39 as a lower electrode of the photosensitive layer. To form. Then, a photoconductor layer 40 such as amorphous silicon is deposited on the entire surface by a plasma CVD method, and the photoconductor layer 40 is deposited thereon.
A transparent electrode layer 42 serving as an upper electrode is formed. Photoconductor layer 4
In the case of 0, the dark current is 1 pA or less in the state where light is not irradiated, and it is set to several pA / lx for light. This method is advantageous in that the photoconductor layer 40 is formed also as a capacitor. When amorphous silicon is used for the photoconductor layer 40, the dark current is very small and the photocurrent is large, so that it is suitable for an optical reading element.

FIG. 11 is a graph showing a typical example of the photosensitive characteristics of an amorphous silicon film. As can be seen from this graph, when an amorphous silicon film is used as the photoconductor layer 40, the illuminance of 1 lx (1 lux) or less is read and detected. can do. In addition, as shown in FIG.
If 0 is a vertical (membrane vertical) conductivity type, the photoconductor layer 40
Also, since the etching off of the upper electrode 42 is unnecessary, the simplicity of depositing the film is a manufacturing feature.

FIG. 5 shows another semiconductor structure of the switching circuit and the photosensitive cell portion in the above line sensor. In this semiconductor structure, the photoconductor layer uses a lateral (membrane horizontal) conductivity type. A silicon thin film for forming a thin film transistor and a capacitor is formed on the substrate 51 by the CVD method.
Next, an N or P type layer is formed on the lower electrode portion 54 of the charge storage capacitor by ion implantation, and then a gate electrode 56 of polycrystalline silicon or the like and an upper electrode 57 of the capacitor are formed. If you carry out ion implantation once,
By self-alignment, a switching thin film transistor portion including an N-type or P-type source region 52, a channel region 53 of an intrinsic region, a drain region 611, and a gate electrode 56 and a lower electrode 54, and a capacitor including an upper electrode 57 and an insulating film 55 are formed. To be done. After that, the interlayer insulating film 58 is deposited and then the contact holes 60, 61, 62 are opened, and the Al wiring 63 and the photoconductor layer 59 which become the output line V _O.
To form. The photoconductor layer 59 is a semiconductor material such as CdS or amorphous silicon that is sensitive to light, and is arranged in parallel with the capacitor. As a result, when the light is not irradiated, the photoconductor layer 59 has a very high resistance and does not discharge the electric charge accumulated in the capacitor, but when the light is irradiated, the electric charge of the capacitor is discharged. When the switching transistor is turned on, a charging current is generated, and as a result, the amount of light is converted into the amount of electricity. The features of the structure shown in FIG. 5 are that by using the photoconductor layer 59 as lateral conductivity, the upper and lower electrodes are not required, and even if there are many pinholes in the film, it can be used.

FIG. 6 is a circuit diagram showing still another configuration example of the switching circuit and the photosensitive cell section in the above line sensor. In this reference example, the thin film transistor 66 operates as a photoconductor. FIG. 12 shows the optical characteristics of the thin film transistor, and the photocurrent value can be controlled by the gate voltage V _G. FIG. 6 shows a state where V _G = 0 (load MOS state) as the simplest usage example. Transistor 6 here
Reference numeral 5 is a light-shielded thin film transistor, 67 is a gate electrode of a thin film transistor 66 that operates as a photoconductor, V _O is an output line, V _SS is a common potential, and Q _N is each output of a shift register array and is a gate of a switching thin film transistor 65. Applied to the electrodes.

FIG. 7 shows a semiconductor structure which realizes the circuit configuration of FIG. A first layer of a silicon thin film for forming a transistor is formed on a substrate 70 and then patterned, a gate insulating film 78 is formed thereon by a thermal oxidation method or the like, and then gate electrodes 76 and 77 are formed. Then, the source region 71, the channel region 72, the drain region 73, the photoconductor channel 74, and the fixed electrode 75 of the transistor are formed by self-alignment by the N-type or P-type ion implantation method. After that, the interlayer insulating film 79 is formed, and the contact holes 83, 84, 8 are formed.
After opening hole 5, an output line 80 made of an Al layer, a light shielding layer 81, and a fixed potential line 82 are formed. In such a structure, the photosensitive region is the channel 74 of the thin film transistor, and the capacitor uses the parasitic capacitance between the gate electrode 77 and the drain region 73 as it is.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A scan circuit as a driver circuit according to an embodiment of the present invention will be described below.

The driver circuit of this example is a scan circuit of the above-mentioned line sensor, and this scan circuit is required to have a certain high speed. For example, if the line sensor has 1000 elements and the read cycle is 1 msec, the scan speed is 1 MHz.
Therefore, the scan circuit requires a shift register that can operate at high speed and a transistor that constitutes the shift register.

FIG. 8 shows a CMOS in the embodiment of the present invention.
It is an example of a scan circuit having a (complementary MOS transistor) configuration, and shows a circuit configuration for one element of a line sensor. Here, φ is a positive phase clock input, Φ is a negative phase clock input, D is scan data input, and Q is scan data output. P-channel thin film transistor (P-TFT) 9
0-93 and N-channel thin film transistor (N-TFT)
94-97. The thin film transistors 91 and 94 are COS inverter circuits having a common gate electrode to which the scan data input D is applied. Between the P channel thin film transistor 91 and the power source, a P channel thin film transistor 90 controlled to open / close by a positive phase clock input φ is a totem. In addition to being pole-connected, an N-channel thin film transistor 95, whose opening and closing is controlled by a negative-phase clock input Φ, is totem-pole connected between the N-channel thin film transistor 94 and the ground power supply. The common drain of the thin film transistors 91 and 94 is connected to the gate of the COS inverter circuit composed of the thin film transistors 93 and 96. A P-channel thin film transistor 92, which is controlled to open / close by a negative-phase clock input Φ, is connected between the P-channel thin film transistor 93 and the power supply by a totem pole, and a positive-phase clock input is provided between the N-channel thin film transistor 96 and the ground power supply. An N-channel thin film transistor 97 whose opening and closing is controlled by φ is connected to a totem pole. First stage COS
The inverter circuit (thin film transistors 91 and 94) is powered on during the low level period of the positive phase clock input φ (the high level period of the negative phase clock input φ), and conversely the second stage CO
The S inverter circuit (thin film transistors 93 and 96) is in the high level period of the positive phase clock input φ (negative phase clock input φ
Power is activated during the low level period of. Therefore, when the scan data input D is input, a shift pulse having a pulse width corresponding to one cycle of the clock input is output from the scan data output Q.

FIG. 9 shows a semiconductor structure of the CMOS thin film transistor of FIG. In this semiconductor structure, the substrate 1
After the first layer of the silicon thin film 101 is formed on 00, the gate oxide film 102 is formed, and then the gate electrode 103 is formed. Next, boron ions are supplied to the P-channel thin film transistor 104 side, and N-channel thin film transistor 105
When phosphorus or arsenic ions are implanted on the side, each thin film transistor is formed by self-alignment. As described above, in the case of a CMOS thin film transistor (TFT), a CMOS can be formed from a mono-channel device (N-MOS or P-MOS) by simply adding an ion implantation step once as compared with a conventional image sensor using a single crystal wafer. Is a major feature. This is due in part to the fact that the intrinsic semiconductor regions containing no impurities are commonly used regardless of whether the channel regions are P-type or N-type.

By the way, when the thin film transistor is used as an analog switch, the ON current of the thin film transistor must be large and the OFF current must be small. On the other hand, when the drive circuit is a CMOS circuit of a thin film transistor, the ON current of the thin film transistor must be large, but the OFF current may be large to some extent. Therefore, it is preferable to use the CMOS circuit of the thin film transistor as the driving circuit in consideration of the advantages of the manufacturing process. Here, when the impurity concentration of the channel region of the thin film transistor is zero,
When the source-to-source voltage is zero, the on-current becomes the minimum. The off current increases regardless of whether the impurity concentration is inclined to P-type or N-type. If the channel region is not made intrinsic, the off current will increase due to slight PN variations in manufacturing, but as in this example, the off current is minimized by setting the channel region as an intrinsic region without impurity doping. be able to.

A thin film transistor (TFT) is required to have high speed in both a scan circuit and a switching transistor, and further, it is necessary to improve the transistor characteristics. Here, if a thermal oxide film is used as the gate insulating film as an example of the process of forming the transistor portion, good transistor characteristics can be obtained. A silicon thin film which does not contain impurities forming the channel portion and the source / drain of the first layer is formed at a deposition temperature of 570 ° C by a low pressure CVD method at about 2000 to 5000Å, and after patterning, 1100 ° C to 1150 ° C. When a thermal oxidation process is performed in C in an O ₂ atmosphere, a good gate insulating film 102 of 1500 Å is formed, and at the same time, grains (crystal grains) of the silicon thin film 101 of the first layer grow and a good amount of Become crystalline.

After that, a gate electrode of N ⁺ -doped polycrystalline silicon is formed, and then P ions are implanted with a dose amount of 1 × 10 ¹⁵ / cm ^{2 using} the gate electrode as a mask, so that only the channel is not doped with impurities. It remains as an intrinsic area. Thereafter, H ₂ plasma treatment is performed to further improve the characteristics. In the semiconductor structure shown in FIGS. 4 and 5, when amorphous silicon is used as the photoconductor film, when TF is carried out by hydrogen-based plasma CVD, TF
T is also automatically subjected to H ₂ plasma treatment. Further, the method of FIG. 7 can also be performed separately.

FIG. 10 shows the N obtained through the above manufacturing process.
It is a graph which shows the characteristic of a channel thin film transistor.
Since polycrystalline silicon is used as the semiconductor thin film, the channel carrier mobility is about 80 cm ² / V · sec.
Which is a good characteristic of about 1/5 of that of single crystal silicon. Further, the scan circuit constituted by using this thin film transistor operates at about 2 to 5 MHz, and sufficient high speed can be obtained. The switching speed of the switching transistor is 100 nsec.

[0030]

As described above, according to the present invention, the driver circuit is constituted by the CMOS circuit including the thin film transistors, and the channel regions in the polycrystalline semiconductor thin films of the P-type and N-type thin film transistors are not intrinsically doped with impurities. Since the feature is the point set as the region, the following effects are obtained.

Although the voltage amplification factor of the thin film transistor is generally small, since it has a CMOS structure, the voltage amplitude of the drive output can be always set to the power supply voltage width, and furthermore, the variation in voltage amplitude can be eliminated. Therefore, the noise margin becomes large. As a result, the circuit operation can be surely performed even if the integrated circuit pattern has a slight defect, so that the yield can be improved.

Further, since variations in voltage amplitude can be eliminated, even when applied as a driver circuit to, for example, a scanning circuit of a solid-state image sensor, generation of fixed pattern noise can be suppressed.

Since the source, drain, and channel regions are formed of a polycrystalline silicon thin film, the crystallinity is slightly uneven, but there is no crystal unevenness as compared with the case of amorphous, and the electrical characteristics due to temperature change are large. Can be suppressed. Further, since the drive circuit is composed of the ratioless circuit in which the through current does not flow, the direct current consumption does not flow, and the power consumption is very small. Therefore, the above temperature change can be suppressed. In particular, since the channel region is an intrinsic region that is not doped with impurities, the off current is set to the minimum. As a result, even when the thin film transistor is formed on an insulator having poor thermal conductivity,
Since the temperature is unlikely to rise, the electrical characteristics do not change into a defect, the circuit does not become inoperable, and the reliability can be improved.

Furthermore, since the channel regions of the N-type and P-type thin film transistors are both intrinsic semiconductor regions that are not doped with impurities, the thin film transistor can be manufactured in a self-aligned manner, and the manufacturing cost can be reduced. The load element and the drive element do not need to be electrically separated, and in addition, a selective mask for performing selective ion implantation only once is required. Therefore, the layout is free and the integration density can be increased. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a line sensor as a reference example.

FIG. 2 is a specific circuit diagram of FIG.

FIG. 3 is a waveform diagram showing operation waveforms of respective parts of the line sensor of FIG.

4 shows a semiconductor structure of a switching circuit and a photosensitive cell section in the line sensor of FIG. 1, (b) is a plan view,
(A) is a sectional view showing a state of being cut along the line AB of (B).

5 shows another semiconductor structure of the switching circuit and the photosensitive cell section in the line sensor of FIG. 1, (b) is a plan view, and (a) shows a state cut along the CD line of (b). FIG.

FIG. 6 is a circuit diagram showing still another configuration example of a switching circuit and a photosensitive cell section in the line sensor of FIG.

FIG. 7 shows a semiconductor structure that realizes the circuit configuration of FIG.
(B) is a plan view and (A) is a cross-sectional view showing a state of being cut along the EF line of (B).

FIG. 8 shows a CMOS (complementary M type) according to an embodiment of the present invention.
OS transistor) configuration of the scan circuit,
It is a circuit diagram showing one element of a line sensor.

9 is a sectional view showing a semiconductor structure of the CMOS thin film transistor in FIG.

FIG. 10 is a graph showing a characteristic example of an N-channel thin film transistor used in an example of the present invention.

FIG. 11 is a graph showing optical characteristics of a photoconductor layer using amorphous silicon.

FIG. 12 is a graph showing optical characteristics when a thin film transistor is used as a photoconductor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/335 Z

Claims (1)

[Claims] 1. A driver circuit using a complementary transistor including a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor, wherein the P-type insulated gate field effect transistor and the N-type insulated gate are provided. type field effect transistor are both source formed on the polycrystalline silicon thin film on an insulator, with a thin film transistor of the drain and the channel region, the source and drain regions of the P-type thin film transistor is a doped region of the P-type impurity The source and drain regions of the N-type thin film transistor are N-type impurity doped regions, and the channel regions of the P-type thin film transistor and the N-type thin film transistor are intrinsic semiconductor regions that are not doped with impurities. Driver circuit using.