JPH07109938B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JPH07109938B2 JPH07109938B2 JP10501993A JP10501993A JPH07109938B2 JP H07109938 B2 JPH07109938 B2 JP H07109938B2 JP 10501993 A JP10501993 A JP 10501993A JP 10501993 A JP10501993 A JP 10501993A JP H07109938 B2 JPH07109938 B2 JP H07109938B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring board
- wiring
- manufacturing
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000919 ceramic Substances 0.000 claims description 18
- 239000006089 photosensitive glass Substances 0.000 claims description 17
- 229920001721 polyimide Polymers 0.000 claims description 11
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000009719 polyimide resin Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層配線基板の製造方法
に関し、特に超大型コンピュータ等に実装されるマルチ
チップモジュールのセラミック基板をベースとした多層
配線基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer wiring board, and more particularly to a method for manufacturing a multi-layer wiring board based on a ceramic substrate of a multi-chip module mounted on a super-large computer or the like.
【０００２】[0002]
【従来の技術】従来、この種の多層配線基板にあって
は、装置の処理能力の高速化を達成すべく配線の高速化
を高密度化に対する努力がなされている。高速化につい
ては、誘電率の低い有機樹脂等を絶縁材に用いたり、銅
等の低抵抗の導電材を使用したりすることが行われてい
る。また、高密度化については、配線パターンの微細
化，あるいは配線層の高多層化が進められている。2. Description of the Related Art Conventionally, in this type of multilayer wiring board, efforts have been made to increase the speed of wiring and to increase the density thereof in order to increase the processing capacity of the device. For speeding up, an organic resin or the like having a low dielectric constant is used as an insulating material, or a conductive material having a low resistance such as copper is used. In order to increase the density, finer wiring patterns or higher wiring layers are being advanced.
【０００３】しかしながら、導体抵抗の問題で配線パタ
ーンの微細化には限界があり、高多層化は、有機樹脂を
絶縁材に使用した場合、配線パターンと絶縁膜とを交互
に形成して多層化していく関係上、多層になる程製造日
数が多くなるという問題を有している。However, there is a limit to the miniaturization of wiring patterns due to the problem of conductor resistance, and in order to achieve a high multilayer structure, when an organic resin is used as an insulating material, wiring patterns and insulating films are alternately formed to form a multilayer structure. Therefore, there is a problem that the number of manufacturing days increases as the number of layers increases.
【０００４】上記問題を解決するために、特開昭６３−
５００９４号公報に開示の多層配線基板の製造方法があ
る。この方法では、図５に示す如く、多層回路基板をセ
ラミック積層配線基板１７を有する下層部用の第１の配
線基板ブロック１０と、金属板としてアルミニウム板３
０を有する上層部用の第２の配線基板ブロック４０とに
予め分割している。In order to solve the above problems, Japanese Patent Laid-Open No. 63-
There is a method for manufacturing a multilayer wiring board disclosed in Japanese Patent Publication No. 50094. In this method, as shown in FIG. 5, a multilayer circuit board is used as a first wiring board block 10 for a lower layer portion having a ceramic laminated wiring board 17, and an aluminum plate 3 as a metal plate.
And a second wiring board block 40 for the upper layer portion having 0.
【０００５】第１の配線基板ブロック１０においては、
セラミック基板１７上に第１の配線層１８を選択的に形
成し、これを覆う第１のポリイミド樹脂絶縁層１９を形
成し、その上に第２の配線２１を形成する。続いて第２
のポリイミド樹脂絶縁層２２をその上に形成し、更に第
３の配線層２３を形成する。更に続いて、第３のポリイ
ミド樹脂絶縁層２４をその上に形成し、最後に金パット
２５と第４の配線層２６とを形成する。In the first wiring board block 10,
The first wiring layer 18 is selectively formed on the ceramic substrate 17, the first polyimide resin insulating layer 19 covering the same is formed, and the second wiring 21 is formed thereon. Then the second
The polyimide resin insulating layer 22 is formed thereon, and the third wiring layer 23 is further formed. Further subsequently, a third polyimide resin insulating layer 24 is formed thereon, and finally a gold pad 25 and a fourth wiring layer 26 are formed.
【０００６】次に、アルミニウム板３０の表面に金パッ
ド３１を形成した後に第４のポリイミド樹脂絶縁層３２
を形成し、続いて第４の配線層３３，第５のポリイミド
樹脂絶縁層３４，第５の配線層３５，第６のポリイミド
樹脂絶縁層３６をこの順に形成する。そして、最後に金
パッド３７をその上に形成する。Next, after forming the gold pad 31 on the surface of the aluminum plate 30, the fourth polyimide resin insulating layer 32 is formed.
Then, a fourth wiring layer 33, a fifth polyimide resin insulating layer 34, a fifth wiring layer 35, and a sixth polyimide resin insulating layer 36 are formed in this order. And finally, the gold pad 37 is formed thereon.
【０００７】次に、アルミニウム板３０を希塩酸で溶解
除去して第２の配線基板ブロック４０を得る。次の工程
では、ブロック１０と４０との金パッド２５と３１とを
互いに当接させつつ金―エポキシ系接着剤を用いて接着
することにより、第１の配線層１８から表層の金パッド
３７までの合計７層の配線層を有する多層回路基板を得
るようになっている。Next, the aluminum plate 30 is dissolved and removed with dilute hydrochloric acid to obtain a second wiring board block 40. In the next step, the gold pads 25 and 31 of the blocks 10 and 40 are brought into contact with each other and adhered using a gold-epoxy adhesive so that the first wiring layer 18 to the surface gold pad 37 are bonded. In this way, a multilayer circuit board having a total of 7 wiring layers is obtained.
【０００８】[0008]
【発明が解決しようとする課題】この図５に示した製造
方法では、第２の配線基板ブロック４０の金属板３０
（アルミニウム板）を希塩酸により溶解した後に、第１
の配線基板ブロック１０と接着を行うようになってい
る。この金属板３０を溶解除去した後の多層配線膜は数
＋〜数百μｍの厚さしかないために、第１の配線基板ブ
ロック１０との接着作業が非常に困難になるという欠点
がある。In the manufacturing method shown in FIG. 5, the metal plate 30 of the second wiring board block 40 is used.
After dissolving (aluminum plate) with dilute hydrochloric acid,
The wiring board block 10 is bonded. Since the multilayer wiring film after the metal plate 30 is dissolved and removed has a thickness of several + to several hundreds of μm, there is a drawback that the bonding work with the first wiring board block 10 becomes very difficult.
【０００９】そこで、この金属板３０を残したままの状
態で第１の配線基板ブロック１０と接着を行うと、セラ
ミック基板１７と金属板３０との熱膨脹係数が大きく異
なるので、加熱処理して接着する際に大きな応力が発生
してセラミック基板がその応力に耐えられずに破壊する
という危険がある。Therefore, if the first wiring board block 10 is adhered with the metal plate 30 left as it is, the thermal expansion coefficient of the ceramic substrate 17 and the metal plate 30 are greatly different. When doing so, there is a risk that a large stress is generated and the ceramic substrate cannot withstand the stress and is destroyed.
【００１０】金属板の代りにセラミック基板を用いれ
ば、熱膨脹係数は等しくなって上述した接着時の基板破
壊を生じないが、その後セラミック基板を溶解除去する
ことは極めて困難である。機械的に除去することも考え
られるが、多層配線部に影響を与えずに除去することは
精度的に不可能である。If a ceramic substrate is used instead of a metal plate, the coefficients of thermal expansion will be equal and the above-mentioned substrate breakage during bonding will not occur, but it is extremely difficult to dissolve and remove the ceramic substrate thereafter. Although mechanical removal may be considered, it is not possible to remove accurately without affecting the multi-layer wiring part.
【００１１】本発明の目的は、配線基板を複数ブロック
に分割してこれ等ブロックを接着して多層配線基板を得
る際に、ブロック同士の接着作業性を良好とした多層配
線基板の製造方法を提供することである。An object of the present invention is to provide a method for manufacturing a multi-layer wiring board in which the workability of adhering the blocks to each other is improved when the wiring board is divided into a plurality of blocks and these blocks are adhered to obtain a multi-layer wiring board. Is to provide.
【００１２】[0012]
【課題を解決するための手段】本発明によれば、セラミ
ック基板上に複数の配線層を絶縁層を介して順次積層し
て構成される多層配線基板の製造方法であって、前記セ
ラミック基板上に配線層を形成し、この配線層上に選択
的に導体接続のための接続部材を、残余の部分に絶縁性
の接着剤層を夫々形成する第１の工程と、感光性ガラス
板上に配線層を形成し、この配線層上に選択的に導体接
続のための接続部材を、残余の部分に絶縁性の接着剤層
を夫々形成する第２の工程と、前記セラミック基板上の
接続部材と前記感光性ガラス板上の接続部材とを互いに
当接せしめつつ加熱により前記接着剤層の接着処理を行
う第３の工程と、この第３の工程後に前記感光性ガラス
を除去する第４の工程とを含むことを特徴とする多層配
線基板の製造方法が得られる。According to the present invention, there is provided a method of manufacturing a multilayer wiring board, which is formed by sequentially laminating a plurality of wiring layers on a ceramic substrate with an insulating layer interposed therebetween. Forming a wiring layer on the wiring layer, forming a connecting member for selectively connecting conductors on the wiring layer, and an insulating adhesive layer on the remaining portion, respectively; A second step of forming a wiring layer, selectively forming a connecting member for conductor connection on the wiring layer, and an insulating adhesive layer on the remaining portion, and a connecting member on the ceramic substrate And a connecting member on the photosensitive glass plate are brought into contact with each other, and a third step of performing an adhesive treatment of the adhesive layer by heating, and a fourth step of removing the photosensitive glass after the third step. And a method for manufacturing a multilayer wiring board, the method including: Obtained.
【００１３】[0013]
【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１４】図１〜図４は本発明の実施例の製造工程順
の断面図である。先ず、図１に示す様に第１の配線基板
ブロック１００を形成する。セラミック基板１上に第１
の配線層２を金めっきで選択的に形成し、これを覆う第
１のポリイミド樹脂絶縁層３をこれまた選択的に形成
し、その上に第２の配線層４を金めっきで選択的に形成
する。1 to 4 are sectional views in the order of manufacturing steps of an embodiment of the present invention. First, as shown in FIG. 1, the first wiring board block 100 is formed. First on ceramic substrate 1
Wiring layer 2 is selectively formed by gold plating, a first polyimide resin insulating layer 3 that covers the wiring layer 2 is selectively formed, and a second wiring layer 4 is selectively formed thereon by gold plating. Form.
【００１５】更に、その上にブロック同士を接着するた
めのポリイミド系接着剤層５を形成し、第２の配線層４
の所定位置に導体接続のための半田バンプを選択的に形
成して第１のブロック１００を得る。Further, a polyimide adhesive layer 5 for adhering the blocks to each other is formed thereon, and the second wiring layer 4 is formed.
Solder bumps for connecting conductors are selectively formed at predetermined positions of the first block 100 to obtain the first block 100.
【００１６】これに平行して、第２に示す様な第２の配
線基板ブロック２００を形成する。感光性ガラス板１１
上に第４の配線層となる配線層１２を金めっきで選択的
に形成し、これを覆う第４の絶縁層となるポリイミド樹
脂絶縁層１３を選択的に形成する。更にその上に第３の
配線層となる配線層１４をこれまた金めっきで選択的に
形成する。In parallel with this, a second wiring board block 200 as shown in the second is formed. Photosensitive glass plate 11
A wiring layer 12 serving as a fourth wiring layer is selectively formed thereon by gold plating, and a polyimide resin insulating layer 13 serving as a fourth insulating layer that covers the wiring layer 12 is selectively formed. Further thereon, the wiring layer 14 to be the third wiring layer is selectively formed by gold plating.
【００１７】その上に、ブロック同士を接着するめたの
ポリイミド系接着剤層１５を形成する。そして、第３の
配線層１４の所定位置に導体接続のための半田バンプ１
６を選択的に形成して第２のブロック２００を得る。A polyimide-based adhesive layer 15 for adhering the blocks to each other is formed thereon. Then, the solder bump 1 for connecting the conductor is provided at a predetermined position of the third wiring layer 14.
6 is selectively formed to obtain the second block 200.
【００１８】こうして得られた２つのブロック１００，
２００同士を、図３に示す如く互いの半田バンプ６と１
６とが当接し合う様に位置決めした後、真空熱プレス処
理を行って接着剤５，１５同士を貼り合せると共に、半
田バンプは半田付けする。The two blocks 100 thus obtained,
200 to each other as shown in FIG.
After positioning so that they contact each other, a vacuum hot press process is performed to bond the adhesives 5 and 15 together, and the solder bumps are soldered.
【００１９】感光性ガラス１１の熱膨脹係数は約８×１
０-6／℃であり、セラミック基板の熱膨脹係数は約５×
１０-6／℃であることから、両者の熱膨脹係数は近似し
ている。従って、熱処理による接着時に、セラミック基
板や感光性ガラスが破壊することはない。The coefficient of thermal expansion of the photosensitive glass 11 is about 8 × 1.
A 0 -6 / ° C., the thermal expansion coefficient of the ceramic substrate was about 5 ×
Since they are 10 −6 / ° C., the thermal expansion coefficients of the two are similar. Therefore, the ceramic substrate and the photosensitive glass are not destroyed during the bonding by heat treatment.
【００２０】また、この接着の際、対２のブロック２０
０は仮の支持基板として感光性ガラス１１を付けたまま
の状態であるために、従来の様に、極めて薄い多層配線
膜（支持基板を有さない）のみで、位置決めから接着ま
での作業を行う必要がなく、接着作業が容易になるので
ある。At the time of this bonding, the block 20 of the pair 2 is used.
Since 0 is a state in which the photosensitive glass 11 is still attached as a temporary support substrate, the work from positioning to bonding is performed only with an extremely thin multilayer wiring film (without a support substrate) as in the past. There is no need to perform it, and the bonding work becomes easy.
【００２１】次に、図４に示す様に、感光性ガラス板１
１を除去する。この除去方法としては、感光性ガラスは
紫外線にさらされると特性が変化して酸に容易に溶解す
るようになる性質を利用する。すなわち、感光性ガラス
板１１に紫外線を照射してその後酸処理を行うことで、
溶解除去が可能になる。Next, as shown in FIG. 4, the photosensitive glass plate 1
Remove 1. As a method of removing this, the property that the photosensitive glass changes its characteristics when exposed to ultraviolet rays and easily dissolves in an acid is used. That is, by irradiating the photosensitive glass plate 11 with ultraviolet rays and then performing acid treatment,
It can be dissolved and removed.
【００２２】以上は２つのブロックに分割した場合の例
であるが、３つ以上のブロックに分割しても良い。この
場合、図１の第１のブロックの形成と平行して図２のブ
ロックを複数個形成する。そして、第１のブロックと第
２のブロックを接着して感光性ガラスを除去した後、第
３ブロックを更に接着する。そして、第３ブロックの感
光性ガラスを除去して、更に第４のブロックを接着す
る。以上の処理を繰返せば、多層配線基板が、容易にか
つ製造日数が短くてでき上がることになる。The above is an example of division into two blocks, but it may be divided into three or more blocks. In this case, a plurality of blocks of FIG. 2 are formed in parallel with the formation of the first block of FIG. Then, the first block and the second block are adhered to remove the photosensitive glass, and then the third block is further adhered. Then, the photosensitive glass of the third block is removed, and the fourth block is further bonded. By repeating the above process, a multilayer wiring board can be easily manufactured in a short number of manufacturing days.
【００２３】[0023]
【発明の効果】叙上の如く、本発明によれば、第１の配
線基板ブロックのセラミック基板と略同一の熱膨脹係数
を有する感光性ガラスを第２の配線基板ブロックの基板
として用いているので、２のつブロックを熱処理により
接着する際には基板を除去することなく接着できるの
で、ブロック接着時の作業性が容易になるという効果が
ある。As described above, according to the present invention, the photosensitive glass having substantially the same thermal expansion coefficient as the ceramic substrate of the first wiring board block is used as the substrate of the second wiring board block. Since the two blocks can be bonded by heat treatment without removing the substrate, there is an effect that workability at the time of block bonding is facilitated.
【図１】本発明の実施例の一工程における第１の配線基
板ブロックを形成する方法を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a method of forming a first wiring board block in a step of an embodiment of the present invention.
【図２】本発明の実施例の一工程における第２の配線基
板ブロックを形成する方法を説明する断面図である。FIG. 2 is a cross-sectional view illustrating a method of forming a second wiring board block in one step of the embodiment of the present invention.
【図３】本発明の実施例の一工程における第１，第２の
ブロックを接着する際の断面図である。FIG. 3 is a cross-sectional view when adhering the first and second blocks in one step of the embodiment of the present invention.
【図４】本発明の実施例により得られた多層配線基板の
断面構造を示す図である。FIG. 4 is a diagram showing a cross-sectional structure of a multilayer wiring board obtained according to an example of the present invention.
【図５】従来の多層配線基板の構造方法を説明する断面
図である。FIG. 5 is a cross-sectional view illustrating a conventional method for constructing a multilayer wiring board.
１ セラミック基板 ２ 第１の配線層 ３ 第１の絶縁層 ４ 第２の配線層 ５ 第３の絶縁層としての接着剤 ６ 半田バンプ １１ 感光性ガラス １２ 第４の配線層 １３ 第４の絶縁層 １４ 第３の配線層 １５ 第３の絶縁層としての接着剤 １６ 半田バンプ １００ 第１の配線基板ブロック ２００ 第２の配線基板ブロック 1 Ceramic Substrate 2 First Wiring Layer 3 First Insulating Layer 4 Second Wiring Layer 5 Adhesive as Third Insulating Layer 6 Solder Bump 11 Photosensitive Glass 12 Fourth Wiring Layer 13 Fourth Insulating Layer 14 Third Wiring Layer 15 Adhesive as Third Insulating Layer 16 Solder Bump 100 First Wiring Board Block 200 Second Wiring Board Block
Claims (4)
層を介して順次積層して構成される多層配線基板の製造
方法であって、前記セラミック基板上に配線層を形成
し、この配線層上に選択的に導体接続のための接続部材
を、残余の部分に絶縁性の接着剤層を夫々形成する第１
の工程と、感光性ガラス板上に配線層を形成し、この配
線層上に選択的に導体接続のための接続部材を、残余の
部分に絶縁性の接着剤層を夫々形成する第２の工程と、
前記セラミック基板上の接続部材と前記感光性ガラス板
上の接続部材とを互いに当接せしめつつ加熱により前記
接着剤層の接着処理を行う第３の工程と、この第３の工
程後に前記感光性ガラスを除去する第４の工程とを含む
ことを特徴とする多層配線基板の製造方法。1. A method for manufacturing a multi-layer wiring board, which is formed by sequentially laminating a plurality of wiring layers on a ceramic substrate with an insulating layer interposed between the wiring layers, the wiring layer being formed on the ceramic substrate. Firstly, a connecting member for selectively connecting a conductor is formed on the upper part, and an insulating adhesive layer is formed on the remaining part.
And the step of forming a wiring layer on the photosensitive glass plate, and selectively forming a connecting member for conductor connection on the wiring layer and an insulating adhesive layer on the remaining portion. Process,
A third step of adhering the adhesive layer by heating while bringing the connecting member on the ceramic substrate and the connecting member on the photosensitive glass plate into contact with each other, and the photosensitive layer after the third step. A fourth step of removing glass, the method for manufacturing a multilayer wiring board.
返して前記セラミック基板上に多層の配線層を形成する
ことを特徴とする請求項１記載の多層配線基板の製造方
法。2. The method for manufacturing a multilayer wiring board according to claim 1, wherein a multilayer wiring layer is formed on the ceramic substrate by repeating the second step to the fourth step.
ラスに紫外線を照射し、しかる後に前記感光性ガラスを
酸にて溶解除去するようにしたことを特徴とする請求項
１または２記載の多層配線基板の製造方法。3. The method according to claim 1 or 2, wherein in the fourth step, the photosensitive glass is irradiated with ultraviolet rays, and then the photosensitive glass is dissolved and removed with an acid. Manufacturing method of multilayer wiring board.
ド系のものであることを特徴とする請求項１，２または
３記載の多層配線基板の製造方法。4. The method of manufacturing a multilayer wiring board according to claim 1, wherein both the insulating layer and the adhesive layer are made of polyimide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10501993A JPH07109938B2 (en) | 1993-04-07 | 1993-04-07 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10501993A JPH07109938B2 (en) | 1993-04-07 | 1993-04-07 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06296081A JPH06296081A (en) | 1994-10-21 |
| JPH07109938B2 true JPH07109938B2 (en) | 1995-11-22 |
Family
ID=14396355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10501993A Expired - Fee Related JPH07109938B2 (en) | 1993-04-07 | 1993-04-07 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07109938B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2697661B2 (en) * | 1995-03-17 | 1998-01-14 | 日本電気株式会社 | Manufacturing method of polyimide multilayer wiring board |
| JP3961537B2 (en) | 2004-07-07 | 2007-08-22 | 日本電気株式会社 | Manufacturing method of semiconductor mounting wiring board and manufacturing method of semiconductor package |
| KR102271665B1 (en) * | 2019-04-10 | 2021-07-01 | 주식회사 디아이티 | Multi layer ceramic substrate with improved interlayer conductivity and method of manufacturing the same |
-
1993
- 1993-04-07 JP JP10501993A patent/JPH07109938B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06296081A (en) | 1994-10-21 |
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